From mboxrd@z Thu Jan 1 00:00:00 1970 From: Marek Vasut Date: Thu, 11 Dec 2014 13:53:15 +0100 Subject: [U-Boot] [PULL] u-boot-socfpga/master Message-ID: <201412111353.15992.marex@denx.de> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de Hi Tom, below is the stuff I had stashed in a tree for a while now. All of the cadence stuff was sent way before RC1 and stabilized just after RC1 was out, yet I was not able to get it out earlier. The stuff from Ding are fixes, which were sent after RC2. All of this is contained to socfpga, so I believe it's fine to apply even now. The following changes since commit 97cdf64026c7d749dd7a5c0dbaba7a60a7292ac9: Merge branch 'sandbox' of git://git.denx.de/u-boot-x86 (2014-12-04 09:24:05 -0500) are available in the git repository at: git://git.denx.de/u-boot-socfpga.git master for you to fetch changes up to b9b5cf0ea3c5c141f31cc0c4c8edebbfd9ff5866: socfpga: correctly increment freeze_controller_base address (2014-12-06 13:53:57 +0100) ---------------------------------------------------------------- Dinh Nguyen (3): arm: socfpga: set skew settings for ethernet phy socfpga: add missing struct member fifo_triple_byte socfpga: correctly increment freeze_controller_base address Stefan Roese (15): arm: socfpga: Add myself as maintainer for the SoCrates board arm: socfpga: dts: Move to SPDX license identifiers spi: Add Cadence QSPI DM driver used by SoCFPGA arm: socfpga: dts: Add Cadence QSPI DT node to socfpga.dtsi arm: socfpga: dts: Add spi0 alias for Cadence QSPI driver arm: socfpga: Add Cadence QSPI support to config header spi: Add designware master SPI DM driver used on SoCFPGA arm: socfpga: dts: Add spi0/1 dts nodes for the Designware master SPI devices arm: socfpga: dts: socrates: Add spi1/2 aliases needed DM SPI probing arm: socfpga: Add Designware (DW) SPI support to config header arm: socfpga: dts: altr,rst-mgr.h: Move to SPDX license identifiers arm: socfpga: Use only one clrbits_le32 call to deassert SPI reset bits arm: socfpga: Add missing DW master SPI clock prototyp to clock_manager.h spi: designware_spi: Some fixes / changes arm: socfpga: DW_SPI: Remove clock info from config header arch/arm/cpu/armv7/socfpga/freeze_controller.c | 6 +- arch/arm/cpu/armv7/socfpga/reset_manager.c | 4 +- arch/arm/dts/socfpga.dtsi | 56 ++++-- arch/arm/dts/socfpga_cyclone5.dtsi | 13 +- arch/arm/dts/socfpga_cyclone5_socrates.dts | 39 ++-- arch/arm/include/asm/arch-socfpga/clock_manager.h | 1 + arch/arm/include/asm/arch-socfpga/freeze_controller.h | 1 - arch/arm/include/asm/arch-socfpga/scan_manager.h | 1 + board/altera/socfpga/MAINTAINERS | 5 + board/altera/socfpga/socfpga_cyclone5.c | 16 ++ drivers/spi/Makefile | 2 + drivers/spi/cadence_qspi.c | 345 ++++++++++++++++++++++++++++++++ drivers/spi/cadence_qspi.h | 76 ++++++++ drivers/spi/cadence_qspi_apb.c | 898 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ drivers/spi/designware_spi.c | 426 ++++++++++++++++++++++++++++++++++++++++ include/configs/socfpga_common.h | 33 +++- include/dt-bindings/reset/altr,rst-mgr.h | 9 +- 17 files changed, 1879 insertions(+), 52 deletions(-) create mode 100644 drivers/spi/cadence_qspi.c create mode 100644 drivers/spi/cadence_qspi.h create mode 100644 drivers/spi/cadence_qspi_apb.c create mode 100644 drivers/spi/designware_spi.c