From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:51398) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Y1uu5-00085k-T4 for qemu-devel@nongnu.org; Fri, 19 Dec 2014 05:35:32 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Y1utz-0003eT-Ge for qemu-devel@nongnu.org; Fri, 19 Dec 2014 05:35:25 -0500 Date: Fri, 19 Dec 2014 18:20:10 +0800 From: Fam Zheng Message-ID: <20141219102010.GA5569@fam-t430.nay.redhat.com> References: <1418920477-11669-1-git-send-email-tommusta@gmail.com> <1418920477-11669-10-git-send-email-tommusta@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1418920477-11669-10-git-send-email-tommusta@gmail.com> Subject: Re: [Qemu-devel] [PATCH 9/9] target-ppc: Introduce Privileged TM Noops List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Tom Musta Cc: qemu-ppc@nongnu.org, qemu-devel@nongnu.org, agraf@suse.de On Thu, 12/18 10:34, Tom Musta wrote: > Add the supervisory Transactional Memory instructions treclaim. and > trechkpt. The implementation is a degenerate one that simply > checks privileged state, TM availability and then sets CR[0] to > 0b0000, just like the unprivileged noops. And also s-o-b for this :) Fam > --- > target-ppc/translate.c | 38 ++++++++++++++++++++++++++++++++++++++ > 1 files changed, 38 insertions(+), 0 deletions(-) > > diff --git a/target-ppc/translate.c b/target-ppc/translate.c > index a3c79a6..b4a4297 100644 > --- a/target-ppc/translate.c > +++ b/target-ppc/translate.c > @@ -9691,6 +9691,40 @@ static void gen_tcheck(DisasContext *ctx) > tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0x8); > } > > +#if defined(CONFIG_USER_ONLY) > +#define GEN_TM_PRIV_NOOP(name) \ > +static inline void gen_##name(DisasContext *ctx) \ > +{ \ > + gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); \ > +} > + > +#else > + > +#define GEN_TM_PRIV_NOOP(name) \ > +static inline void gen_##name(DisasContext *ctx) \ > +{ \ > + if (unlikely(ctx->pr)) { \ > + gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); \ > + return; \ > + } \ > + if (unlikely(!ctx->tm_enabled)) { \ > + gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \ > + return; \ > + } \ > + /* Because tbegin always fails, the implementation is \ > + * simple: \ > + * \ > + * CR[0] = 0b0 || MSR[TS] || 0b0 \ > + * = 0b0 || 0b00 | 0b0 \ > + */ \ > + tcg_gen_movi_i32(cpu_crf[0], 0); \ > +} > + > +#endif > + > +GEN_TM_PRIV_NOOP(treclaim); > +GEN_TM_PRIV_NOOP(trechkpt); > + > static opcode_t opcodes[] = { > GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE), > GEN_HANDLER(cmp, 0x1F, 0x00, 0x00, 0x00400000, PPC_INTEGER), > @@ -11122,6 +11156,10 @@ GEN_HANDLER2_E(tsr, "tsr", 0x1F, 0x0E, 0x17, 0x03DFF800, \ > PPC_NONE, PPC2_TM), > GEN_HANDLER2_E(tcheck, "tcheck", 0x1F, 0x0E, 0x16, 0x007FF800, \ > PPC_NONE, PPC2_TM), > +GEN_HANDLER2_E(treclaim, "treclaim", 0x1F, 0x0E, 0x1D, 0x03E0F800, \ > + PPC_NONE, PPC2_TM), > +GEN_HANDLER2_E(trechkpt, "trechkpt", 0x1F, 0x0E, 0x1F, 0x03FFF800, \ > + PPC_NONE, PPC2_TM), > }; > > #include "helper_regs.h" > -- > 1.7.1 > >