From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:38994) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Y86gv-0000jg-8S for qemu-devel@nongnu.org; Mon, 05 Jan 2015 07:23:26 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Y86gs-0001kL-0m for qemu-devel@nongnu.org; Mon, 05 Jan 2015 07:23:25 -0500 Received: from mx1.redhat.com ([209.132.183.28]:50366) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Y86gr-0001kG-QA for qemu-devel@nongnu.org; Mon, 05 Jan 2015 07:23:21 -0500 Date: Mon, 5 Jan 2015 17:53:15 +0530 From: Amit Shah Message-ID: <20150105122315.GH4609@grmbl.mre> References: <54918054.8070500@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <54918054.8070500@gmail.com> Subject: Re: [Qemu-devel] [PATCH 1/1] ich9: add disable_s3, disable_s4, s4_val properties List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Marcel Apfelbaum Cc: Paolo Bonzini , "Michael S. Tsirkin" , qemu list , Igor Mammedov On (Wed) 17 Dec 2014 [15:08:36], Marcel Apfelbaum wrote: > On 12/16/2014 01:23 PM, Amit Shah wrote: > >PIIX4 has disable_s3 and disable_s4 properties to enable or disable PM > >functions. Add such properties to the ICH9 chipset as well for the Q35 > >machine type. > > > >S3 / S4 are not guaranteed to always work (needs work in the guest as > >well as QEMU for things to work properly), and disabling advertising of > >these features ensures guests don't go into zombie state if something > >isn't working right. > > > >The defaults are kept the same as in PIIX4: both S3 and S4 are enabled > >by default. > > > >These can be disabled via the cmdline: > > > > ... -global ICH9-LPC,disable_s3=1 -global ICH9-LPC,disable_s4=1 > Maybe we can add them to Q35 Machines instead? > - machine q35,disable_s3=1,disable_s4=1 The PM properties are chipset properties, aren't they? To make the change you requested, q35 will have to query the chipsets it supports, and set the properties for the chipset in use - not sure how that happens. I modeled this based on how i440fx works, so there's also the case for keeping things similar to an existing implementation... Amit