Re: [PATCH 5/9] drm/i915: don't set the FBC plane select bits on HSW+

[Daniel Vetter <daniel@ffwll.ch>]

On Tue, Dec 23, 2014 at 10:35:41AM -0200, Paulo Zanoni wrote:
> From: Paulo Zanoni <paulo.r.zanoni@intel.com>
> 
> This commit is just to make the intentions explicit: on HSW+ these
> bits are MBZ, but since we only support plane A and the macro
> evaluates to zero when plane A is the parameter, we're not fixing any
> bug.
> 
> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_fbc.c | 7 +++++--
>  1 file changed, 5 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_fbc.c b/drivers/gpu/drm/i915/intel_fbc.c
> index 83d3c8a..c6e688c 100644
> --- a/drivers/gpu/drm/i915/intel_fbc.c
> +++ b/drivers/gpu/drm/i915/intel_fbc.c
> @@ -258,12 +258,15 @@ static void gen7_fbc_enable(struct drm_crtc *crtc)
>  	struct drm_framebuffer *fb = crtc->primary->fb;
>  	struct drm_i915_gem_object *obj = intel_fb_obj(fb);
>  	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> -	u32 dpfc_ctl;
> +	u32 dpfc_ctl = 0;
>  	int threshold = dev_priv->fbc.threshold;
>  
>  	dev_priv->fbc.enabled = true;
>  
> -	dpfc_ctl = IVB_DPFC_CTL_PLANE(intel_crtc->plane);
> +
> +	if (IS_IVYBRIDGE(dev))

What about baytrail?
-Daniel

> +		dpfc_ctl |= IVB_DPFC_CTL_PLANE(intel_crtc->plane);
> +
>  	if (drm_format_plane_cpp(fb->pixel_format, 0) == 2)
>  		threshold++;
>  
> -- 
> 2.1.3
> 
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-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
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