[U-Boot] [PATCH 0/23] x86: Add bare support for Intel Minnowboard Max

[U-Boot] [PATCH 0/23] x86: Add bare support for Intel Minnowboard Max

[Simon Glass]

This series adds support for the Intel Minnowboard Max (called Minnowmax
for short). Along the way a few refactors and additions are made:

- The Intel Firmware Support Package support is moved from queensbay to a
common location
- PCI support for XHCI is added
- A few tweaks are made to the PCI support
- Support for the debug UART (early debug output) is provided
- The microcode tool now also supports reading in header files

This board has been lightly tested. The following seem to work:

- USB2 on the blue port (not USB3), e.g. for keyboard
- Ethernet
- HDMI out and console
- UART
- uSD card
- SPI

SATA is detected but I have not attached a drive to try it. USB3 shows signs
of life but does not detect a USB stick, and crashes when trying to use a
USB Ethernet adaptor.

For SPI some parts cannot be read and others cannot be written. This seems
to be a feature of the Intel hardware configuration. It may be possible to
fix this using the SPI registers but I cannot work out how / lost interest
trying. So far, addresses from 500000 to 700000 can be used.

I have not tried the ICH GPIO driver but it likely needs work before it will
function. I2C is not supported as there is currently no U-Boot driver for
this.

The zboot command can be used to start a bzImage kernel. Verified boot is
supported - use mkimage to sign images as described in this walk-through:
doc/uImage.FIT/beaglebone_vboot.txt

Boot time is grim:
- 1423ms to set up display (Intel FSP)
- 454ms to scan AHCI (when no devices are connected)
- ~1000ms to power up and start cache-as-RAM init (Intel FSP)
     (this is not benchmarked, may be inaccurate)
- ~950ms to set up memory and initial machine configuration (Intel FSP)
     (this is not benchmarked, may be inaccurate)

So it takes over 4 seconds to get to booting a kernel.

Implementing the Memory Reference Code (MRC) cache should improve this
slightly (perhaps a reduction of 500-1000ms). This cache is implemented for
ivybridge so that code needs to be moved into a generic x86 directory and
plumbed into the FSP code. This has not been done in this series. Also the
video and SATA/AHCI can be disabled if preferred.

It is also possible to run as a coreboot payload. See the instructions in
README.x86 for this. In this case video does not work since coreboot does
not pass through the VESA display information.

To support the single-core 1GB variant, changes would need to be made to
arch/x86/cpu/baytrail/fsp_configs.c to select different values for the
memory. The microcode update may need to change also.

This series is available at u-boot-x86 branch minnow-working.


Simon Glass (23):
  x86: Enhance the microcode tool to support header files as input
  pci: Add a function to find a device by class
  x86: pci: Add PCI IDs for Minnowboard Max
  x86: video: Enable video for Minnowboard Max
  usb: pci: Use pci_find_class() to find the device
  usb: pci: Add XHCI driver for PCI
  x86: Add an option to enabling building a ROM file
  x86: Make MMCONF_BASE_ADDRESS common across x86
  x86: video: Allow video ROM execution to fall back to the other method
  x86: bootstage: Add time measurement for vesa start-up
  x86: Move common FSP code into a common location
  x86: Adjust the FSP types slightly
  x86: Make CAR and DRAM FSP code common
  x86: Move common FSP functions into a common file
  x86: Remove unnecessary casts and fix comment typos
  x86: Allow FSP Kconfig settings for all x86
  x86: Define cache line size
  x86: Allow a UART to be set up before the FSP is ready
  x86: spi: Support ValleyView in ICH SPI driver
  scsi: bootstage: Measure time taken to scan the bus
  x86: Enable bootstage features
  x86: Add some documentation on how to port U-Boot on x86
  x86: Add support for Intel Minnowboard Max

 Makefile                                           |    5 +-
 arch/x86/Kconfig                                   |   62 +
 arch/x86/cpu/Makefile                              |    1 +
 arch/x86/cpu/baytrail/Kconfig                      |    9 +
 arch/x86/cpu/baytrail/Makefile                     |   10 +
 arch/x86/cpu/baytrail/early_uart.c                 |   82 +
 arch/x86/cpu/baytrail/fsp_configs.c                |  156 +
 arch/x86/cpu/baytrail/pci.c                        |   47 +
 arch/x86/cpu/baytrail/valleyview.c                 |   37 +
 arch/x86/cpu/ivybridge/gma.c                       |    3 +-
 arch/x86/cpu/queensbay/Kconfig                     |   38 -
 arch/x86/cpu/queensbay/Makefile                    |    4 +-
 arch/x86/cpu/queensbay/fsp_configs.c               |    2 +-
 arch/x86/cpu/queensbay/tnc.c                       |   29 +-
 arch/x86/cpu/queensbay/tnc_pci.c                   |   17 +-
 arch/x86/cpu/queensbay/topcliff.c                  |   32 +-
 arch/x86/dts/Makefile                              |    3 +-
 arch/x86/dts/microcode/m0130673322.dtsi            | 3284 ++++++++++++++++++++
 arch/x86/dts/minnowmax.dts                         |   45 +
 arch/x86/dts/serial.dtsi                           |    2 +-
 arch/x86/include/asm/arch-baytrail/fsp/azalia.h    |   39 +
 arch/x86/include/asm/arch-baytrail/fsp/fsp_vpd.h   |   95 +
 arch/x86/include/asm/arch-baytrail/gpio.h          |   13 +
 arch/x86/include/asm/arch-queensbay/fsp/fsp_vpd.h  |    2 -
 arch/x86/include/asm/cache.h                       |    2 +
 .../include/asm/{arch-queensbay => }/fsp/fsp_api.h |    6 +-
 .../asm/{arch-queensbay => }/fsp/fsp_bootmode.h    |    0
 .../include/asm/{arch-queensbay => }/fsp/fsp_ffs.h |    0
 .../include/asm/{arch-queensbay => }/fsp/fsp_fv.h  |    0
 .../include/asm/{arch-queensbay => }/fsp/fsp_hob.h |    0
 .../asm/{arch-queensbay => }/fsp/fsp_infoheader.h  |    0
 .../asm/{arch-queensbay => }/fsp/fsp_platform.h    |    0
 .../asm/{arch-queensbay => }/fsp/fsp_support.h     |    6 +-
 .../asm/{arch-queensbay => }/fsp/fsp_types.h       |    0
 arch/x86/include/asm/u-boot-x86.h                  |   20 +
 arch/x86/lib/Makefile                              |    1 +
 arch/x86/lib/cmd_hob.c                             |    2 +-
 arch/x86/lib/fsp/Makefile                          |   10 +
 .../{cpu/queensbay/tnc_car.S => lib/fsp/fsp_car.S} |    0
 arch/x86/lib/fsp/fsp_common.c                      |   88 +
 .../queensbay/tnc_dram.c => lib/fsp/fsp_dram.c}    |    2 +-
 arch/x86/{cpu/queensbay => lib/fsp}/fsp_support.c  |   20 +-
 board/google/chromebook_link/Kconfig               |    1 -
 board/intel/minnowmax/Kconfig                      |   31 +
 board/intel/minnowmax/MAINTAINERS                  |    6 +
 board/intel/minnowmax/Makefile                     |    7 +
 board/intel/minnowmax/minnowmax.c                  |   32 +
 board/intel/minnowmax/start.S                      |    9 +
 common/cmd_scsi.c                                  |    2 +
 configs/minnowmax_defconfig                        |   13 +
 doc/README.x86                                     |  120 +-
 drivers/pci/pci.c                                  |   38 +
 drivers/pci/pci_rom.c                              |   32 +-
 drivers/spi/ich.c                                  |   56 +-
 drivers/spi/ich.h                                  |   11 +-
 drivers/usb/host/Makefile                          |    1 +
 drivers/usb/host/ehci-pci.c                        |   53 +-
 drivers/usb/host/xhci-pci.c                        |   60 +
 drivers/video/vesa_fb.c                            |    9 +-
 include/bootstage.h                                |    1 +
 include/configs/minnowmax.h                        |   69 +
 include/configs/x86-common.h                       |    3 +
 include/pci.h                                      |    3 +-
 include/pci_ids.h                                  |    5 +
 include/pci_rom.h                                  |   15 +-
 tools/microcode-tool.py                            |   90 +-
 66 files changed, 4589 insertions(+), 252 deletions(-)
 create mode 100644 arch/x86/cpu/baytrail/Kconfig
 create mode 100644 arch/x86/cpu/baytrail/Makefile
 create mode 100644 arch/x86/cpu/baytrail/early_uart.c
 create mode 100644 arch/x86/cpu/baytrail/fsp_configs.c
 create mode 100644 arch/x86/cpu/baytrail/pci.c
 create mode 100644 arch/x86/cpu/baytrail/valleyview.c
 create mode 100644 arch/x86/dts/microcode/m0130673322.dtsi
 create mode 100644 arch/x86/dts/minnowmax.dts
 create mode 100644 arch/x86/include/asm/arch-baytrail/fsp/azalia.h
 create mode 100644 arch/x86/include/asm/arch-baytrail/fsp/fsp_vpd.h
 create mode 100644 arch/x86/include/asm/arch-baytrail/gpio.h
 rename arch/x86/include/asm/{arch-queensbay => }/fsp/fsp_api.h (88%)
 rename arch/x86/include/asm/{arch-queensbay => }/fsp/fsp_bootmode.h (100%)
 rename arch/x86/include/asm/{arch-queensbay => }/fsp/fsp_ffs.h (100%)
 rename arch/x86/include/asm/{arch-queensbay => }/fsp/fsp_fv.h (100%)
 rename arch/x86/include/asm/{arch-queensbay => }/fsp/fsp_hob.h (100%)
 rename arch/x86/include/asm/{arch-queensbay => }/fsp/fsp_infoheader.h (100%)
 rename arch/x86/include/asm/{arch-queensbay => }/fsp/fsp_platform.h (100%)
 rename arch/x86/include/asm/{arch-queensbay => }/fsp/fsp_support.h (98%)
 rename arch/x86/include/asm/{arch-queensbay => }/fsp/fsp_types.h (100%)
 create mode 100644 arch/x86/lib/fsp/Makefile
 rename arch/x86/{cpu/queensbay/tnc_car.S => lib/fsp/fsp_car.S} (100%)
 create mode 100644 arch/x86/lib/fsp/fsp_common.c
 rename arch/x86/{cpu/queensbay/tnc_dram.c => lib/fsp/fsp_dram.c} (98%)
 rename arch/x86/{cpu/queensbay => lib/fsp}/fsp_support.c (96%)
 create mode 100644 board/intel/minnowmax/Kconfig
 create mode 100644 board/intel/minnowmax/MAINTAINERS
 create mode 100644 board/intel/minnowmax/Makefile
 create mode 100644 board/intel/minnowmax/minnowmax.c
 create mode 100644 board/intel/minnowmax/start.S
 create mode 100644 configs/minnowmax_defconfig
 create mode 100644 drivers/usb/host/xhci-pci.c
 create mode 100644 include/configs/minnowmax.h

-- 
2.2.0.rc0.207.ga3a616c

[U-Boot] [PATCH 01/23] x86: Enhance the microcode tool to support header files as input

[Simon Glass]

Sometimes microcode is delivered as a header file. Allow the tool to
support this as well as collecting multiple microcode blocks into a
single update.

Signed-off-by: Simon Glass <sjg@chromium.org>
---

 tools/microcode-tool.py | 90 ++++++++++++++++++++++++++++++++++++++-----------
 1 file changed, 70 insertions(+), 20 deletions(-)

diff --git a/tools/microcode-tool.py b/tools/microcode-tool.py
index 003716d..71c2e91 100755
--- a/tools/microcode-tool.py
+++ b/tools/microcode-tool.py
@@ -76,6 +76,35 @@ def ParseFile(fname):
         microcodes[name] = Microcode(name, data)
     return date, license_text, microcodes
 
+def ParseHeaderFiles(fname_list):
+    """Parse a list of header files and return the component parts
+
+    Args:
+        fname_list: List of files to parse
+    Returns:
+            date:         String containing date from the file's header
+            license_text: List of text lines for the license file
+            microcodes:   List of Microcode objects from the file
+    """
+    microcodes = {}
+    license_text = []
+    date = ''
+    name = None
+    for fname in fname_list:
+        name = os.path.basename(fname).lower()
+        name = os.path.splitext(name)[0]
+        data = []
+        with open(fname) as fd:
+            for line in fd:
+                line = line.rstrip()
+
+                # Omit anything after the last comma
+                words = line.split(',')[:-1]
+                data += [word + ',' for word in words]
+        microcodes[name] = Microcode(name, data)
+    return date, license_text, microcodes
+
+
 def List(date, microcodes, model):
     """List the available microcode chunks
 
@@ -129,13 +158,13 @@ def FindMicrocode(microcodes, model):
             break
     return found, tried
 
-def CreateFile(date, license_text, mcode, outfile):
+def CreateFile(date, license_text, mcodes, outfile):
     """Create a microcode file in U-Boot's .dtsi format
 
     Args:
         date:       String containing date of original microcode file
         license:    List of text lines for the license file
-        mcode:      Microcode object to write
+        mcodes:      Microcode objects to write (normally only 1)
         outfile:    Filename to write to ('-' for stdout)
     """
     out = '''/*%s
@@ -159,15 +188,22 @@ intel,processor-flags = <%#x>;
 data = <%s
 \t>;'''
     words = ''
-    for i in range(len(mcode.words)):
-        if not (i & 3):
-            words += '\n'
-        val = mcode.words[i]
-        # Change each word so it will be little-endian in the FDT
-        # This data is needed before RAM is available on some platforms so we
-        # cannot do an endianness swap on boot.
-        val = struct.unpack("<I", struct.pack(">I", val))[0]
-        words += '\t%#010x' % val
+    add_comments = len(mcodes) > 1
+    for mcode in mcodes:
+        if add_comments:
+            words += '\n/* %s */' % mcode.name
+        for i in range(len(mcode.words)):
+            if not (i & 3):
+                words += '\n'
+            val = mcode.words[i]
+            # Change each word so it will be little-endian in the FDT
+            # This data is needed before RAM is available on some platforms so
+            # we cannot do an endianness swap on boot.
+            val = struct.unpack("<I", struct.pack(">I", val))[0]
+            words += '\t%#010x' % val
+
+    # Use the first microcode for the headers
+    mcode = mcodes[0]
 
     # Take care to avoid adding a space before a tab
     text = ''
@@ -187,8 +223,8 @@ data = <%s
                 print >> sys.stderr, "Creating directory '%s'" % MICROCODE_DIR
                 os.makedirs(MICROCODE_DIR)
             outfile = os.path.join(MICROCODE_DIR, mcode.name + '.dtsi')
-            print >> sys.stderr, "Writing microcode for '%s' to '%s'" % (
-                     mcode.name, outfile)
+        print >> sys.stderr, "Writing microcode for '%s' to '%s'" % (
+                ', '.join([mcode.name for mcode in mcodes]), outfile)
         with open(outfile, 'w') as fd:
             print >> fd, out % tuple(args)
 
@@ -198,8 +234,12 @@ def MicrocodeTool():
     parser = OptionParser()
     parser.add_option('-d', '--mcfile', type='string', action='store',
                     help='Name of microcode.dat file')
+    parser.add_option('-H', '--headerfile', type='string', action='append',
+                    help='Name of .h file containing microcode')
     parser.add_option('-m', '--model', type='string', action='store',
-                    help='Model name to extract')
+                    help="Model name to extract ('all' for all)")
+    parser.add_option('-M', '--multiple', type='string', action='store',
+                    help="Allow output of multiple models")
     parser.add_option('-o', '--outfile', type='string', action='store',
                     help='Filename to use for output (- for stdout), default is'
                     ' %s/<name>.dtsi' % MICROCODE_DIR)
@@ -224,9 +264,14 @@ def MicrocodeTool():
     if cmd not in commands:
         parser.error("Unknown command '%s'" % cmd)
 
-    if not options.mcfile:
-        parser.error('You must specify a microcode file')
-    date, license_text, microcodes = ParseFile(options.mcfile)
+    if (not not options.mcfile) != (not not options.mcfile):
+        parser.error("You must specify either header files or a microcode file, not both")
+    if options.headerfile:
+        date, license_text, microcodes = ParseHeaderFiles(options.headerfile)
+    elif options.mcfile:
+        date, license_text, microcodes = ParseFile(options.mcfile)
+    else:
+        parser.error('You must specify a microcode file (or header files)')
 
     if cmd == 'list':
         List(date, microcodes, options.model)
@@ -236,16 +281,21 @@ def MicrocodeTool():
         if not options.model:
             parser.error('You must specify a model to create')
         model = options.model.lower()
-        mcode_list, tried = FindMicrocode(microcodes, model)
+        if options.model == 'all':
+            options.multiple = True
+            mcode_list = microcodes.values()
+            tried = []
+        else:
+            mcode_list, tried = FindMicrocode(microcodes, model)
         if not mcode_list:
             parser.error("Unknown model '%s' (%s) - try 'list' to list" %
                         (model, ', '.join(tried)))
-        if len(mcode_list) > 1:
+        if not options.multiple and len(mcode_list) > 1:
             parser.error("Ambiguous model '%s' (%s) matched %s - try 'list' "
                         "to list or specify a particular file" %
                         (model, ', '.join(tried),
                         ', '.join([m.name for m in mcode_list])))
-        CreateFile(date, license_text, mcode_list[0], options.outfile)
+        CreateFile(date, license_text, mcode_list, options.outfile)
     else:
         parser.error("Unknown command '%s'" % cmd)
 
-- 
2.2.0.rc0.207.ga3a616c

[U-Boot] [PATCH 02/23] pci: Add a function to find a device by class

[Simon Glass]

There is an existing function prototype in the header file but it is not
implemented. Implement something similar.

Signed-off-by: Simon Glass <sjg@chromium.org>
---

 drivers/pci/pci.c | 38 ++++++++++++++++++++++++++++++++++++++
 include/pci.h     |  3 +--
 2 files changed, 39 insertions(+), 2 deletions(-)

diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
index 950a247..215a092 100644
--- a/drivers/pci/pci.c
+++ b/drivers/pci/pci.c
@@ -15,6 +15,7 @@
 #include <common.h>
 
 #include <command.h>
+#include <errno.h>
 #include <asm/processor.h>
 #include <asm/io.h>
 #include <pci.h>
@@ -236,6 +237,43 @@ pci_dev_t pci_find_devices(struct pci_device_id *ids, int index)
 	return -1;
 }
 
+pci_dev_t pci_find_class(uint find_class, int index)
+{
+	int bus;
+	int devnum;
+	pci_dev_t bdf;
+	uint32_t class;
+
+	for (bus = 0; bus <= pci_last_busno(); bus++) {
+		for (devnum = 0; devnum < PCI_MAX_PCI_DEVICES-1; devnum++) {
+			pci_read_config_dword(PCI_BDF(bus, devnum, 0),
+					      PCI_CLASS_REVISION, &class);
+			if (class >> 16 == 0xffff)
+				continue;
+
+			for (bdf = PCI_BDF(bus, devnum, 0);
+					bdf <= PCI_BDF(bus, devnum,
+						PCI_MAX_PCI_FUNCTIONS - 1);
+					bdf += PCI_BDF(0, 0, 1)) {
+				pci_read_config_dword(bdf, PCI_CLASS_REVISION,
+						      &class);
+				class >>= 8;
+
+				if (class != find_class)
+					continue;
+				if (index) {
+					index--;
+					continue;
+				}
+				/* Return index'th controller. */
+				return bdf;
+			}
+		}
+	}
+
+	return -ENODEV;
+}
+
 pci_dev_t pci_find_device(unsigned int vendor, unsigned int device, int index)
 {
 	struct pci_device_id ids[2] = { {}, {0, 0} };
diff --git a/include/pci.h b/include/pci.h
index 4fbb8f6..004a048 100644
--- a/include/pci.h
+++ b/include/pci.h
@@ -644,8 +644,7 @@ extern int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev);
 
 extern pci_dev_t pci_find_device (unsigned int vendor, unsigned int device, int index);
 extern pci_dev_t pci_find_devices (struct pci_device_id *ids, int index);
-extern pci_dev_t pci_find_class(int wanted_class, int wanted_sub_code,
-				int wanted_prog_if, int index);
+pci_dev_t pci_find_class(unsigned int find_class, int index);
 
 extern int pci_hose_config_device(struct pci_controller *hose,
 				  pci_dev_t dev,
-- 
2.2.0.rc0.207.ga3a616c

[U-Boot] [PATCH 03/23] x86: pci: Add PCI IDs for Minnowboard Max

[Simon Glass]

This board includes a few IDs we have not seen before.

Signed-off-by: Simon Glass <sjg@chromium.org>
---

 include/pci_ids.h | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/include/pci_ids.h b/include/pci_ids.h
index 26f4748..1012abe 100644
--- a/include/pci_ids.h
+++ b/include/pci_ids.h
@@ -1346,6 +1346,7 @@
 
 #define PCI_VENDOR_ID_REALTEK		0x10ec
 #define PCI_DEVICE_ID_REALTEK_8139	0x8139
+#define PCI_DEVICE_ID_REALTEK_8168	0x8168
 
 #define PCI_VENDOR_ID_XILINX		0x10ee
 #define PCI_DEVICE_ID_RME_DIGI96	0x3fc0
@@ -2594,6 +2595,10 @@
 #define PCI_DEVICE_ID_INTEL_I960	0x0960
 #define PCI_DEVICE_ID_INTEL_I960RM	0x0962
 #define PCI_DEVICE_ID_INTEL_CENTERTON_ILB	0x0c60
+#define PCI_DEVICE_ID_INTEL_VALLEYVIEW_SDIO	0x0f15
+#define PCI_DEVICE_ID_INTEL_VALLEYVIEW_SDCARD	0x0f16
+#define PCI_DEVICE_ID_INTEL_VALLEYVIEW_LPC	0x0f1c
+#define PCI_DEVICE_ID_INTEL_VALLEYVIEW_SATA	0x0f23
 #define PCI_DEVICE_ID_INTEL_82541ER	0x1078
 #define PCI_DEVICE_ID_INTEL_82541GI_LF	0x107c
 #define PCI_DEVICE_ID_INTEL_82542	0x1000
-- 
2.2.0.rc0.207.ga3a616c

[U-Boot] [PATCH 04/23] x86: video: Enable video for Minnowboard Max

[Simon Glass]

This board uses a new PCI ID.

Signed-off-by: Simon Glass <sjg@chromium.org>
---

 drivers/video/vesa_fb.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/video/vesa_fb.c b/drivers/video/vesa_fb.c
index 3dacafd..3a0fea2 100644
--- a/drivers/video/vesa_fb.c
+++ b/drivers/video/vesa_fb.c
@@ -23,6 +23,7 @@ struct pci_device_id vesa_video_ids[] = {
 	{ .vendor = 0x1002, .device = 0x5159 },
 	{ .vendor = 0x1002, .device = 0x4752 },
 	{ .vendor = 0x1002, .device = 0x5452 },
+	{ .vendor = 0x8086, .device = 0x0f31 },
 	{},
 };
 
-- 
2.2.0.rc0.207.ga3a616c

[U-Boot] [PATCH 05/23] usb: pci: Use pci_find_class() to find the device

[Simon Glass]

Use the new utility function instead of local code.

Signed-off-by: Simon Glass <sjg@chromium.org>
---

 drivers/usb/host/ehci-pci.c | 53 +--------------------------------------------
 1 file changed, 1 insertion(+), 52 deletions(-)

diff --git a/drivers/usb/host/ehci-pci.c b/drivers/usb/host/ehci-pci.c
index 991b199..b9eabc5 100644
--- a/drivers/usb/host/ehci-pci.c
+++ b/drivers/usb/host/ehci-pci.c
@@ -34,57 +34,6 @@ static struct pci_device_id ehci_pci_ids[] = {
 	{0, 0}
 };
 #else
-static pci_dev_t ehci_find_class(int index)
-{
-	int bus;
-	int devnum;
-	pci_dev_t bdf;
-	uint32_t class;
-
-	for (bus = 0; bus <= pci_last_busno(); bus++) {
-		for (devnum = 0; devnum < PCI_MAX_PCI_DEVICES-1; devnum++) {
-			pci_read_config_dword(PCI_BDF(bus, devnum, 0),
-					      PCI_CLASS_REVISION, &class);
-			if (class >> 16 == 0xffff)
-				continue;
-
-			for (bdf = PCI_BDF(bus, devnum, 0);
-					bdf <= PCI_BDF(bus, devnum,
-						PCI_MAX_PCI_FUNCTIONS - 1);
-					bdf += PCI_BDF(0, 0, 1)) {
-				pci_read_config_dword(bdf, PCI_CLASS_REVISION,
-						      &class);
-				class >>= 8;
-				/*
-				 * Here be dragons! In case we have multiple
-				 * PCI EHCI controllers, this function will
-				 * be called multiple times as well. This
-				 * function will scan the PCI busses, always
-				 * starting from bus 0, device 0, function 0,
-				 * until it finds an USB controller. The USB
-				 * stack gives us an 'index' of a controller
-				 * that is currently being registered, which
-				 * is a number, starting from 0 and growing
-				 * in ascending order as controllers are added.
-				 * To avoid probing the same controller in tne
-				 * subsequent runs of this function, we will
-				 * skip 'index - 1' detected controllers and
-				 * report the index'th controller.
-				 */
-				if (class != PCI_CLASS_SERIAL_USB_EHCI)
-					continue;
-				if (index) {
-					index--;
-					continue;
-				}
-				/* Return index'th controller. */
-				return bdf;
-			}
-		}
-	}
-
-	return -ENODEV;
-}
 #endif
 
 /*
@@ -102,7 +51,7 @@ int ehci_hcd_init(int index, enum usb_init_type init,
 #ifdef CONFIG_PCI_EHCI_DEVICE
 	pdev = pci_find_devices(ehci_pci_ids, CONFIG_PCI_EHCI_DEVICE);
 #else
-	pdev = ehci_find_class(index);
+	pdev = pci_find_class(PCI_CLASS_SERIAL_USB_EHCI, index);
 #endif
 	if (pdev < 0) {
 		printf("EHCI host controller not found\n");
-- 
2.2.0.rc0.207.ga3a616c

[U-Boot] [PATCH 06/23] usb: pci: Add XHCI driver for PCI

[Simon Glass]

Add a driver which locates the available XHCI controllers on the PCI bus
and makes them available.

Signed-off-by: Simon Glass <sjg@chromium.org>
---

 drivers/usb/host/Makefile   |  1 +
 drivers/usb/host/xhci-pci.c | 60 +++++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 61 insertions(+)
 create mode 100644 drivers/usb/host/xhci-pci.c

diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile
index c11b551..66d6e9a 100644
--- a/drivers/usb/host/Makefile
+++ b/drivers/usb/host/Makefile
@@ -47,6 +47,7 @@ obj-$(CONFIG_USB_XHCI) += xhci.o xhci-mem.o xhci-ring.o
 obj-$(CONFIG_USB_XHCI_KEYSTONE) += xhci-keystone.o
 obj-$(CONFIG_USB_XHCI_EXYNOS) += xhci-exynos5.o
 obj-$(CONFIG_USB_XHCI_OMAP) += xhci-omap.o
+obj-$(CONFIG_USB_XHCI_PCI) += xhci-pci.o
 
 # designware
 obj-$(CONFIG_USB_DWC2) += dwc2.o
diff --git a/drivers/usb/host/xhci-pci.c b/drivers/usb/host/xhci-pci.c
new file mode 100644
index 0000000..361fcce
--- /dev/null
+++ b/drivers/usb/host/xhci-pci.c
@@ -0,0 +1,60 @@
+/*
+ * Copyright (c) 2015, Google, Inc
+ * Written by Simon Glass <sjg@chromium.org>
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier:	GPL-2.0
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <pci.h>
+#include <usb.h>
+
+#include "xhci.h"
+
+/*
+ * Create the appropriate control structures to manage a new XHCI host
+ * controller.
+ */
+int xhci_hcd_init(int index, struct xhci_hccr **ret_hccr,
+		  struct xhci_hcor **ret_hcor)
+{
+	struct xhci_hccr *hccr;
+	struct xhci_hcor *hcor;
+	pci_dev_t pdev;
+	uint32_t cmd;
+	int len;
+
+	pdev = pci_find_class(PCI_CLASS_SERIAL_USB_XHCI, index);
+	if (pdev < 0) {
+		printf("XHCI host controller not found\n");
+		return -1;
+	}
+
+	hccr = (struct xhci_hccr *)pci_map_bar(pdev,
+			PCI_BASE_ADDRESS_0, PCI_REGION_MEM);
+	len = HC_LENGTH(xhci_readl(&hccr->cr_capbase));
+	hcor = (struct xhci_hcor *)((uint32_t)hccr + len);
+
+	debug("XHCI-PCI init hccr 0x%x and hcor 0x%x hc_length %d\n",
+	      (uint32_t)hccr, (uint32_t)hcor, len);
+
+	*ret_hccr = hccr;
+	*ret_hcor = hcor;
+
+	/* enable busmaster */
+	pci_read_config_dword(pdev, PCI_COMMAND, &cmd);
+	cmd |= PCI_COMMAND_MASTER;
+	pci_write_config_dword(pdev, PCI_COMMAND, cmd);
+
+	return 0;
+}
+
+/*
+ * Destroy the appropriate control structures corresponding * to the XHCI host
+ * controller
+ */
+void xhci_hcd_stop(int index)
+{
+}
-- 
2.2.0.rc0.207.ga3a616c

[U-Boot] [PATCH 07/23] x86: Add an option to enabling building a ROM file

[Simon Glass]

Rather than requiring the Makefile to be modified, provide a build option to
enable the ROM to be built.

We cannot do this by default since it requires binary blobs. Without these
the build will fail.

Signed-off-by: Simon Glass <sjg@chromium.org>
---

 Makefile       |  5 +++--
 doc/README.x86 | 10 ++++++----
 2 files changed, 9 insertions(+), 6 deletions(-)

diff --git a/Makefile b/Makefile
index a876f1f..c6e4ad1 100644
--- a/Makefile
+++ b/Makefile
@@ -729,8 +729,9 @@ ALL-$(CONFIG_SPL) += $(CONFIG_SPL_TARGET:"%"=%)
 endif
 ALL-$(CONFIG_REMAKE_ELF) += u-boot.elf
 
-# We can't do this yet due to the need for binary blobs
-# ALL-$(CONFIG_X86_RESET_VECTOR) += u-boot.rom
+ifneq ($(BUILD_ROM),)
+ALL-$(CONFIG_X86_RESET_VECTOR) += u-boot.rom
+endif
 
 # enable combined SPL/u-boot/dtb rules for tegra
 ifneq ($(CONFIG_TEGRA),)
diff --git a/doc/README.x86 b/doc/README.x86
index 7df8cc5..809a291 100644
--- a/doc/README.x86
+++ b/doc/README.x86
@@ -51,9 +51,11 @@ Building ROM version of U-Boot (hereafter referred to as u-boot.rom) is a
 little bit tricky, as generally it requires several binary blobs which are not
 shipped in the U-Boot source tree. Due to this reason, the u-boot.rom build is
 not turned on by default in the U-Boot source tree. Firstly, you need turn it
-on by uncommenting the following line in the main U-Boot Makefile:
+on by enabling the ROM board:
 
-# ALL-$(CONFIG_X86_RESET_VECTOR) += u-boot.rom
+$ export BUILD_ROM=y
+
+This tells the Makefile to build u-boot.rom as a target.
 
 Link-specific instructions:
 
@@ -126,11 +128,11 @@ Make sure 0x1110000 matches CONFIG_SYS_TEXT_BASE and 0x1110015 matches the
 symbol address of _start (in arch/x86/cpu/start.S).
 
 If you want to use ELF as the coreboot payload, change U-Boot configuration to
-use CONFIG_OF_EMBED.
+use CONFIG_OF_EMBED instead of CONFIG_OF_SEPARATE.
 
 CPU Microcode
 -------------
-Modern CPU usually requires a special bit stream called microcode [5] to be
+Modern CPUs usually requires a special bit stream called microcode [5] to be
 loaded on the processor after power up in order to function properly. U-Boot
 has already integrated these as hex dumps in the source tree.
 
-- 
2.2.0.rc0.207.ga3a616c

[U-Boot] [PATCH 08/23] x86: Make MMCONF_BASE_ADDRESS common across x86

[Simon Glass]

This setting will be used by more than just ivybridge so make it common.

Signed-off-by: Simon Glass <sjg@chromium.org>
---

 arch/x86/Kconfig                     | 12 ++++++++++++
 board/google/chromebook_link/Kconfig |  1 -
 2 files changed, 12 insertions(+), 1 deletion(-)

diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index 90e828a..1523c91 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -356,4 +356,16 @@ source "board/google/chromebook_link/Kconfig"
 
 source "board/intel/crownbay/Kconfig"
 
+config MMCONF_BASE_ADDRESS
+	hex
+        default 0xe0000000
+	help
+	  This is the address of PCI configuration space. It can be set up
+	  amost anywhere. Before it is set up, it is possible to access PCI
+	  configuration space through I/O access, but memory access is more
+	  convenient. Using this, PCI can be scanned and configured. This
+	  should be set to a region that does not conflict with memory
+	  assigned to PCI devices - i.e. the memory and prefetch regions, as
+	  passed to pci_set_region().
+
 endmenu
diff --git a/board/google/chromebook_link/Kconfig b/board/google/chromebook_link/Kconfig
index 33a31f3..948af59 100644
--- a/board/google/chromebook_link/Kconfig
+++ b/board/google/chromebook_link/Kconfig
@@ -23,7 +23,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select BOARD_ROMSIZE_KB_8192
 
 config MMCONF_BASE_ADDRESS
-	hex
 	default 0xf0000000
 
 config EARLY_POST_CROS_EC
-- 
2.2.0.rc0.207.ga3a616c

[U-Boot] [PATCH 09/23] x86: video: Allow video ROM execution to fall back to the other method

[Simon Glass]

If the BIOS emulator is not available, allow use of native execution if
available, and vice versa. This can be controlled by the caller.

Signed-off-by: Simon Glass <sjg@chromium.org>
---

 arch/x86/cpu/ivybridge/gma.c |  3 ++-
 drivers/pci/pci_rom.c        | 32 +++++++++++++++++++++++++-------
 drivers/video/vesa_fb.c      |  6 +++---
 include/pci_rom.h            | 15 +++++++++++++--
 4 files changed, 43 insertions(+), 13 deletions(-)

diff --git a/arch/x86/cpu/ivybridge/gma.c b/arch/x86/cpu/ivybridge/gma.c
index 6cf9654..821ea25 100644
--- a/arch/x86/cpu/ivybridge/gma.c
+++ b/arch/x86/cpu/ivybridge/gma.c
@@ -758,7 +758,8 @@ int gma_func0_init(pci_dev_t dev, struct pci_controller *hose,
 
 #ifdef CONFIG_VIDEO
 	start = get_timer(0);
-	ret = pci_run_vga_bios(dev, int15_handler, false);
+	ret = pci_run_vga_bios(dev, int15_handler, PCI_ROM_USE_NATIVE |
+			       PCI_ROM_ALLOW_FALLBACK);
 	debug("BIOS ran in %lums\n", get_timer(start));
 #endif
 	/* Post VBIOS init */
diff --git a/drivers/pci/pci_rom.c b/drivers/pci/pci_rom.c
index eb76591..0796179 100644
--- a/drivers/pci/pci_rom.c
+++ b/drivers/pci/pci_rom.c
@@ -228,11 +228,12 @@ int vbe_get_video_info(struct graphic_device *gdev)
 #endif
 }
 
-int pci_run_vga_bios(pci_dev_t dev, int (*int15_handler)(void), bool emulate)
+int pci_run_vga_bios(pci_dev_t dev, int (*int15_handler)(void), int exec_method)
 {
 	struct pci_rom_header *rom, *ram;
 	int vesa_mode = -1;
 	uint16_t class;
+	bool emulate;
 	int ret;
 
 	/* Only execute VGA ROMs */
@@ -262,6 +263,29 @@ int pci_run_vga_bios(pci_dev_t dev, int (*int15_handler)(void), bool emulate)
 	vesa_mode = CONFIG_FRAMEBUFFER_VESA_MODE;
 #endif
 	debug("Selected vesa mode %#x\n", vesa_mode);
+
+	if (exec_method & PCI_ROM_USE_NATIVE) {
+#ifdef CONFIG_X86
+		emulate = false;
+#else
+		if (!(exec_method & PCI_ROM_ALLOW_FALLBACK)) {
+			printf("BIOS native execution is only available on x86\n");
+			return -ENOSYS;
+		}
+		emulate = true;
+#endif
+	} else {
+#ifdef CONFIG_BIOSEMU
+		emulate = true;
+#else
+		if (!(exec_method & PCI_ROM_ALLOW_FALLBACK)) {
+			printf("BIOS emulation not available - see CONFIG_BIOSEMU\n");
+			return -ENOSYS;
+		}
+		emulate = false;
+#endif
+	}
+
 	if (emulate) {
 #ifdef CONFIG_BIOSEMU
 		BE_VGAInfo *info;
@@ -274,9 +298,6 @@ int pci_run_vga_bios(pci_dev_t dev, int (*int15_handler)(void), bool emulate)
 				  vesa_mode, &mode_info);
 		if (ret)
 			return ret;
-#else
-		printf("BIOS emulation not available - see CONFIG_BIOSEMU\n");
-		return -ENOSYS;
 #endif
 	} else {
 #ifdef CONFIG_X86
@@ -284,9 +305,6 @@ int pci_run_vga_bios(pci_dev_t dev, int (*int15_handler)(void), bool emulate)
 
 		bios_run_on_x86(dev, (unsigned long)ram, vesa_mode,
 				&mode_info);
-#else
-		printf("BIOS native execution is only available on x86\n");
-		return -ENOSYS;
 #endif
 	}
 	debug("Final vesa mode %#x\n", mode_info.video_mode);
diff --git a/drivers/video/vesa_fb.c b/drivers/video/vesa_fb.c
index 3a0fea2..9164f8d 100644
--- a/drivers/video/vesa_fb.c
+++ b/drivers/video/vesa_fb.c
@@ -42,8 +42,8 @@ void *video_hw_init(void)
 			printf("no card detected\n");
 			return NULL;
 		}
-		printf("bdf %x\n", dev);
-		ret = pci_run_vga_bios(dev, NULL, true);
+		ret = pci_run_vga_bios(dev, NULL, PCI_ROM_USE_NATIVE |
+				       PCI_ROM_ALLOW_FALLBACK);
 		if (ret) {
 			printf("failed to run video BIOS: %d\n", ret);
 			return NULL;
@@ -59,7 +59,7 @@ void *video_hw_init(void)
 	sprintf(gdev->modeIdent, "%dx%dx%d", gdev->winSizeX, gdev->winSizeY,
 		bits_per_pixel);
 	printf("%s\n", gdev->modeIdent);
-	debug("Framex buffer at %x\n", gdev->pciBase);
+	debug("Frame buffer at %x\n", gdev->pciBase);
 
 	return (void *)gdev;
 }
diff --git a/include/pci_rom.h b/include/pci_rom.h
index 4ba36eb..d24c52a 100644
--- a/include/pci_rom.h
+++ b/include/pci_rom.h
@@ -33,14 +33,25 @@ struct pci_rom_data {
 	uint16_t reserved_2;
 };
 
+/*
+ * Determines which execution method is used and whether we allow falling back
+ * to the other if the requested method is not available.
+ */
+enum pci_rom_emul_t {
+	PCI_ROM_EMULATE		= 0 << 0,
+	PCI_ROM_USE_NATIVE	= 1 << 0,
+	PCI_ROM_ALLOW_FALLBACK	= 1 << 1,
+};
+
  /**
  * pci_run_vga_bios() - Run the VGA BIOS in an x86 PC
  *
  * @dev:	Video device containing the BIOS
  * @int15_handler:	Function to call to handle int 0x15
- * @emulate:	true to use the x86 emulator, false to run native
+ * @exec_method:	flags from enum pci_rom_emul_t
  */
-int pci_run_vga_bios(pci_dev_t dev, int (*int15_handler)(void), bool emulate);
+int pci_run_vga_bios(pci_dev_t dev, int (*int15_handler)(void),
+		     int exec_method);
 
 /**
  * board_map_oprom_vendev() - map several PCI IDs to the one the ROM expects
-- 
2.2.0.rc0.207.ga3a616c

[U-Boot] [PATCH 10/23] x86: bootstage: Add time measurement for vesa start-up

[Simon Glass]

Since we must run a PCI BIOS ROM, and this can take a calamitous amount of
time, measure it using bootstage.

Signed-off-by: Simon Glass <sjg@chromium.org>
---

 drivers/video/vesa_fb.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/video/vesa_fb.c b/drivers/video/vesa_fb.c
index 9164f8d..47f824a 100644
--- a/drivers/video/vesa_fb.c
+++ b/drivers/video/vesa_fb.c
@@ -42,8 +42,10 @@ void *video_hw_init(void)
 			printf("no card detected\n");
 			return NULL;
 		}
+		bootstage_start(BOOTSTAGE_ID_ACCUM_LCD, "vesa display");
 		ret = pci_run_vga_bios(dev, NULL, PCI_ROM_USE_NATIVE |
 				       PCI_ROM_ALLOW_FALLBACK);
+		bootstage_accum(BOOTSTAGE_ID_ACCUM_LCD);
 		if (ret) {
 			printf("failed to run video BIOS: %d\n", ret);
 			return NULL;
-- 
2.2.0.rc0.207.ga3a616c

[U-Boot] [PATCH 11/23] x86: Move common FSP code into a common location

[Simon Glass]

Signed-off-by: Simon Glass <sjg@chromium.org>
---

 arch/x86/cpu/queensbay/Makefile                                | 2 +-
 arch/x86/cpu/queensbay/fsp_configs.c                           | 2 +-
 arch/x86/cpu/queensbay/tnc.c                                   | 2 +-
 arch/x86/cpu/queensbay/tnc_dram.c                              | 2 +-
 arch/x86/cpu/queensbay/tnc_pci.c                               | 2 +-
 arch/x86/include/asm/{arch-queensbay => }/fsp/fsp_api.h        | 0
 arch/x86/include/asm/{arch-queensbay => }/fsp/fsp_bootmode.h   | 0
 arch/x86/include/asm/{arch-queensbay => }/fsp/fsp_ffs.h        | 0
 arch/x86/include/asm/{arch-queensbay => }/fsp/fsp_fv.h         | 0
 arch/x86/include/asm/{arch-queensbay => }/fsp/fsp_hob.h        | 0
 arch/x86/include/asm/{arch-queensbay => }/fsp/fsp_infoheader.h | 0
 arch/x86/include/asm/{arch-queensbay => }/fsp/fsp_platform.h   | 0
 arch/x86/include/asm/{arch-queensbay => }/fsp/fsp_support.h    | 2 +-
 arch/x86/include/asm/{arch-queensbay => }/fsp/fsp_types.h      | 0
 arch/x86/lib/Makefile                                          | 1 +
 arch/x86/lib/cmd_hob.c                                         | 2 +-
 arch/x86/lib/fsp/Makefile                                      | 7 +++++++
 arch/x86/{cpu/queensbay => lib/fsp}/fsp_support.c              | 2 +-
 18 files changed, 16 insertions(+), 8 deletions(-)
 rename arch/x86/include/asm/{arch-queensbay => }/fsp/fsp_api.h (100%)
 rename arch/x86/include/asm/{arch-queensbay => }/fsp/fsp_bootmode.h (100%)
 rename arch/x86/include/asm/{arch-queensbay => }/fsp/fsp_ffs.h (100%)
 rename arch/x86/include/asm/{arch-queensbay => }/fsp/fsp_fv.h (100%)
 rename arch/x86/include/asm/{arch-queensbay => }/fsp/fsp_hob.h (100%)
 rename arch/x86/include/asm/{arch-queensbay => }/fsp/fsp_infoheader.h (100%)
 rename arch/x86/include/asm/{arch-queensbay => }/fsp/fsp_platform.h (100%)
 rename arch/x86/include/asm/{arch-queensbay => }/fsp/fsp_support.h (99%)
 rename arch/x86/include/asm/{arch-queensbay => }/fsp/fsp_types.h (100%)
 create mode 100644 arch/x86/lib/fsp/Makefile
 rename arch/x86/{cpu/queensbay => lib/fsp}/fsp_support.c (99%)

diff --git a/arch/x86/cpu/queensbay/Makefile b/arch/x86/cpu/queensbay/Makefile
index 2c2ec01..b3e7d87 100644
--- a/arch/x86/cpu/queensbay/Makefile
+++ b/arch/x86/cpu/queensbay/Makefile
@@ -5,5 +5,5 @@
 #
 
 obj-y += tnc_car.o tnc_dram.o tnc.o topcliff.o
-obj-y += fsp_configs.o fsp_support.o
+obj-y += fsp_configs.o
 obj-$(CONFIG_PCI) += tnc_pci.o
diff --git a/arch/x86/cpu/queensbay/fsp_configs.c b/arch/x86/cpu/queensbay/fsp_configs.c
index af28e45..78bc966 100644
--- a/arch/x86/cpu/queensbay/fsp_configs.c
+++ b/arch/x86/cpu/queensbay/fsp_configs.c
@@ -6,7 +6,7 @@
  */
 
 #include <common.h>
-#include <asm/arch/fsp/fsp_support.h>
+#include <asm/fsp/fsp_support.h>
 
 void update_fsp_upd(struct upd_region *fsp_upd)
 {
diff --git a/arch/x86/cpu/queensbay/tnc.c b/arch/x86/cpu/queensbay/tnc.c
index 8637cdc..f9b3bfa 100644
--- a/arch/x86/cpu/queensbay/tnc.c
+++ b/arch/x86/cpu/queensbay/tnc.c
@@ -9,7 +9,7 @@
 #include <asm/pci.h>
 #include <asm/post.h>
 #include <asm/arch/tnc.h>
-#include <asm/arch/fsp/fsp_support.h>
+#include <asm/fsp/fsp_support.h>
 #include <asm/processor.h>
 
 static void unprotect_spi_flash(void)
diff --git a/arch/x86/cpu/queensbay/tnc_dram.c b/arch/x86/cpu/queensbay/tnc_dram.c
index df79a39..4c0a7c8 100644
--- a/arch/x86/cpu/queensbay/tnc_dram.c
+++ b/arch/x86/cpu/queensbay/tnc_dram.c
@@ -5,7 +5,7 @@
  */
 
 #include <common.h>
-#include <asm/arch/fsp/fsp_support.h>
+#include <asm/fsp/fsp_support.h>
 #include <asm/e820.h>
 #include <asm/post.h>
 
diff --git a/arch/x86/cpu/queensbay/tnc_pci.c b/arch/x86/cpu/queensbay/tnc_pci.c
index 39bff49..9b0b725 100644
--- a/arch/x86/cpu/queensbay/tnc_pci.c
+++ b/arch/x86/cpu/queensbay/tnc_pci.c
@@ -7,7 +7,7 @@
 #include <common.h>
 #include <pci.h>
 #include <asm/pci.h>
-#include <asm/arch/fsp/fsp_support.h>
+#include <asm/fsp/fsp_support.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
diff --git a/arch/x86/include/asm/arch-queensbay/fsp/fsp_api.h b/arch/x86/include/asm/fsp/fsp_api.h
similarity index 100%
rename from arch/x86/include/asm/arch-queensbay/fsp/fsp_api.h
rename to arch/x86/include/asm/fsp/fsp_api.h
diff --git a/arch/x86/include/asm/arch-queensbay/fsp/fsp_bootmode.h b/arch/x86/include/asm/fsp/fsp_bootmode.h
similarity index 100%
rename from arch/x86/include/asm/arch-queensbay/fsp/fsp_bootmode.h
rename to arch/x86/include/asm/fsp/fsp_bootmode.h
diff --git a/arch/x86/include/asm/arch-queensbay/fsp/fsp_ffs.h b/arch/x86/include/asm/fsp/fsp_ffs.h
similarity index 100%
rename from arch/x86/include/asm/arch-queensbay/fsp/fsp_ffs.h
rename to arch/x86/include/asm/fsp/fsp_ffs.h
diff --git a/arch/x86/include/asm/arch-queensbay/fsp/fsp_fv.h b/arch/x86/include/asm/fsp/fsp_fv.h
similarity index 100%
rename from arch/x86/include/asm/arch-queensbay/fsp/fsp_fv.h
rename to arch/x86/include/asm/fsp/fsp_fv.h
diff --git a/arch/x86/include/asm/arch-queensbay/fsp/fsp_hob.h b/arch/x86/include/asm/fsp/fsp_hob.h
similarity index 100%
rename from arch/x86/include/asm/arch-queensbay/fsp/fsp_hob.h
rename to arch/x86/include/asm/fsp/fsp_hob.h
diff --git a/arch/x86/include/asm/arch-queensbay/fsp/fsp_infoheader.h b/arch/x86/include/asm/fsp/fsp_infoheader.h
similarity index 100%
rename from arch/x86/include/asm/arch-queensbay/fsp/fsp_infoheader.h
rename to arch/x86/include/asm/fsp/fsp_infoheader.h
diff --git a/arch/x86/include/asm/arch-queensbay/fsp/fsp_platform.h b/arch/x86/include/asm/fsp/fsp_platform.h
similarity index 100%
rename from arch/x86/include/asm/arch-queensbay/fsp/fsp_platform.h
rename to arch/x86/include/asm/fsp/fsp_platform.h
diff --git a/arch/x86/include/asm/arch-queensbay/fsp/fsp_support.h b/arch/x86/include/asm/fsp/fsp_support.h
similarity index 99%
rename from arch/x86/include/asm/arch-queensbay/fsp/fsp_support.h
rename to arch/x86/include/asm/fsp/fsp_support.h
index ebdbd03..6329cfe 100644
--- a/arch/x86/include/asm/arch-queensbay/fsp/fsp_support.h
+++ b/arch/x86/include/asm/fsp/fsp_support.h
@@ -16,7 +16,7 @@
 #include "fsp_platform.h"
 #include "fsp_infoheader.h"
 #include "fsp_bootmode.h"
-#include "fsp_vpd.h"
+#include <asm/arch/fsp/fsp_vpd.h>
 
 struct shared_data {
 	struct fsp_header	*fsp_hdr;
diff --git a/arch/x86/include/asm/arch-queensbay/fsp/fsp_types.h b/arch/x86/include/asm/fsp/fsp_types.h
similarity index 100%
rename from arch/x86/include/asm/arch-queensbay/fsp/fsp_types.h
rename to arch/x86/include/asm/fsp/fsp_types.h
diff --git a/arch/x86/lib/Makefile b/arch/x86/lib/Makefile
index 32d7b98..c17f7f0 100644
--- a/arch/x86/lib/Makefile
+++ b/arch/x86/lib/Makefile
@@ -25,6 +25,7 @@ obj-y	+= string.o
 obj-$(CONFIG_SYS_X86_TSC_TIMER)	+= tsc_timer.o
 obj-$(CONFIG_VIDEO_VGA)	+= video.o
 obj-$(CONFIG_CMD_ZBOOT)	+= zimage.o
+obj-$(CONFIG_HAVE_FSP) += fsp/
 
 extra-$(CONFIG_USE_PRIVATE_LIBGCC) := lib.a
 
diff --git a/arch/x86/lib/cmd_hob.c b/arch/x86/lib/cmd_hob.c
index a0ef037..915746a 100644
--- a/arch/x86/lib/cmd_hob.c
+++ b/arch/x86/lib/cmd_hob.c
@@ -7,7 +7,7 @@
 #include <common.h>
 #include <command.h>
 #include <linux/compiler.h>
-#include <asm/arch/fsp/fsp_support.h>
+#include <asm/fsp/fsp_support.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
diff --git a/arch/x86/lib/fsp/Makefile b/arch/x86/lib/fsp/Makefile
new file mode 100644
index 0000000..1b9b0e2
--- /dev/null
+++ b/arch/x86/lib/fsp/Makefile
@@ -0,0 +1,7 @@
+#
+# Copyright (C) 2015 Google, Inc
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y += fsp_support.o
diff --git a/arch/x86/cpu/queensbay/fsp_support.c b/arch/x86/lib/fsp/fsp_support.c
similarity index 99%
rename from arch/x86/cpu/queensbay/fsp_support.c
rename to arch/x86/lib/fsp/fsp_support.c
index aed3e2b..f6ae85a 100644
--- a/arch/x86/cpu/queensbay/fsp_support.c
+++ b/arch/x86/lib/fsp/fsp_support.c
@@ -6,7 +6,7 @@
  */
 
 #include <common.h>
-#include <asm/arch/fsp/fsp_support.h>
+#include <asm/fsp/fsp_support.h>
 #include <asm/post.h>
 
 /**
-- 
2.2.0.rc0.207.ga3a616c

[U-Boot] [PATCH 12/23] x86: Adjust the FSP types slightly

[Simon Glass]

To avoid casts, find_fsp_header() should return a pointer. Add asmlinkage
to two API functions which use that convention. UPD_TERMINATOR is common
so move it into a common file.

Signed-off-by: Simon Glass <sjg@chromium.org>
---

 arch/x86/include/asm/arch-queensbay/fsp/fsp_vpd.h | 2 --
 arch/x86/include/asm/fsp/fsp_api.h                | 6 ++++--
 arch/x86/include/asm/fsp/fsp_support.h            | 4 +++-
 arch/x86/lib/fsp/fsp_support.c                    | 4 ++--
 4 files changed, 9 insertions(+), 7 deletions(-)

diff --git a/arch/x86/include/asm/arch-queensbay/fsp/fsp_vpd.h b/arch/x86/include/asm/arch-queensbay/fsp/fsp_vpd.h
index bce58b1..3c57558 100644
--- a/arch/x86/include/asm/arch-queensbay/fsp/fsp_vpd.h
+++ b/arch/x86/include/asm/arch-queensbay/fsp/fsp_vpd.h
@@ -10,8 +10,6 @@
 #ifndef __VPDHEADER_H__
 #define __VPDHEADER_H__
 
-#define UPD_TERMINATOR	0x55AA
-
 struct __packed upd_region {
 	u64	sign;			/* Offset 0x0000 */
 	u64	reserved;		/* Offset 0x0008 */
diff --git a/arch/x86/include/asm/fsp/fsp_api.h b/arch/x86/include/asm/fsp/fsp_api.h
index a9d7156..2d34d13 100644
--- a/arch/x86/include/asm/fsp/fsp_api.h
+++ b/arch/x86/include/asm/fsp/fsp_api.h
@@ -8,6 +8,8 @@
 #ifndef __FSP_API_H__
 #define __FSP_API_H__
 
+#include <linux/linkage.h>
+
 /*
  * FspInit continuation function prototype.
  * Control will be returned to this callback function after FspInit API call.
@@ -47,9 +49,9 @@ struct fsp_notify_params {
 };
 
 /* FspInit API function prototype */
-typedef u32 (*fsp_init_f)(struct fsp_init_params *params);
+typedef asmlinkage u32 (*fsp_init_f)(struct fsp_init_params *params);
 
 /* FspNotify API function prototype */
-typedef u32 (*fsp_notify_f)(struct fsp_notify_params *params);
+typedef asmlinkage u32 (*fsp_notify_f)(struct fsp_notify_params *params);
 
 #endif
diff --git a/arch/x86/include/asm/fsp/fsp_support.h b/arch/x86/include/asm/fsp/fsp_support.h
index 6329cfe..c6c7dc0 100644
--- a/arch/x86/include/asm/fsp/fsp_support.h
+++ b/arch/x86/include/asm/fsp/fsp_support.h
@@ -26,6 +26,8 @@ struct shared_data {
 
 #define FSP_LOWMEM_BASE		0x100000UL
 #define FSP_HIGHMEM_BASE	0x100000000ULL
+#define UPD_TERMINATOR		0x55AA
+
 
 /**
  * FSP Continuation assembly helper routine
@@ -61,7 +63,7 @@ void fsp_continue(struct shared_data *shared_data, u32 status,
  *
  * @retval: the offset of FSP header. If signature is invalid, returns 0.
  */
-u32 find_fsp_header(void);
+struct fsp_header *find_fsp_header(void);
 
 /**
  * FSP initialization wrapper function.
diff --git a/arch/x86/lib/fsp/fsp_support.c b/arch/x86/lib/fsp/fsp_support.c
index f6ae85a..bf37807 100644
--- a/arch/x86/lib/fsp/fsp_support.c
+++ b/arch/x86/lib/fsp/fsp_support.c
@@ -30,7 +30,7 @@ static bool compare_guid(const struct efi_guid *guid1,
 		return false;
 }
 
-u32 __attribute__((optimize("O0"))) find_fsp_header(void)
+struct fsp_header *__attribute__((optimize("O0"))) find_fsp_header(void)
 {
 	/*
 	 * This function may be called before the a stack is established,
@@ -84,7 +84,7 @@ u32 __attribute__((optimize("O0"))) find_fsp_header(void)
 		fsp = 0;
 	}
 
-	return (u32)fsp;
+	return (struct fsp_header *)fsp;
 }
 
 void fsp_continue(struct shared_data *shared_data, u32 status, void *hob_list)
-- 
2.2.0.rc0.207.ga3a616c

[U-Boot] [PATCH 13/23] x86: Make CAR and DRAM FSP code common

[Simon Glass]

For now this code seems to be the same for all FSP platforms. Make it
common until we see what differences are required.

Signed-off-by: Simon Glass <sjg@chromium.org>
---

 arch/x86/cpu/queensbay/Makefile                           | 2 +-
 arch/x86/lib/fsp/Makefile                                 | 2 ++
 arch/x86/{cpu/queensbay/tnc_car.S => lib/fsp/fsp_car.S}   | 0
 arch/x86/{cpu/queensbay/tnc_dram.c => lib/fsp/fsp_dram.c} | 0
 4 files changed, 3 insertions(+), 1 deletion(-)
 rename arch/x86/{cpu/queensbay/tnc_car.S => lib/fsp/fsp_car.S} (100%)
 rename arch/x86/{cpu/queensbay/tnc_dram.c => lib/fsp/fsp_dram.c} (100%)

diff --git a/arch/x86/cpu/queensbay/Makefile b/arch/x86/cpu/queensbay/Makefile
index b3e7d87..d8761fd 100644
--- a/arch/x86/cpu/queensbay/Makefile
+++ b/arch/x86/cpu/queensbay/Makefile
@@ -4,6 +4,6 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-obj-y += tnc_car.o tnc_dram.o tnc.o topcliff.o
 obj-y += fsp_configs.o
+obj-y += tnc.o topcliff.o
 obj-$(CONFIG_PCI) += tnc_pci.o
diff --git a/arch/x86/lib/fsp/Makefile b/arch/x86/lib/fsp/Makefile
index 1b9b0e2..3a2bac0 100644
--- a/arch/x86/lib/fsp/Makefile
+++ b/arch/x86/lib/fsp/Makefile
@@ -4,4 +4,6 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
+obj-y += fsp_car.o
+obj-y += fsp_dram.o
 obj-y += fsp_support.o
diff --git a/arch/x86/cpu/queensbay/tnc_car.S b/arch/x86/lib/fsp/fsp_car.S
similarity index 100%
rename from arch/x86/cpu/queensbay/tnc_car.S
rename to arch/x86/lib/fsp/fsp_car.S
diff --git a/arch/x86/cpu/queensbay/tnc_dram.c b/arch/x86/lib/fsp/fsp_dram.c
similarity index 100%
rename from arch/x86/cpu/queensbay/tnc_dram.c
rename to arch/x86/lib/fsp/fsp_dram.c
-- 
2.2.0.rc0.207.ga3a616c

[U-Boot] [PATCH 14/23] x86: Move common FSP functions into a common file

[Simon Glass]

Since these board functions seem to be the same for all boards which use
FSP, move them into a common file. We can adjust this later if future FSPs
need more flexibility.

Signed-off-by: Simon Glass <sjg@chromium.org>
---

 arch/x86/cpu/queensbay/tnc.c      | 27 ------------
 arch/x86/cpu/queensbay/tnc_pci.c  | 15 -------
 arch/x86/cpu/queensbay/topcliff.c | 32 +-------------
 arch/x86/include/asm/u-boot-x86.h | 17 ++++++++
 arch/x86/lib/fsp/Makefile         |  1 +
 arch/x86/lib/fsp/fsp_common.c     | 88 +++++++++++++++++++++++++++++++++++++++
 6 files changed, 108 insertions(+), 72 deletions(-)
 create mode 100644 arch/x86/lib/fsp/fsp_common.c

diff --git a/arch/x86/cpu/queensbay/tnc.c b/arch/x86/cpu/queensbay/tnc.c
index f9b3bfa..30ab725 100644
--- a/arch/x86/cpu/queensbay/tnc.c
+++ b/arch/x86/cpu/queensbay/tnc.c
@@ -43,30 +43,3 @@ int arch_cpu_init(void)
 
 	return 0;
 }
-
-int print_cpuinfo(void)
-{
-	post_code(POST_CPU_INFO);
-	return default_print_cpuinfo();
-}
-
-void reset_cpu(ulong addr)
-{
-	/* cold reset */
-	outb(0x06, PORT_RESET);
-}
-
-void board_final_cleanup(void)
-{
-	u32 status;
-
-	/* call into FspNotify */
-	debug("Calling into FSP (notify phase INIT_PHASE_BOOT): ");
-	status = fsp_notify(NULL, INIT_PHASE_BOOT);
-	if (status != FSP_SUCCESS)
-		debug("fail, error code %x\n", status);
-	else
-		debug("OK\n");
-
-	return;
-}
diff --git a/arch/x86/cpu/queensbay/tnc_pci.c b/arch/x86/cpu/queensbay/tnc_pci.c
index 9b0b725..6c291f9 100644
--- a/arch/x86/cpu/queensbay/tnc_pci.c
+++ b/arch/x86/cpu/queensbay/tnc_pci.c
@@ -44,18 +44,3 @@ void board_pci_setup_hose(struct pci_controller *hose)
 
 	hose->region_count = 4;
 }
-
-int board_pci_post_scan(struct pci_controller *hose)
-{
-	u32 status;
-
-	/* call into FspNotify */
-	debug("Calling into FSP (notify phase INIT_PHASE_PCI): ");
-	status = fsp_notify(NULL, INIT_PHASE_PCI);
-	if (status != FSP_SUCCESS)
-		debug("fail, error code %x\n", status);
-	else
-		debug("OK\n");
-
-	return 0;
-}
diff --git a/arch/x86/cpu/queensbay/topcliff.c b/arch/x86/cpu/queensbay/topcliff.c
index b01422a..25032cc 100644
--- a/arch/x86/cpu/queensbay/topcliff.c
+++ b/arch/x86/cpu/queensbay/topcliff.c
@@ -5,43 +5,15 @@
  */
 
 #include <common.h>
-#include <errno.h>
-#include <malloc.h>
-#include <pci.h>
 #include <pci_ids.h>
-#include <sdhci.h>
 
 static struct pci_device_id mmc_supported[] = {
 	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TCF_SDIO_0 },
 	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TCF_SDIO_1 },
-	{ }
 };
 
 int cpu_mmc_init(bd_t *bis)
 {
-	struct sdhci_host *mmc_host;
-	pci_dev_t devbusfn;
-	u32 iobase;
-	int ret;
-	int i;
-
-	for (i = 0; i < ARRAY_SIZE(mmc_supported); i++) {
-		devbusfn =  pci_find_devices(mmc_supported, i);
-		if (devbusfn == -1)
-			return -ENODEV;
-
-		mmc_host = (struct sdhci_host *)malloc(sizeof(struct sdhci_host));
-		if (!mmc_host)
-			return -ENOMEM;
-
-		mmc_host->name = "Topcliff SDHCI";
-		pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_0, &iobase);
-		mmc_host->ioaddr = (void *)iobase;
-		mmc_host->quirks = 0;
-		ret = add_sdhci(mmc_host, 0, 0);
-		if (ret)
-			return ret;
-	}
-
-	return 0;
+	return fsp_cpu_mmc_init("Topcliff SDHCI", mmc_supported,
+				ARRAY_SIZE(mmc_supported));
 }
diff --git a/arch/x86/include/asm/u-boot-x86.h b/arch/x86/include/asm/u-boot-x86.h
index b98afa8..44c24ff 100644
--- a/arch/x86/include/asm/u-boot-x86.h
+++ b/arch/x86/include/asm/u-boot-x86.h
@@ -45,6 +45,23 @@ ulong board_get_usable_ram_top(ulong total_size);
 void dram_init_banksize(void);
 int default_print_cpuinfo(void);
 
+struct pci_device_id;
+
+/**
+ * fsp_cpu_mmc_init() - set up PCI MMC devices
+ *
+ * This finds all the matching PCI IDs and sets them up as MMC devices.
+ *
+ * @name:		Name to use for devices
+ * @mmc_supported:	PCI IDs to search for
+ * @num_ids:		Number of elements in @mmc_supported
+ */
+int fsp_cpu_mmc_init(const char *name, struct pci_device_id mmc_supported[],
+		     int num_ids);
+
+/* Set up a UART which can be used with printch(), printhex8(), etc. */
+int setup_early_uart(void);
+
 void setup_pcat_compatibility(void);
 
 void isa_unmap_rom(u32 addr);
diff --git a/arch/x86/lib/fsp/Makefile b/arch/x86/lib/fsp/Makefile
index 3a2bac0..5b12c12 100644
--- a/arch/x86/lib/fsp/Makefile
+++ b/arch/x86/lib/fsp/Makefile
@@ -5,5 +5,6 @@
 #
 
 obj-y += fsp_car.o
+obj-y += fsp_common.o
 obj-y += fsp_dram.o
 obj-y += fsp_support.o
diff --git a/arch/x86/lib/fsp/fsp_common.c b/arch/x86/lib/fsp/fsp_common.c
new file mode 100644
index 0000000..846c136
--- /dev/null
+++ b/arch/x86/lib/fsp/fsp_common.c
@@ -0,0 +1,88 @@
+/*
+ * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <malloc.h>
+#include <sdhci.h>
+#include <asm/io.h>
+#include <asm/pci.h>
+#include <asm/post.h>
+#include <asm/processor.h>
+#include <asm/fsp/fsp_support.h>
+
+int print_cpuinfo(void)
+{
+	post_code(POST_CPU_INFO);
+	return default_print_cpuinfo();
+}
+
+void reset_cpu(ulong addr)
+{
+	/* cold reset */
+	outb(0x06, PORT_RESET);
+}
+
+
+int board_pci_post_scan(struct pci_controller *hose)
+{
+	u32 status;
+
+	/* call into FspNotify */
+	debug("Calling into FSP (notify phase INIT_PHASE_PCI): ");
+	status = fsp_notify(NULL, INIT_PHASE_PCI);
+	if (status != FSP_SUCCESS)
+		debug("fail, error code %x\n", status);
+	else
+		debug("OK\n");
+
+	return 0;
+}
+
+void board_final_cleanup(void)
+{
+	u32 status;
+
+	/* call into FspNotify */
+	debug("Calling into FSP (notify phase INIT_PHASE_BOOT): ");
+	status = fsp_notify(NULL, INIT_PHASE_BOOT);
+	if (status != FSP_SUCCESS)
+		debug("fail, error code %x\n", status);
+	else
+		debug("OK\n");
+
+	return;
+}
+
+int fsp_cpu_mmc_init(const char *name, struct pci_device_id mmc_supported[],
+		     int num_ids)
+{
+	struct sdhci_host *mmc_host;
+	pci_dev_t devbusfn;
+	u32 iobase;
+	int ret;
+	int i;
+
+	for (i = 0; i < num_ids; i++) {
+		devbusfn = pci_find_devices(mmc_supported, i);
+		if (devbusfn == -1)
+			return -ENODEV;
+
+		mmc_host = malloc(sizeof(struct sdhci_host));
+		if (!mmc_host)
+			return -ENOMEM;
+
+		mmc_host->name = (char *)name;
+		pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_0, &iobase);
+		mmc_host->ioaddr = (void *)iobase;
+		mmc_host->quirks = 0;
+		ret = add_sdhci(mmc_host, 0, 0);
+		if (ret)
+			return ret;
+	}
+
+	return 0;
+}
-- 
2.2.0.rc0.207.ga3a616c

[U-Boot] [PATCH 15/23] x86: Remove unnecessary casts and fix comment typos

[Simon Glass]

Tidy up the FSP support code a little.

Signed-off-by: Simon Glass <sjg@chromium.org>
---

 arch/x86/lib/fsp/fsp_support.c | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/arch/x86/lib/fsp/fsp_support.c b/arch/x86/lib/fsp/fsp_support.c
index bf37807..8b639f7 100644
--- a/arch/x86/lib/fsp/fsp_support.c
+++ b/arch/x86/lib/fsp/fsp_support.c
@@ -124,25 +124,25 @@ void fsp_init(u32 stack_top, u32 boot_mode, void *nvs_buf)
 	struct fsp_init_params *params_ptr;
 	struct upd_region *fsp_upd;
 
-	fsp_hdr = (struct fsp_header *)find_fsp_header();
+	fsp_hdr = find_fsp_header();
 	if (fsp_hdr == NULL) {
 		/* No valid FSP info header was found */
 		panic("Invalid FSP header");
 	}
 
-	fsp_upd = (struct upd_region *)&shared_data.fsp_upd;
+	fsp_upd = &shared_data.fsp_upd;
 	memset(&rt_buf, 0, sizeof(struct fspinit_rtbuf));
 
 	/* Reserve a gap in stack top */
 	rt_buf.common.stack_top = (u32 *)stack_top - 32;
 	rt_buf.common.boot_mode = boot_mode;
-	rt_buf.common.upd_data = (struct upd_region *)fsp_upd;
+	rt_buf.common.upd_data = fsp_upd;
 
 	/* Get VPD region start */
 	fsp_vpd = (struct vpd_region *)(fsp_hdr->img_base +
 			fsp_hdr->cfg_region_off);
 
-	/* Verifify the VPD data region is valid */
+	/* Verify the VPD data region is valid */
 	assert((fsp_vpd->img_rev == VPD_IMAGE_REV) &&
 	       (fsp_vpd->sign == VPD_IMAGE_ID));
 
@@ -150,7 +150,7 @@ void fsp_init(u32 stack_top, u32 boot_mode, void *nvs_buf)
 	memcpy(fsp_upd, (void *)(fsp_hdr->img_base + fsp_vpd->upd_offset),
 	       sizeof(struct upd_region));
 
-	/* Verifify the UPD data region is valid */
+	/* Verify the UPD data region is valid */
 	assert(fsp_upd->terminator == UPD_TERMINATOR);
 
 	/* Override any UPD setting if required */
-- 
2.2.0.rc0.207.ga3a616c

[U-Boot] [PATCH 16/23] x86: Allow FSP Kconfig settings for all x86

[Simon Glass]

While queensbay is the first chip with these settings, others will want to
use them too. Make them common.

Signed-off-by: Simon Glass <sjg@chromium.org>
---

 arch/x86/Kconfig               | 38 ++++++++++++++++++++++++++++++++++++++
 arch/x86/cpu/queensbay/Kconfig | 38 --------------------------------------
 2 files changed, 38 insertions(+), 38 deletions(-)

diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index 1523c91..73a7392 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -344,6 +344,44 @@ config TSC_FREQ_IN_MHZ
 	help
 	  The running frequency in MHz of Time-Stamp Counter (TSC).
 
+config HAVE_FSP
+	bool "Add an Firmware Support Package binary"
+	help
+	  Select this option to add an Firmware Support Package binary to
+	  the resulting U-Boot image. It is a binary blob which U-Boot uses
+	  to set up SDRAM and other chipset specific initialization.
+
+	  Note: Without this binary U-Boot will not be able to set up its
+	  SDRAM so will not boot.
+
+config FSP_FILE
+	string "Firmware Support Package binary filename"
+	depends on HAVE_FSP
+	default "fsp.bin"
+	help
+	  The filename of the file to use as Firmware Support Package binary
+	  in the board directory.
+
+config FSP_ADDR
+	hex "Firmware Support Package binary location"
+	depends on HAVE_FSP
+	default 0xfffc0000
+	help
+	  FSP is not Position Independent Code (PIC) and the whole FSP has to
+	  be rebased if it is placed at a location which is different from the
+	  perferred base address specified during the FSP build. Use Intel's
+	  Binary Configuration Tool (BCT) to do the rebase.
+
+	  The default base address of 0xfffc0000 indicates that the binary must
+	  be located at offset 0xc0000 from the beginning of a 1MB flash device.
+
+config FSP_TEMP_RAM_ADDR
+	hex
+	default 0x2000000
+	help
+	  Stack top address which is used in FspInit after DRAM is ready and
+	  CAR is disabled.
+
 source "arch/x86/cpu/coreboot/Kconfig"
 
 source "arch/x86/cpu/ivybridge/Kconfig"
diff --git a/arch/x86/cpu/queensbay/Kconfig b/arch/x86/cpu/queensbay/Kconfig
index f6b5201..397e599 100644
--- a/arch/x86/cpu/queensbay/Kconfig
+++ b/arch/x86/cpu/queensbay/Kconfig
@@ -11,44 +11,6 @@ config INTEL_QUEENSBAY
 
 if INTEL_QUEENSBAY
 
-config HAVE_FSP
-	bool "Add an Firmware Support Package binary"
-	help
-	  Select this option to add an Firmware Support Package binary to
-	  the resulting U-Boot image. It is a binary blob which U-Boot uses
-	  to set up SDRAM and other chipset specific initialization.
-
-	  Note: Without this binary U-Boot will not be able to set up its
-	  SDRAM so will not boot.
-
-config FSP_FILE
-	string "Firmware Support Package binary filename"
-	depends on HAVE_FSP
-	default "fsp.bin"
-	help
-	  The filename of the file to use as Firmware Support Package binary
-	  in the board directory.
-
-config FSP_ADDR
-	hex "Firmware Support Package binary location"
-	depends on HAVE_FSP
-	default 0xfffc0000
-	help
-	  FSP is not Position Independent Code (PIC) and the whole FSP has to
-	  be rebased if it is placed at a location which is different from the
-	  perferred base address specified during the FSP build. Use Intel's
-	  Binary Configuration Tool (BCT) to do the rebase.
-
-	  The default base address of 0xfffc0000 indicates that the binary must
-	  be located at offset 0xc0000 from the beginning of a 1MB flash device.
-
-config FSP_TEMP_RAM_ADDR
-	hex
-	default 0x2000000
-	help
-	  Stack top address which is used in FspInit after DRAM is ready and
-	  CAR is disabled.
-
 config HAVE_CMC
 	bool "Add a Chipset Micro Code state machine binary"
 	help
-- 
2.2.0.rc0.207.ga3a616c

[U-Boot] [PATCH 17/23] x86: Define cache line size

[Simon Glass]

This avoids a warning in the Realtek Ethernet driver. The value may not
matter on x86.

Signed-off-by: Simon Glass <sjg@chromium.org>
---

 arch/x86/include/asm/cache.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/x86/include/asm/cache.h b/arch/x86/include/asm/cache.h
index 508b63f..fff1edd 100644
--- a/arch/x86/include/asm/cache.h
+++ b/arch/x86/include/asm/cache.h
@@ -7,6 +7,8 @@
 #ifndef __X86_CACHE_H__
 #define __X86_CACHE_H__
 
+#define CONFIG_SYS_CACHELINE_SIZE	16
+
 /*
  * If CONFIG_SYS_CACHELINE_SIZE is defined use it for DMA alignment.  Otherwise
  * use 64-bytes, a safe default for x86.
-- 
2.2.0.rc0.207.ga3a616c

[U-Boot] [PATCH 18/23] x86: Allow a UART to be set up before the FSP is ready

[Simon Glass]

Since the FSP is a black box it helps to have some sort of debugging
available to check its inputs. If the debug UART is in use, set it up
after CAR is available.

Signed-off-by: Simon Glass <sjg@chromium.org>
---

 arch/x86/include/asm/u-boot-x86.h | 3 +++
 arch/x86/lib/fsp/fsp_support.c    | 4 ++++
 2 files changed, 7 insertions(+)

diff --git a/arch/x86/include/asm/u-boot-x86.h b/arch/x86/include/asm/u-boot-x86.h
index 44c24ff..85fafc0 100644
--- a/arch/x86/include/asm/u-boot-x86.h
+++ b/arch/x86/include/asm/u-boot-x86.h
@@ -62,6 +62,9 @@ int fsp_cpu_mmc_init(const char *name, struct pci_device_id mmc_supported[],
 /* Set up a UART which can be used with printch(), printhex8(), etc. */
 int setup_early_uart(void);
 
+/* Set up a UART which can be used with printch(), printhex8(), etc. */
+int setup_early_uart(void);
+
 void setup_pcat_compatibility(void);
 
 void isa_unmap_rom(u32 addr);
diff --git a/arch/x86/lib/fsp/fsp_support.c b/arch/x86/lib/fsp/fsp_support.c
index 8b639f7..5f96da1 100644
--- a/arch/x86/lib/fsp/fsp_support.c
+++ b/arch/x86/lib/fsp/fsp_support.c
@@ -124,6 +124,10 @@ void fsp_init(u32 stack_top, u32 boot_mode, void *nvs_buf)
 	struct fsp_init_params *params_ptr;
 	struct upd_region *fsp_upd;
 
+#ifdef CONFIG_DEBUG_UART
+	setup_early_uart();
+#endif
+
 	fsp_hdr = find_fsp_header();
 	if (fsp_hdr == NULL) {
 		/* No valid FSP info header was found */
-- 
2.2.0.rc0.207.ga3a616c

[U-Boot] [PATCH 19/23] x86: spi: Support ValleyView in ICH SPI driver

[Simon Glass]

The base address is found in a different way and the protection bit is also
in a different place. Otherwise it is very similar.

Signed-off-by: Simon Glass <sjg@chromium.org>
---

 drivers/spi/ich.c | 56 ++++++++++++++++++++++++++++++++++++++++---------------
 drivers/spi/ich.h | 11 ++++++-----
 2 files changed, 47 insertions(+), 20 deletions(-)

diff --git a/drivers/spi/ich.c b/drivers/spi/ich.c
index fdff158..da85779 100644
--- a/drivers/spi/ich.c
+++ b/drivers/spi/ich.c
@@ -7,6 +7,7 @@
  */
 
 #include <common.h>
+#include <errno.h>
 #include <malloc.h>
 #include <spi.h>
 #include <pci.h>
@@ -21,6 +22,7 @@
 struct ich_ctlr {
 	pci_dev_t dev;		/* PCI device number */
 	int ich_version;	/* Controller version, 7 or 9 */
+	bool use_sbase;		/* Use SBASE instead of RCB */
 	int ichspi_lock;
 	int locked;
 	uint8_t *opmenu;
@@ -145,7 +147,7 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
 	 * ICH 7 SPI controller only supports array read command
 	 * and byte program command for SST flash
 	 */
-	if (ctlr.ich_version == 7) {
+	if (ctlr.ich_version == 7 || ctlr.use_sbase) {
 		ich->slave.op_mode_rx = SPI_OPM_RX_AS;
 		ich->slave.op_mode_tx = SPI_OPM_TX_BP;
 	}
@@ -181,7 +183,8 @@ static int get_ich_version(uint16_t device_id)
 	if ((device_id >= PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_MIN &&
 	     device_id <= PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_MAX) ||
 	    (device_id >= PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_MIN &&
-	     device_id <= PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_MAX))
+	     device_id <= PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_MAX) ||
+	    device_id == PCI_DEVICE_ID_INTEL_VALLEYVIEW_LPC)
 		return 9;
 
 	return 0;
@@ -204,14 +207,14 @@ static int ich9_can_do_33mhz(pci_dev_t dev)
 	return speed == 1;
 }
 
-static int ich_find_spi_controller(pci_dev_t *devp, int *ich_versionp)
+static int ich_find_spi_controller(struct ich_ctlr *ich)
 {
 	int last_bus = pci_last_busno();
 	int bus;
 
 	if (last_bus == -1) {
 		debug("No PCI busses?\n");
-		return -1;
+		return -ENODEV;
 	}
 
 	for (bus = 0; bus <= last_bus; bus++) {
@@ -225,24 +228,33 @@ static int ich_find_spi_controller(pci_dev_t *devp, int *ich_versionp)
 		device_id = ids >> 16;
 
 		if (vendor_id == PCI_VENDOR_ID_INTEL) {
-			*devp = dev;
-			*ich_versionp = get_ich_version(device_id);
-			return 0;
+			ich->dev = dev;
+			ich->ich_version = get_ich_version(device_id);
+			if (device_id == PCI_DEVICE_ID_INTEL_VALLEYVIEW_LPC)
+				ich->use_sbase = true;
+			return ich->ich_version == 0 ? -ENODEV : 0;
 		}
 	}
 
 	debug("ICH SPI: No ICH found.\n");
-	return -1;
+	return -ENODEV;
 }
 
 static int ich_init_controller(struct ich_ctlr *ctlr)
 {
 	uint8_t *rcrb; /* Root Complex Register Block */
 	uint32_t rcba; /* Root Complex Base Address */
+	uint32_t sbase_addr;
+	uint8_t *sbase;
 
 	pci_read_config_dword(ctlr->dev, 0xf0, &rcba);
 	/* Bits 31-14 are the base address, 13-1 are reserved, 0 is enable. */
 	rcrb = (uint8_t *)(rcba & 0xffffc000);
+
+	/* SBASE is similar */
+	pci_read_config_dword(ctlr->dev, 0x54, &sbase_addr);
+	sbase = (uint8_t *)(sbase_addr & 0xfffffe00);
+
 	if (ctlr->ich_version == 7) {
 		struct ich7_spi_regs *ich7_spi;
 
@@ -262,7 +274,10 @@ static int ich_init_controller(struct ich_ctlr *ctlr)
 	} else if (ctlr->ich_version == 9) {
 		struct ich9_spi_regs *ich9_spi;
 
-		ich9_spi = (struct ich9_spi_regs *)(rcrb + 0x3800);
+		if (ctlr->use_sbase)
+			ich9_spi = (struct ich9_spi_regs *)sbase;
+		else
+			ich9_spi = (struct ich9_spi_regs *)(rcrb + 0x3800);
 		ctlr->ichspi_lock = ich_readw(&ich9_spi->hsfs) & HSFS_FLOCKDN;
 		ctlr->opmenu = ich9_spi->opmenu;
 		ctlr->menubytes = sizeof(ich9_spi->opmenu);
@@ -282,12 +297,13 @@ static int ich_init_controller(struct ich_ctlr *ctlr)
 		      ctlr->ich_version);
 		return -1;
 	}
-	debug("ICH SPI: Version %d detected\n", ctlr->ich_version);
 
 	/* Work out the maximum speed we can support */
 	ctlr->max_speed = 20000000;
 	if (ctlr->ich_version == 9 && ich9_can_do_33mhz(ctlr->dev))
 		ctlr->max_speed = 33000000;
+	debug("ICH SPI: Version %d detected at %p, speed %ld\n",
+	      ctlr->ich_version, ctlr->base, ctlr->max_speed);
 
 	ich_set_bbar(ctlr, 0);
 
@@ -298,7 +314,7 @@ void spi_init(void)
 {
 	uint8_t bios_cntl;
 
-	if (ich_find_spi_controller(&ctlr.dev, &ctlr.ich_version)) {
+	if (ich_find_spi_controller(&ctlr)) {
 		printf("ICH SPI: Cannot find device\n");
 		return;
 	}
@@ -312,10 +328,20 @@ void spi_init(void)
 	 * Disable the BIOS write protect so write commands are allowed.  On
 	 * v9, deassert SMM BIOS Write Protect Disable.
 	 */
-	pci_read_config_byte(ctlr.dev, 0xdc, &bios_cntl);
-	if (ctlr.ich_version == 9)
-		bios_cntl &= ~(1 << 5);
-	pci_write_config_byte(ctlr.dev, 0xdc, bios_cntl | 0x1);
+	if (ctlr.use_sbase) {
+		struct ich9_spi_regs *ich9_spi;
+
+		ich9_spi = (struct ich9_spi_regs *)ctlr.base;
+		bios_cntl = ich_readb(&ich9_spi->bcr);
+		bios_cntl &= ~(1 << 5);	/* clear Enable InSMM_STS (EISS) */
+		bios_cntl |= 1;		/* Write Protect Disable (WPD) */
+		ich_writeb(bios_cntl, &ich9_spi->bcr);
+	} else {
+		pci_read_config_byte(ctlr.dev, 0xdc, &bios_cntl);
+		if (ctlr.ich_version == 9)
+			bios_cntl &= ~(1 << 5);
+		pci_write_config_byte(ctlr.dev, 0xdc, bios_cntl | 0x1);
+	}
 }
 
 int spi_claim_bus(struct spi_slave *slave)
diff --git a/drivers/spi/ich.h b/drivers/spi/ich.h
index d2e4b85..1419b23 100644
--- a/drivers/spi/ich.h
+++ b/drivers/spi/ich.h
@@ -37,18 +37,19 @@ struct ich9_spi_regs {
 	uint8_t opmenu[8];		/* 0x98 */
 	uint32_t bbar;
 	uint8_t _reserved3[12];
-	uint32_t fdoc;
+	uint32_t fdoc;			/* 0xb0 */
 	uint32_t fdod;
 	uint8_t _reserved4[8];
-	uint32_t afc;
+	uint32_t afc;			/* 0xc0 */
 	uint32_t lvscc;
 	uint32_t uvscc;
 	uint8_t _reserved5[4];
-	uint32_t fpb;
+	uint32_t fpb;			/* 0xd0 */
 	uint8_t _reserved6[28];
-	uint32_t srdl;
+	uint32_t srdl;			/* 0xf0 */
 	uint32_t srdc;
-	uint32_t srd;
+	uint32_t scs;
+	uint32_t bcr;
 } __packed;
 
 enum {
-- 
2.2.0.rc0.207.ga3a616c

[U-Boot] [PATCH 20/23] scsi: bootstage: Measure time taken to scan the bus

[Simon Glass]

On some hardware this time can be significant. Add bootstage support for
measuring this. The result can be obtained using 'bootstage report' or
passed on to the Linux via the device tree.

Signed-off-by: Simon Glass <sjg@chromium.org>
---

 common/cmd_scsi.c   | 2 ++
 include/bootstage.h | 1 +
 2 files changed, 3 insertions(+)

diff --git a/common/cmd_scsi.c b/common/cmd_scsi.c
index cbc107e..a0a62eb 100644
--- a/common/cmd_scsi.c
+++ b/common/cmd_scsi.c
@@ -217,8 +217,10 @@ void scsi_init(void)
 		       (busdevfunc >> 8) & 0x7);
 	}
 #endif
+	bootstage_start(BOOTSTAGE_ID_ACCUM_SCSI, "ahci");
 	scsi_low_level_init(busdevfunc);
 	scsi_scan(1);
+	bootstage_accum(BOOTSTAGE_ID_ACCUM_SCSI);
 }
 #endif
 
diff --git a/include/bootstage.h b/include/bootstage.h
index df13ab2..6b7588d 100644
--- a/include/bootstage.h
+++ b/include/bootstage.h
@@ -194,6 +194,7 @@ enum bootstage_id {
 	BOOTSTAGE_ID_MAIN_CPU_READY,
 
 	BOOTSTAGE_ID_ACCUM_LCD,
+	BOOTSTAGE_ID_ACCUM_SCSI,
 
 	/* a few spare for the user, from here */
 	BOOTSTAGE_ID_USER,
-- 
2.2.0.rc0.207.ga3a616c

[U-Boot] [PATCH 21/23] x86: Enable bootstage features

[Simon Glass]

Allow measuring of boot time using bootstage.

Signed-off-by: Simon Glass <sjg@chromium.org>
---

 include/configs/x86-common.h | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/include/configs/x86-common.h b/include/configs/x86-common.h
index ecedfc3..66d4894 100644
--- a/include/configs/x86-common.h
+++ b/include/configs/x86-common.h
@@ -245,6 +245,9 @@
 #define CONFIG_BOOTP_GATEWAY
 #define CONFIG_BOOTP_HOSTNAME
 
+#define CONFIG_BOOTSTAGE
+#define CONFIG_CMD_BOOTSTAGE
+
 #define CONFIG_CMD_USB
 
 #define CONFIG_EXTRA_ENV_SETTINGS \
-- 
2.2.0.rc0.207.ga3a616c

[U-Boot] [PATCH 22/23] x86: Add some documentation on how to port U-Boot on x86

[Simon Glass]

Some information has been gleaned on tools and procedures for porting
U-Boot to different x86 platforms. Add a few notes to start things off.

Signed-off-by: Simon Glass <sjg@chromium.org>
---

 doc/README.x86 | 63 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 63 insertions(+)

diff --git a/doc/README.x86 b/doc/README.x86
index 809a291..0e4628a 100644
--- a/doc/README.x86
+++ b/doc/README.x86
@@ -164,6 +164,69 @@ mtrr - List and set the Memory Type Range Registers (MTRR). These are used to
 	 mode to use. U-Boot sets up some reasonable values but you can
 	 adjust then with this command.
 
+Development Flow
+----------------
+
+These notes are for those who want to port U-Boot to a new x86 platform.
+
+Since x86 CPUs boot from SPI flash, a SPI flash emulator is a good investment.
+The Dediprog em100 can be used on Linux. The em100 tool is available here:
+
+   http://review.coreboot.org/p/em100.git
+
+On Minnowboard Max the following command line can be used:
+
+   sudo em100 -s -p LOW -d u-boot.rom -c W25Q64DW -r
+
+A suitable clip for connecting over the SPI flash chip is here:
+
+   http://www.dediprog.com/pd/programmer-accessories/EM-TC-8
+
+This allows you to override the SPI flash contents for development purposes.
+Typically you can write to the em100 in around 1200ms, considerably faster
+than programming the real flash device each time. The only important
+limitation of the em100 is that it only supports SPI bus speeds up to 20MHz.
+This means that images must be set to boot with that speed (Intel-specific
+feature).
+
+If your chip/board uses an Intel Firmware Support Package (FSP) it is fairly
+easy to fit it in. You can follow the Minnowboard Max implementation, for
+example. Hopefully you will just need to create new files similar to those
+in arch/x86/cpu/baytrail which provide Bay Trail support.
+
+If you are not using an FSP you have more freedom and more responsibility.
+The ivybridge support works this way, although it still uses a ROM for
+graphics and still has binary blobs containing Intel code. You should aim to
+support all important peripherals on your platform including video and storage.
+Use the device tree for configuration where possible.
+
+For the microcode you can create a suitable device tree file using the
+microcode tool:
+
+  ./tools/microcode-tool -d microcode.dat create <model>
+
+or if you only have header files and not the full Intel microcode.dat database:
+
+  ./tools/microcode-tool -H BAY_TRAIL_FSP_KIT/Microcode/M0130673322.h \
+	-H BAY_TRAIL_FSP_KIT/Microcode/M0130679901.h \
+	create all
+
+These are written to arch/x86/dts/microcode/ by default.
+
+Note that it is possible to just add the micrcode for your CPU if you know its
+model. U-Boot prints this information when it starts
+
+   CPU: x86_64, vendor Intel, device 30673h
+
+so here we can use the M0130673322 file.
+
+If you platform can display POST codes on two little 7-segment displays on
+the board, then you can use post_code() calls from C or assembler to monitor
+boot progress. This can be good for debugging.
+
+If not, you can try to get serial working as early as possible. The early
+debug serial port may be useful here. See setup_early_uart() for an example.
+
 TODO List
 ---------
 - Audio
-- 
2.2.0.rc0.207.ga3a616c

[U-Boot] [PATCH 23/23] x86: Add support for Intel Minnowboard Max

[Simon Glass]

This is a relatively low-cost x86 board in a small form factor. The main
peripherals are uSD, USB, HDMI, Ethernet and SATA. It uses an Atom 3800
series CPU. So far only the dual core 2GB variant is supported.

This uses the existing FSP support. Binary blobs are required to make this
board work. The microcode update is included as a patch (all 3000 lines of
it).

Signed-off-by: Simon Glass <sjg@chromium.org>
---

 arch/x86/Kconfig                                 |   12 +
 arch/x86/cpu/Makefile                            |    1 +
 arch/x86/cpu/baytrail/Kconfig                    |    9 +
 arch/x86/cpu/baytrail/Makefile                   |   10 +
 arch/x86/cpu/baytrail/early_uart.c               |   82 +
 arch/x86/cpu/baytrail/fsp_configs.c              |  156 +
 arch/x86/cpu/baytrail/pci.c                      |   47 +
 arch/x86/cpu/baytrail/valleyview.c               |   37 +
 arch/x86/dts/Makefile                            |    3 +-
 arch/x86/dts/microcode/m0130673322.dtsi          | 3284 ++++++++++++++++++++++
 arch/x86/dts/minnowmax.dts                       |   45 +
 arch/x86/dts/serial.dtsi                         |    2 +-
 arch/x86/include/asm/arch-baytrail/fsp/azalia.h  |   39 +
 arch/x86/include/asm/arch-baytrail/fsp/fsp_vpd.h |   95 +
 arch/x86/include/asm/arch-baytrail/gpio.h        |   13 +
 board/intel/minnowmax/Kconfig                    |   31 +
 board/intel/minnowmax/MAINTAINERS                |    6 +
 board/intel/minnowmax/Makefile                   |    7 +
 board/intel/minnowmax/minnowmax.c                |   32 +
 board/intel/minnowmax/start.S                    |    9 +
 configs/minnowmax_defconfig                      |   13 +
 doc/README.x86                                   |   49 +-
 include/configs/minnowmax.h                      |   69 +
 23 files changed, 4043 insertions(+), 8 deletions(-)
 create mode 100644 arch/x86/cpu/baytrail/Kconfig
 create mode 100644 arch/x86/cpu/baytrail/Makefile
 create mode 100644 arch/x86/cpu/baytrail/early_uart.c
 create mode 100644 arch/x86/cpu/baytrail/fsp_configs.c
 create mode 100644 arch/x86/cpu/baytrail/pci.c
 create mode 100644 arch/x86/cpu/baytrail/valleyview.c
 create mode 100644 arch/x86/dts/microcode/m0130673322.dtsi
 create mode 100644 arch/x86/dts/minnowmax.dts
 create mode 100644 arch/x86/include/asm/arch-baytrail/fsp/azalia.h
 create mode 100644 arch/x86/include/asm/arch-baytrail/fsp/fsp_vpd.h
 create mode 100644 arch/x86/include/asm/arch-baytrail/gpio.h
 create mode 100644 board/intel/minnowmax/Kconfig
 create mode 100644 board/intel/minnowmax/MAINTAINERS
 create mode 100644 board/intel/minnowmax/Makefile
 create mode 100644 board/intel/minnowmax/minnowmax.c
 create mode 100644 board/intel/minnowmax/start.S
 create mode 100644 configs/minnowmax_defconfig
 create mode 100644 include/configs/minnowmax.h

diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index 73a7392..49bd76f 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -41,6 +41,14 @@ config TARGET_CROWNBAY
 	  Intel Platform Controller Hub EG20T, other system components and
 	  peripheral connectors for PCIe/SATA/USB/LAN/SD/UART/Audio/LVDS.
 
+config TARGET_MINNOWMAX
+	bool "Support Intel Minnowboard MAX"
+	help
+	  This is the Intel Minnowboard MAX. It contains an Atom E3800
+	  processor in a small form factor with Ethernet, micro-SD, USB 2,
+	  USB 3, SATA, serial console, some GPIOs and HDMI 1.3 video out.
+	  It requires some binary blobs - see README.x86 for details.
+
 endchoice
 
 config RAMBASE
@@ -388,12 +396,16 @@ source "arch/x86/cpu/ivybridge/Kconfig"
 
 source "arch/x86/cpu/queensbay/Kconfig"
 
+source "arch/x86/cpu/baytrail/Kconfig"
+
 source "board/coreboot/coreboot/Kconfig"
 
 source "board/google/chromebook_link/Kconfig"
 
 source "board/intel/crownbay/Kconfig"
 
+source "board/intel/minnowmax/Kconfig"
+
 config MMCONF_BASE_ADDRESS
 	hex
         default 0xe0000000
diff --git a/arch/x86/cpu/Makefile b/arch/x86/cpu/Makefile
index 62e43c0..5acf8bb 100644
--- a/arch/x86/cpu/Makefile
+++ b/arch/x86/cpu/Makefile
@@ -12,6 +12,7 @@ extra-y	= start.o
 obj-$(CONFIG_X86_RESET_VECTOR) += resetvec.o start16.o
 obj-y	+= interrupts.o cpu.o call64.o
 
+obj-$(CONFIG_INTEL_BAYTRAIL) += baytrail/
 obj-$(CONFIG_SYS_COREBOOT) += coreboot/
 obj-$(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE) += ivybridge/
 obj-$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE) += ivybridge/
diff --git a/arch/x86/cpu/baytrail/Kconfig b/arch/x86/cpu/baytrail/Kconfig
new file mode 100644
index 0000000..e86cc01
--- /dev/null
+++ b/arch/x86/cpu/baytrail/Kconfig
@@ -0,0 +1,9 @@
+#
+# Copyright (C) 2015 Google, Inc
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+config INTEL_BAYTRAIL
+	bool
+	select HAVE_FSP
diff --git a/arch/x86/cpu/baytrail/Makefile b/arch/x86/cpu/baytrail/Makefile
new file mode 100644
index 0000000..8914e8b
--- /dev/null
+++ b/arch/x86/cpu/baytrail/Makefile
@@ -0,0 +1,10 @@
+#
+# Copyright (C) 2015 Google, Inc
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y += early_uart.o
+obj-y += fsp_configs.o
+obj-y += pci.o
+obj-y += valleyview.o
diff --git a/arch/x86/cpu/baytrail/early_uart.c b/arch/x86/cpu/baytrail/early_uart.c
new file mode 100644
index 0000000..c54deb9
--- /dev/null
+++ b/arch/x86/cpu/baytrail/early_uart.c
@@ -0,0 +1,82 @@
+/*
+ * Copyright (C) 2015 Google, Inc
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <debug_uart.h>
+#include <errno.h>
+#include <asm/io.h>
+
+#define PCI_DEV_CONFIG(segbus, dev, fn) ( \
+		(((segbus) & 0xfff) << 20) | \
+		(((dev) & 0x1f) << 15) | \
+		(((fn)  & 0x07) << 12))
+
+/* Platform Controller Unit */
+#define LPC_DEV			0x1f
+#define LPC_FUNC		0
+
+/* Enable UART */
+#define UART_CONT		0x80
+
+/* SCORE Pad definitions */
+#define UART_RXD_PAD			82
+#define UART_TXD_PAD			83
+
+/* Pad base: PAD_CONF0[n]= PAD_BASE + 16 * n */
+#define GPSCORE_PAD_BASE	(IO_BASE_ADDRESS + IO_BASE_OFFSET_GPSCORE)
+
+/* IO Memory */
+#define IO_BASE_ADDRESS			0xfed0c000
+#define  IO_BASE_OFFSET_GPSCORE		0x0000
+#define  IO_BASE_OFFSET_GPNCORE		0x1000
+#define  IO_BASE_OFFSET_GPSSUS		0x2000
+#define IO_BASE_SIZE			0x4000
+
+static inline unsigned int score_pconf0(int pad_num)
+{
+	return GPSCORE_PAD_BASE + pad_num * 16;
+}
+
+static void score_select_func(int pad, int func)
+{
+	uint32_t reg;
+	uint32_t pconf0_addr = score_pconf0(pad);
+
+	reg = readl(pconf0_addr);
+	reg &= ~0x7;
+	reg |= func & 0x7;
+	writel(reg, pconf0_addr);
+}
+
+static void pci_write_config32(int dev, unsigned int where, u32 value)
+{
+	unsigned long addr;
+
+	addr = CONFIG_MMCONF_BASE_ADDRESS | dev | (where & ~3);
+	writel(value, addr);
+}
+
+/* This can be called after memory-mapped PCI is working */
+int setup_early_uart(void)
+{
+	if (!IS_ENABLED(CONFIG_DEBUG_UART))
+		return -ENOSYS;
+
+	/* Enable the legacy UART hardware. */
+	pci_write_config32(PCI_DEV_CONFIG(0, LPC_DEV, LPC_FUNC), UART_CONT, 1);
+
+	/*
+	 * Set up the pads to the UART function. This allows the signals to
+	 * leave the chip
+	 */
+	score_select_func(UART_RXD_PAD, 1);
+	score_select_func(UART_TXD_PAD, 1);
+
+	debug_uart_init();
+	printascii("Debug UART ready\r\n");
+
+	return 0;
+}
diff --git a/arch/x86/cpu/baytrail/fsp_configs.c b/arch/x86/cpu/baytrail/fsp_configs.c
new file mode 100644
index 0000000..86b6926
--- /dev/null
+++ b/arch/x86/cpu/baytrail/fsp_configs.c
@@ -0,0 +1,156 @@
+/*
+ * Copyright (C) 2013, Intel Corporation
+ * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier:	Intel
+ */
+
+#include <common.h>
+#include <asm/arch/fsp/azalia.h>
+#include <asm/fsp/fsp_support.h>
+
+/* ALC262 Verb Table - 10EC0262 */
+static const uint32_t verb_table_data13[] = {
+	/* Pin Complex (NID 0x11) */
+	0x01171cf0,
+	0x01171d11,
+	0x01171e11,
+	0x01171f41,
+	/* Pin Complex (NID 0x12) */
+	0x01271cf0,
+	0x01271d11,
+	0x01271e11,
+	0x01271f41,
+	/* Pin Complex (NID 0x14) */
+	0x01471c10,
+	0x01471d40,
+	0x01471e01,
+	0x01471f01,
+	/* Pin Complex (NID 0x15) */
+	0x01571cf0,
+	0x01571d11,
+	0x01571e11,
+	0x01571f41,
+	/* Pin Complex (NID 0x16) */
+	0x01671cf0,
+	0x01671d11,
+	0x01671e11,
+	0x01671f41,
+	/* Pin Complex (NID 0x18) */
+	0x01871c20,
+	0x01871d98,
+	0x01871ea1,
+	0x01871f01,
+	/* Pin Complex (NID 0x19) */
+	0x01971c21,
+	0x01971d98,
+	0x01971ea1,
+	0x01971f02,
+	/* Pin Complex (NID 0x1A) */
+	0x01a71c2f,
+	0x01a71d30,
+	0x01a71e81,
+	0x01a71f01,
+	/* Pin Complex */
+	0x01b71c1f,
+	0x01b71d40,
+	0x01b71e21,
+	0x01b71f02,
+	/* Pin Complex */
+	0x01c71cf0,
+	0x01c71d11,
+	0x01c71e11,
+	0x01c71f41,
+	/* Pin Complex */
+	0x01d71c01,
+	0x01d71dc6,
+	0x01d71e14,
+	0x01d71f40,
+	/* Pin Complex */
+	0x01e71cf0,
+	0x01e71d11,
+	0x01e71e11,
+	0x01e71f41,
+	/* Pin Complex */
+	0x01f71cf0,
+	0x01f71d11,
+	0x01f71e11,
+	0x01f71f41,
+};
+
+/*
+ * This needs to be in ROM since if we put it in CAR, FSP init loses it when
+ * it drops CAR.
+ *
+ * TODO(sjg at chromium.org): Move to device tree when FSP allows it
+ *
+ * VerbTable: (RealTek ALC262)
+ * Revision ID = 0xFF, support all steps
+ * Codec Verb Table For AZALIA
+ * Codec Address: CAd value (0/1/2)
+ * Codec Vendor: 0x10EC0262
+ */
+static const struct pch_azalia_verb_table azalia_verb_table[] = {
+	{
+		{
+			0x10ec0262,
+			0x0000,
+			0xff,
+			0x01,
+			0x000b,
+			0x0002,
+		},
+		verb_table_data13
+	}
+};
+
+const struct pch_azalia_config azalia_config = {
+	.pme_enable = 1,
+	.docking_supported = 1,
+	.docking_attached = 0,
+	.hdmi_codec_enable = 1,
+	.azalia_v_ci_enable = 1,
+	.rsvdbits = 0,
+	.azalia_verb_table_num = 1,
+	.azalia_verb_table = azalia_verb_table,
+	.reset_wait_timer_us = 300
+};
+
+void update_fsp_upd(struct upd_region *fsp_upd)
+{
+	struct memory_down_data *mem;
+
+	/*
+	 * Configure everything here to avoid the poor hard-pressed user
+	 * needing to run Intel's binary configuration tool. It may also allow
+	 * us to support the 1GB single core variant easily.
+	 *
+	 * TODO(sjg at chromium.org): Move to device tree
+	 */
+	fsp_upd->mrc_init_tseg_size = 8;
+	fsp_upd->mrc_init_mmio_size = 0x800;
+	fsp_upd->emmc_boot_mode = 0xff;
+	fsp_upd->enable_sdio = 1;
+	fsp_upd->enable_sdcard = 1;
+	fsp_upd->enable_hsuart0 = 1;
+	fsp_upd->azalia_config_ptr = (uint32_t)&azalia_config;
+	fsp_upd->enable_i2_c0 = 0;
+	fsp_upd->enable_i2_c2 = 0;
+	fsp_upd->enable_i2_c3 = 0;
+	fsp_upd->enable_i2_c4 = 0;
+	fsp_upd->enable_xhci = 0;
+	fsp_upd->igd_render_standby = 1;
+
+	mem = &fsp_upd->memory_params;
+	mem->enable_memory_down = 1;
+	mem->dram_speed = 1;
+	mem->dimm_width = 1;
+	mem->dimm_density = 2;
+	mem->dimm_tcl = 0xb;
+	mem->dimm_trpt_rcd = 0xb;
+	mem->dimm_twr = 0xc;
+	mem->dimm_twtr = 6;
+	mem->dimm_trrd = 6;
+	mem->dimm_trtp = 6;
+	mem->dimm_tfaw = 0x14;
+}
diff --git a/arch/x86/cpu/baytrail/pci.c b/arch/x86/cpu/baytrail/pci.c
new file mode 100644
index 0000000..7032c97
--- /dev/null
+++ b/arch/x86/cpu/baytrail/pci.c
@@ -0,0 +1,47 @@
+/*
+ * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <debug_uart.h>
+#include <pci.h>
+#include <asm/pci.h>
+#include <asm/fsp/fsp_support.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void board_pci_setup_hose(struct pci_controller *hose)
+{
+	hose->first_busno = 0;
+	hose->last_busno = 0;
+
+	/* PCI memory space */
+	pci_set_region(hose->regions + 0,
+		       CONFIG_PCI_MEM_BUS,
+		       CONFIG_PCI_MEM_PHYS,
+		       CONFIG_PCI_MEM_SIZE,
+		       PCI_REGION_MEM);
+
+	/* PCI IO space */
+	pci_set_region(hose->regions + 1,
+		       CONFIG_PCI_IO_BUS,
+		       CONFIG_PCI_IO_PHYS,
+		       CONFIG_PCI_IO_SIZE,
+		       PCI_REGION_IO);
+
+	pci_set_region(hose->regions + 2,
+		       CONFIG_PCI_PREF_BUS,
+		       CONFIG_PCI_PREF_PHYS,
+		       CONFIG_PCI_PREF_SIZE,
+		       PCI_REGION_PREFETCH);
+
+	pci_set_region(hose->regions + 3,
+		       0,
+		       0,
+		       gd->ram_size,
+		       PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
+
+	hose->region_count = 4;
+}
diff --git a/arch/x86/cpu/baytrail/valleyview.c b/arch/x86/cpu/baytrail/valleyview.c
new file mode 100644
index 0000000..ab89b54
--- /dev/null
+++ b/arch/x86/cpu/baytrail/valleyview.c
@@ -0,0 +1,37 @@
+/*
+ * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <pci_ids.h>
+#include <asm/post.h>
+
+static struct pci_device_id mmc_supported[] = {
+	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_VALLEYVIEW_SDIO },
+	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_VALLEYVIEW_SDCARD },
+};
+
+int cpu_mmc_init(bd_t *bis)
+{
+	printf("mmc init\n");
+	return fsp_cpu_mmc_init("ValleyView SDHCI", mmc_supported,
+				ARRAY_SIZE(mmc_supported));
+}
+
+int arch_cpu_init(void)
+{
+	int ret;
+
+	post_code(POST_CPU_INIT);
+#ifdef CONFIG_SYS_X86_TSC_TIMER
+	timer_set_base(rdtsc());
+#endif
+
+	ret = x86_cpu_init_f();
+	if (ret)
+		return ret;
+
+	return 0;
+}
diff --git a/arch/x86/dts/Makefile b/arch/x86/dts/Makefile
index 97ed884..4e0171a 100644
--- a/arch/x86/dts/Makefile
+++ b/arch/x86/dts/Makefile
@@ -1,5 +1,6 @@
 dtb-y += chromebook_link.dtb \
-	crownbay.dtb
+	crownbay.dtb \
+	minnowmax.dtb
 
 targets += $(dtb-y)
 
diff --git a/arch/x86/dts/microcode/m0130673322.dtsi b/arch/x86/dts/microcode/m0130673322.dtsi
new file mode 100644
index 0000000..90bf2fb
--- /dev/null
+++ b/arch/x86/dts/microcode/m0130673322.dtsi
@@ -0,0 +1,3284 @@
+/*
+ * ---
+ * This is a device tree fragment. Use #include to add these properties to a
+ * node.
+ *
+ * Date:
+ */
+
+compatible = "intel,microcode";
+intel,header-version = <1>;
+intel,update-revision = <0x322>;
+intel,date-code = <0x4012014>;
+intel,processor-signature = <0x30673>;
+intel,checksum = <0x17b0d914>;
+intel,loader-revision = <1>;
+intel,processor-flags = <0x1>;
+
+/* The first 48-bytes are the public header which repeats the above data */
+data = <
+	0x01000000	0x22030000	0x14200104	0x73060300
+	0x14d9b017	0x01000000	0x01000000	0xd0cb0000
+	0x00cc0000	0x00000000	0x00000000	0x00000000
+	0x00000000	0xa1000000	0x01000200	0x22030000
+	0x00000000	0x00000000	0x31031420	0x11320000
+	0x01000000	0x73060300	0x00000000	0x00000000
+	0x00000000	0x00000000	0x00000000	0x00000000
+	0x00000000	0xf4320000	0x00000000	0x00000000
+	0x00000000	0x00000000	0x00000000	0x00000000
+	0x0ae10178	0x7c98f9d1	0x41962d85	0x19391270
+	0xcf3c0336	0xc1f13d6f	0xe46abaf6	0x3b65ca6b
+	0xdb666815	0x5a17bfc4	0x4fca009d	0x099ae8b3
+	0x198e2c7d	0x7c665bbf	0xc07a1a7a	0x7dbcee26
+	0x867296b2	0xc885b6ce	0xe602baff	0x68544b14
+	0xc928c400	0x3add156d	0x531946f9	0x92a03216
+	0xda352322	0xd967ee1f	0x3c5170a7	0xf6de834e
+	0x5a2ed8b3	0x9fb8f050	0x450de17f	0xfd5ef070
+	0x4954575f	0xa3a071ab	0xb56e2afb	0xe2b48302
+	0x6655a958	0x57c9a438	0x1b2f688a	0x09309bc4
+	0x0be95612	0x529c1633	0xc48515d9	0x29eb78df
+	0x9933409f	0xda58dea9	0x58c805fd	0xbc110f5a
+	0x40780ec0	0x6ad59bb3	0xc7387fb8	0x591c1490
+	0xf9335932	0x32130e0b	0xef4b3c96	0xacd903f2
+	0x5b362539	0xe7f85529	0xcb17c41f	0xe7e440d8
+	0xfaf7e925	0x969b76fb	0x5edab8c7	0xf00012e8
+	0x121c2971	0xe5b18959	0xadfd07c0	0x1f09c9d7
+	0x9781006a	0x39550073	0x6c438b6d	0x436f60bc
+	0x11000000	0x8514b971	0x40df7b4a	0x6a6b7285
+	0x7978ef59	0x319bddf5	0x04c68e5a	0xe1c28b10
+	0x172f63dc	0x306fb95d	0x31d881e8	0x69f8e08d
+	0x617a99e1	0x1ab6b574	0x2951fa5b	0xcc7e3e94
+	0xff379d19	0x5c035dec	0xe28ed726	0x22b8a5ac
+	0xd08b3ac5	0x45c03b9e	0xcea4083c	0xc26758aa
+	0xbe7cf81e	0x43d898f3	0x5c45a635	0xc9cac095
+	0xb89aea20	0x2c02b40e	0xe3a8b48d	0xeabfb60e
+	0x776ed2a9	0x080ae6d5	0x7f64b1df	0x00e40ee6
+	0x0f1c10f4	0x792e5423	0x787f5459	0x63a8b02c
+	0x3fd6a255	0x049cae26	0x0949f5ff	0x9aebb236
+	0xecc01775	0x91b57b84	0xe0e45ea3	0x5a8bf79e
+	0x356a843a	0x2406795f	0x8aaae5d8	0x6a8c877c
+	0xa8b2b8f4	0x04cf8f49	0x422d9e2c	0xf09f9896
+	0xe9b92215	0x9c98fb44	0x88556b7f	0x519d6f4c
+	0x9e8a016b	0xcb18d16c	0x419b4ee7	0x080b49c8
+	0xc51b875e	0x46aabc9c	0x262d27eb	0x93ea189d
+	0xdd0da69d	0x3e5b17e8	0xcc78509a	0x00b07e6e
+	0x363d5a70	0x64572070	0x8a84abc4	0x1cb03838
+	0x965fd76a	0x540aafc9	0x83a91654	0x1a722e67
+	0x4bf98ce1	0x2b3c2ff9	0x972cebd4	0xf3a68395
+	0x2613e422	0xf8d031d7	0xb1c79a0f	0xfd44f65b
+	0xa7012a9b	0xd9a15a60	0xc311fc0c	0x6f52f878
+	0x3d68381d	0xd2a035d7	0xb790c50e	0x9f1e5010
+	0x41877064	0xa9d1e4ae	0xfe9abbd5	0x60c2c748
+	0x8167e5ad	0x022dbfb3	0x75abe483	0x51c37170
+	0x09b8590d	0xc1bb323d	0x2c7336b1	0xd4d0d49b
+	0xc7f6152b	0x7919d596	0x1e1ff62e	0xc49604a0
+	0x33857369	0xeaa3f382	0x98b8cd86	0x176e1bf3
+	0x1a68867b	0x6af0a11c	0x69a82b25	0x48c72525
+	0xa00aae2d	0xb09f67f4	0x1a99f83d	0x7266cca3
+	0x8d03a7da	0x2e1d7c49	0x01ac68ae	0x93188770
+	0x0609e769	0x982ed28d	0xe40999e0	0x8932ebab
+	0x5637ad5a	0x2725e8ad	0x56d7caaf	0xc351faa2
+	0x09dbd737	0x0d2f3bf0	0x0623330d	0xdd547489
+	0xcca7e722	0xa9096d13	0x95b17818	0xc092cb81
+	0x72c6eefc	0x1811c37e	0x78161497	0x8be0c4c6
+	0xd63aeb19	0x91ab68df	0x8f2e5e4d	0xf4c74566
+	0x7677a553	0x19698ac3	0xedca0620	0x77f32470
+	0x031e011b	0x751f6696	0xb277d06e	0x3eae2742
+	0x133e621a	0x38fa3172	0x9398cc1c	0xf42a507b
+	0x4547d933	0x63a91eb0	0xf5bcf6a4	0x926ba056
+	0x0adf5bce	0x140f53e4	0x7ff6bb5c	0x87dd79ba
+	0xbba240ac	0x694f743d	0x709cdb20	0x5b4d4401
+	0xc9693610	0x55f9f268	0x1142bc3f	0xf8fe3689
+	0x04a93c4c	0x33dedc46	0xdc73c725	0x2f5ba264
+	0x5b7a6a69	0x024b64f5	0x6e8bfa12	0x62bf2aa7
+	0x520f5a07	0x3c7c4292	0xb7ad2613	0x1f78fc87
+	0xd5284e4e	0x2c730f33	0x8861e947	0x8bacef7d
+	0xbafa2608	0x14ed0b5b	0x3b9bfb02	0x24ced271
+	0x002b2941	0x22d4431c	0x855f4248	0x5ec46e29
+	0x6f1f42fb	0x5dd24fe0	0x290961f6	0xf392dbaf
+	0xa1a8d9c2	0x61e18f4e	0xfda59a70	0x5498daa5
+	0x5ae7ea6f	0xf058c635	0x6817ebee	0x8e30dc8b
+	0x7c8d79be	0x5fb15b9b	0xeed64741	0xe2642a94
+	0x680d7e6e	0x3cbad7aa	0x808c415f	0xe9323aa2
+	0xaadf5b25	0xf60abf13	0xd5c47967	0xc248d0b3
+	0x0f232cbd	0x84092449	0x5744384b	0x5e153ded
+	0x8bb19817	0x34430271	0x917d2315	0x1fc790c7
+	0xc21b5db6	0xec578b1f	0x903a286e	0xca0c59bc
+	0x03e95c7a	0x8c659e99	0x7b09da0a	0xd61e7517
+	0x90b1c519	0x8deac92c	0xf99c7bec	0xb6257d92
+	0x3d61c16e	0xebd58be0	0xb470e655	0xa44bbf4f
+	0xfebe5313	0x4662110a	0x5d42ccd9	0x140845ec
+	0xc80329a9	0x915ca966	0x71e33828	0xe46c870a
+	0x7da9a490	0x255544da	0xa20fb8df	0xf94062b3
+	0xb2df5870	0xebf31e88	0x6e723e2f	0xe6ba9cf1
+	0x7e7084c2	0x1782ac71	0x0a0b0127	0xe9234e38
+	0x881356d6	0xb27a54b6	0x5594730e	0x9a14bd8f
+	0x6dba7da9	0x1069e285	0x02a52798	0x61ea7d86
+	0x665b2572	0x29d41eb5	0x1d211169	0x1218b345
+	0xbfbd264c	0x5b8b0625	0xbbfdcf39	0x6768dfce
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+	0x8e943872	0x809b2c79	0x108511da	0x08b4f54d
+	0x95f52442	0x26fe296f	0xf7e037c0	0xa1aecdd3
+	0x89774a91	0xde67c55f	0x1f9816dc	0x1469a4c2
+	0x28240be2	0x5fd0ad14	0x0949db3a	0x451b94d3
+	0x637e6d49	0x8a4771c8	0xf65104b7	0xc3058c40
+	0x592fe4d0	0xe26129f0	0xe66e6ce9	0x26ab39b8
+	0x308da532	0x205afe77	0x6dc78664	0x84d4890f
+	0x9d49fcb0	0xcac8f2ed	0xe713d798	0xfed7c75b
+	0xe441a0d4	0xdf60df37	0xc2eed2f5	0x2d68b20e
+	0x7827c89a	0x9d4cb9f2	0xb8912cce	0x07516335
+	0x976ffbb6	0x5cd0de48	0xed716f54	0x6f3c9f7f
+	0x34cf42d1	0xc1027cbb	0xde67c065	0xe0a229af
+	0xfc8bd2e8	0xd62ca176	0x8bfb76b2	0x54a1388f
+	0xe0650bb6	0x6d60682b	0xe16cf130	0xbd7c3ca2
+	0xea642814	0xa25f4d44	0x27013786	0x7316aa38
+	0x571511c8	0xf1b6b789	0xb7bfe72b	0x8fd2652c
+	0xbfc7771a	0x51a2e551	0x3bd738c2	0x2698b495
+	0xec69a196	0xd5ecb5c4	0x9bd3224c	0x6d9ab4cf
+	0x326c9942	0x4d711191	0xde9be50a	0xa980ca0b
+	0xe8e59dd0	0x4439e4ae	0x35de914d	0xee499a84
+	0xd1ca0c9d	0xfe6ee96d	0x5b1f4fd0	0xabf0621a
+	0x0c8220c7	0xcb6dbb1e	0xa5116036	0xe858d3c3
+	0x728e3a56	0x3b33e818	0xbe2643c1	0x497bbcc7
+	0xeb369828	0x9a4a01be	0x8c7e72a6	0xaf052f25
+	0x8d3ca85b	0x4703e55e	0x45647d4c	0x86d1e3e8
+	0x40ab59f9	0x3259b195	0xf979a147	0xb8961870
+	0x88b024f9	0x366e26bc	0xd6811525	0x252910c2
+	0x4223a20e	0x7fc971a3	0x4a639bf3	0xb6550c3b
+	0xfe05e552	0xbdc98897	0x509923ff	0xf51a5abc
+	0xc6cc0891	0x61cdac05	0x03a68664	0x1b80cc76
+	0xe18d8ee1	0x798bb4d2	0xd7769bf9	0x9ab4c02d
+	0x7484774b	0xa9ee2c8b	0x87d34c85	0x15697682
+	0x9f6a4a55	0x9d7a731c	0x10014d6a	0xb9798070
+	0xd42f79cb	0x89db59b3	0xd5b0a0b6	0xf60864a5
+	0x2d6fb084	0x1cb607b2	0x48232701	0x9310cbc6
+	0x5bc81c98	0x6b25016c	0x2014b99d	0x0836e60b
+	0x0addbc4c	0x3b8bac7c	0x8d95ac77	0x1d56c3c7
+	0x58333104	0x3d6eb719	0x676eb951	0xd5c2d1a3
+	0x239dae86	0x92181ab8	0xbdde9741	0x7995d452
+	0xe0020661	0x2f80c8b7	0xeedcd4fc	0xe4bde175
+	0xb98fdf78	0x84b9228f	0x78ecb4f3	0xe99e5d46
+	0xa33b9b96	0xe2cbc71c	0xc19e2146	0xdc0ee758
+	0x2d8f8767	0x2036685b	0x149df155	0x2e7ab376
+	0xb13b4266	0xf5c8a3b0	0x02ca1e19	0x1badd81b
+	0xb9c1832a	0x73b31f75	0x69979b55	0x567070a2
+	0x2edeb3dc	0x26b55921	0x461df49f	0xc1aba883
+	0x25d6faec	0x5260e9bf	0xa8ccdd4c	0x04291961
+	0xfaf7a1b8	0xbc2d36e3	0xd6c86385	0x2757fbb9
+	0x62c7107c	0x87dac461	0x0c006454	0x0e971e49
+	0x4749afca	0x7f1fb389	0xdc0b69d3	0xc69fab09
+	0x12c372c9	0x78480a51	0x8ab03a94	0xb37022ca
+	0x1d00e893	0x0989de45	0x8c819503	0x8e0e1c06
+	0x11cfef86	0x3c2386a6	0x66c0e6c8	0x1befa478
+	0xd2e7a4a7	0x9a8b5917	0x2cfa1816	0xaf7e6c7a
+	0xd6c9f0ff	0x1aada3e0	0xbe36a471	0x5a91f3c7
+	0x6c61ea95	0x5246ef7c	0x20bc86c4	0xcfd87abd
+	0xdc61f595	0x8310a684	0x0477e35c	0xe59e776f
+	0xfa403863	0xdaf7bcb1	0xd6084825	0xb90bb047
+	0xeb9ff684	0x7223fbca	0x6b4af987	0x6b2553f8
+	0xdaabc6d2	0x82e2ebc3	0xa7c1c054	0x667eb0a7
+	0x53a0c7d4	0x3fcba743	0x38170187	0x2a2e5830
+	0xee134608	0xcd6e0112	0xac0831f9	0x9537d532
+	0x1e176b9c	0xe3fcb69f	0x17a2eee9	0xa9e6467f
+	0xbf6b0246	0x6a08c0fb	0x7fb943b6	0xb8f67c0e
+	0x2b3b4ffc	0xb155d20c	0x4eb5de53	0xf078715b
+	>;
diff --git a/arch/x86/dts/minnowmax.dts b/arch/x86/dts/minnowmax.dts
new file mode 100644
index 0000000..7e15c26
--- /dev/null
+++ b/arch/x86/dts/minnowmax.dts
@@ -0,0 +1,45 @@
+/*
+ * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/dts-v1/;
+
+/include/ "skeleton.dtsi"
+/include/ "serial.dtsi"
+
+/ {
+	model = "Intel Minnowboard Max";
+	compatible = "intel,minnowmax", "intel,baytrail";
+
+	aliases {
+		serial0 = &serial;
+	};
+
+	config {
+		silent_console = <0>;
+	};
+
+	chosen {
+		stdout-path = "/serial";
+	};
+
+	spi {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "intel,ich7";
+		spi-flash at 0 {
+			reg = <0>;
+			compatible = "sst,25vf016b", "spi-flash";
+			memory-map = <0xff800000 0x00800000>;
+		};
+	};
+
+	microcode {
+		update at 0 {
+#include "microcode/m0130673322.dtsi"
+		};
+	};
+
+};
diff --git a/arch/x86/dts/serial.dtsi b/arch/x86/dts/serial.dtsi
index 9b097f4..6865eed 100644
--- a/arch/x86/dts/serial.dtsi
+++ b/arch/x86/dts/serial.dtsi
@@ -1,5 +1,5 @@
 / {
-	serial {
+	serial: serial {
 		compatible = "x86-uart";
 		reg = <0x3f8 8>;
 		reg-shift = <0>;
diff --git a/arch/x86/include/asm/arch-baytrail/fsp/azalia.h b/arch/x86/include/asm/arch-baytrail/fsp/azalia.h
new file mode 100644
index 0000000..d96a20f
--- /dev/null
+++ b/arch/x86/include/asm/arch-baytrail/fsp/azalia.h
@@ -0,0 +1,39 @@
+/*
+ * Copyright (C) 2013, Intel Corporation
+ * Copyright (C) 2015 Google, Inc
+ *
+ * SPDX-License-Identifier:	Intel
+ */
+
+#ifndef _FSP_AZALIA_H_
+#define _FSP_AZALIA_H_
+
+struct __packed pch_azalia_verb_table_header {
+	uint32_t vendor_device_id;
+	uint16_t sub_system_id;
+	uint8_t revision_id;		/* 0xff applies to all steppings */
+	uint8_t front_panel_support;
+	uint16_t number_of_rear_jacks;
+	uint16_t number_of_front_jacks;
+};
+
+struct __packed pch_azalia_verb_table {
+	struct pch_azalia_verb_table_header verb_table_header;
+	const uint32_t *verb_table_data;
+};
+
+struct __packed pch_azalia_config {
+	uint8_t pme_enable:1;
+	uint8_t docking_supported:1;
+	uint8_t docking_attached:1;
+	uint8_t hdmi_codec_enable:1;
+	uint8_t azalia_v_ci_enable:1;
+	uint8_t rsvdbits:3;
+	/* number of verb tables provided by platform */
+	uint8_t azalia_verb_table_num;
+	const struct pch_azalia_verb_table *azalia_verb_table;
+	/* delay timer after azalia reset */
+	uint16_t reset_wait_timer_us;
+};
+
+#endif
diff --git a/arch/x86/include/asm/arch-baytrail/fsp/fsp_vpd.h b/arch/x86/include/asm/arch-baytrail/fsp/fsp_vpd.h
new file mode 100644
index 0000000..82862f6
--- /dev/null
+++ b/arch/x86/include/asm/arch-baytrail/fsp/fsp_vpd.h
@@ -0,0 +1,95 @@
+/*
+ * Copyright (C) 2013, Intel Corporation
+ * Copyright (C) 2015 Google, Inc
+ *
+ * SPDX-License-Identifier:	Intel
+ */
+
+#ifndef __FSP_VPD_H
+#define __FSP_VPD_H
+
+struct memory_down_data {
+	uint8_t enable_memory_down;
+	uint8_t dram_speed;
+	uint8_t dram_type;
+	uint8_t dimm_0_enable;
+	uint8_t dimm_1_enable;
+	uint8_t dimm_width;
+	uint8_t dimm_density;
+	uint8_t dimm_bus_width;
+	uint8_t dimm_sides;			/* Ranks Per dimm_ */
+	uint8_t dimm_tcl;			/* tCL */
+	/* tRP and tRCD in DRAM clk - 5:12.5ns, 6:15ns, etc. */
+	uint8_t dimm_trpt_rcd;
+	uint8_t dimm_twr;			/* tWR in DRAM clk  */
+	uint8_t dimm_twtr;			/* tWTR in DRAM clk */
+	uint8_t dimm_trrd;			/* tRRD in DRAM clk */
+	uint8_t dimm_trtp;			/* tRTP in DRAM clk */
+	uint8_t dimm_tfaw;			/* tFAW in DRAM clk */
+};
+
+struct __packed upd_region {
+	uint64_t signature;			/* Offset 0x0000 */
+	uint8_t reserved0[24];			/* Offset 0x0008 */
+	uint16_t mrc_init_tseg_size;		/* Offset 0x0020 */
+	uint16_t mrc_init_mmio_size;		/* Offset 0x0022 */
+	uint8_t mrc_init_spd_addr1;		/* Offset 0x0024 */
+	uint8_t mrc_init_spd_addr2;		/* Offset 0x0025 */
+	uint8_t emmc_boot_mode;			/* Offset 0x0026 */
+	uint8_t enable_sdio;			/* Offset 0x0027 */
+	uint8_t enable_sdcard;			/* Offset 0x0028 */
+	uint8_t enable_hsuart0;			/* Offset 0x0029 */
+	uint8_t enable_hsuart1;			/* Offset 0x002a */
+	uint8_t enable_spi;			/* Offset 0x002b */
+	uint8_t reserved1;			/* Offset 0x002c */
+	uint8_t enable_sata;			/* Offset 0x002d */
+	uint8_t sata_mode;			/* Offset 0x002e */
+	uint8_t enable_azalia;			/* Offset 0x002f */
+	uint32_t azalia_config_ptr;		/* Offset 0x0030 */
+	uint8_t enable_xhci;			/* Offset 0x0034 */
+	uint8_t enable_lpe;			/* Offset 0x0035 */
+	uint8_t lpss_sio_enable_pci_mode;	/* Offset 0x0036 */
+	uint8_t enable_dma0;			/* Offset 0x0037 */
+	uint8_t enable_dma1;			/* Offset 0x0038 */
+	uint8_t enable_i2_c0;			/* Offset 0x0039 */
+	uint8_t enable_i2_c1;			/* Offset 0x003a */
+	uint8_t enable_i2_c2;			/* Offset 0x003b */
+	uint8_t enable_i2_c3;			/* Offset 0x003c */
+	uint8_t enable_i2_c4;			/* Offset 0x003d */
+	uint8_t enable_i2_c5;			/* Offset 0x003e */
+	uint8_t enable_i2_c6;			/* Offset 0x003f */
+	uint8_t enable_pwm0;			/* Offset 0x0040 */
+	uint8_t enable_pwm1;			/* Offset 0x0041 */
+	uint8_t enable_hsi;			/* Offset 0x0042 */
+	uint8_t igd_dvmt50_pre_alloc;		/* Offset 0x0043 */
+	uint8_t aperture_size;			/* Offset 0x0044 */
+	uint8_t gtt_size;			/* Offset 0x0045 */
+	uint32_t serial_debug_port_address;	/* Offset 0x0046 */
+	uint8_t serial_debug_port_type;		/* Offset 0x004a */
+	uint8_t mrc_debug_msg;			/* Offset 0x004b */
+	uint8_t isp_enable;			/* Offset 0x004c */
+	uint8_t scc_enable_pci_mode;		/* Offset 0x004d */
+	uint8_t igd_render_standby;		/* Offset 0x004e */
+	uint8_t txe_uma_enable;			/* Offset 0x004f */
+	uint8_t os_selection;			/* Offset 0x0050 */
+	uint8_t emmc45_ddr50_enabled;		/* Offset 0x0051 */
+	uint8_t emmc45_hs200_enabled;		/* Offset 0x0052 */
+	uint8_t emmc45_retune_timer_value;	/* Offset 0x0053 */
+	uint8_t unused_upd_space1[156];		/* Offset 0x0054 */
+	struct memory_down_data memory_params;	/* Offset 0x00f0 */
+	uint16_t terminator;			/* Offset 0x0100 */
+};
+
+#define VPD_IMAGE_ID		0x3157454956594C56	/* 'VLYVIEW1' */
+#define VPD_IMAGE_REV		0x00000303
+
+struct __packed vpd_region {
+	uint64_t sign;				/* Offset 0x0000 */
+	uint32_t img_rev;			/* Offset 0x0008 */
+	uint32_t upd_offset;			/* Offset 0x000c */
+	uint8_t unused[16];			/* Offset 0x0010 */
+	uint32_t fsp_res_memlen;		/* Offset 0x0020 */
+	uint8_t platform_type;			/* Offset 0x0024 */
+	uint8_t enable_secure_boot;		/* Offset 0x0025 */
+};
+#endif
diff --git a/arch/x86/include/asm/arch-baytrail/gpio.h b/arch/x86/include/asm/arch-baytrail/gpio.h
new file mode 100644
index 0000000..ab4e059
--- /dev/null
+++ b/arch/x86/include/asm/arch-baytrail/gpio.h
@@ -0,0 +1,13 @@
+/*
+ * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _X86_ARCH_GPIO_H_
+#define _X86_ARCH_GPIO_H_
+
+/* Where in config space is the register that points to the GPIO registers? */
+#define PCI_CFG_GPIOBASE 0x44
+
+#endif /* _X86_ARCH_GPIO_H_ */
diff --git a/board/intel/minnowmax/Kconfig b/board/intel/minnowmax/Kconfig
new file mode 100644
index 0000000..7c2b927
--- /dev/null
+++ b/board/intel/minnowmax/Kconfig
@@ -0,0 +1,31 @@
+if TARGET_MINNOWMAX
+
+config SYS_BOARD
+	default "minnowmax"
+
+config SYS_VENDOR
+	default "intel"
+
+config SYS_SOC
+	default "baytrail"
+
+config SYS_CONFIG_NAME
+	default "minnowmax"
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+	def_bool y
+	select X86_RESET_VECTOR
+	select INTEL_BAYTRAIL
+	select BOARD_ROMSIZE_KB_8192
+
+config MMCONF_BASE_ADDRESS
+	default 0xe0000000
+
+config DEBUG_UART_BASE
+	default 0x3f8
+
+config DEBUG_UART_CLOCK
+	default 1843200
+#	default 115200
+
+endif
diff --git a/board/intel/minnowmax/MAINTAINERS b/board/intel/minnowmax/MAINTAINERS
new file mode 100644
index 0000000..d655761
--- /dev/null
+++ b/board/intel/minnowmax/MAINTAINERS
@@ -0,0 +1,6 @@
+CircuitCo Minnowboard Max
+M:	Simon Glass <sjg@chromium.org>
+S:	Maintained
+F:	board/intel/minnowmax
+F:	include/configs/minnowmax.h
+F:	configs/minnowmax_defconfig
diff --git a/board/intel/minnowmax/Makefile b/board/intel/minnowmax/Makefile
new file mode 100644
index 0000000..1a61432
--- /dev/null
+++ b/board/intel/minnowmax/Makefile
@@ -0,0 +1,7 @@
+#
+# Copyright (C) 2015, Google, Inc
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y	+= minnowmax.o start.o
diff --git a/board/intel/minnowmax/minnowmax.c b/board/intel/minnowmax/minnowmax.c
new file mode 100644
index 0000000..6e82b16
--- /dev/null
+++ b/board/intel/minnowmax/minnowmax.c
@@ -0,0 +1,32 @@
+/*
+ * Copyright (C) 2015, Google, Inc
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/ibmpc.h>
+#include <asm/pnp_def.h>
+#include <netdev.h>
+#include <smsc_lpc47m.h>
+
+#define SERIAL_DEV PNP_DEV(0x2e, 4)
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_early_init_f(void)
+{
+	lpc47m_enable_serial(SERIAL_DEV, UART0_BASE);
+
+	return 0;
+}
+
+void setup_pch_gpios(u16 gpiobase, const struct pch_gpio_map *gpio)
+{
+	return;
+}
+
+int board_eth_init(bd_t *bis)
+{
+	return pci_eth_init(bis);
+}
diff --git a/board/intel/minnowmax/start.S b/board/intel/minnowmax/start.S
new file mode 100644
index 0000000..2c941a4
--- /dev/null
+++ b/board/intel/minnowmax/start.S
@@ -0,0 +1,9 @@
+/*
+ * Copyright (C) 2015, Google, Inc
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+.globl early_board_init
+early_board_init:
+	jmp	early_board_init_ret
diff --git a/configs/minnowmax_defconfig b/configs/minnowmax_defconfig
new file mode 100644
index 0000000..7bc9085
--- /dev/null
+++ b/configs/minnowmax_defconfig
@@ -0,0 +1,13 @@
+CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0xfff00000"
+CONFIG_X86=y
+CONFIG_TARGET_MINNOWMAX=y
+CONFIG_OF_CONTROL=y
+CONFIG_OF_SEPARATE=y
+CONFIG_DEFAULT_DEVICE_TREE="minnowmax"
+CONFIG_VIDEO_X86=y
+CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
+CONFIG_FRAMEBUFFER_VESA_MODE_11A=y
+CONFIG_DEBUG_UART_NS16550=y
+CONFIG_DEBUG_UART=y
+CONFIG_MMCONF_BASE_ADDRESS=0xe0000000
+CONFIG_HAVE_INTEL_ME=y
diff --git a/doc/README.x86 b/doc/README.x86
index 0e4628a..cd9a926 100644
--- a/doc/README.x86
+++ b/doc/README.x86
@@ -18,11 +18,11 @@ U-Boot supports running as a coreboot [1] payload on x86. So far only Link
 on other x86 boards since coreboot deals with most of the low-level details.
 
 U-Boot also supports booting directly from x86 reset vector without coreboot,
-aka raw support or bare support. Currently Link and Intel Crown Bay board
-support running U-Boot 'bare metal'.
+aka raw support or bare support. Currently Link, Intel Crown Bay and Intel
+Minnowboard Max support running U-Boot 'bare metal'.
 
-As for loading OS, U-Boot supports directly booting a 32-bit or 64-bit Linux
-kernel as part of a FIT image. It also supports a compressed zImage.
+As for loading an OS, U-Boot supports directly booting a 32-bit or 64-bit
+Linux kernel as part of a FIT image. It also supports a compressed zImage.
 
 Build Instructions
 ------------------
@@ -47,11 +47,11 @@ Change the 'Board configuration file' and 'Board Device Tree Source (dts) file'
 to point to a new board. You can also change the Cache-As-RAM (CAR) related
 settings here if the default values do not fit your new board.
 
-Building ROM version of U-Boot (hereafter referred to as u-boot.rom) is a
+Building a ROM version of U-Boot (hereafter referred to as u-boot.rom) is a
 little bit tricky, as generally it requires several binary blobs which are not
 shipped in the U-Boot source tree. Due to this reason, the u-boot.rom build is
 not turned on by default in the U-Boot source tree. Firstly, you need turn it
-on by enabling the ROM board:
+on by enabling the ROM build
 
 $ export BUILD_ROM=y
 
@@ -110,6 +110,33 @@ Now you can build U-Boot and obtain u-boot.rom
 $ make crownbay_defconfig
 $ make all
 
+
+Intel Minnowboard Max instructions:
+
+This uses as FSP as with Crown Bay, except it is for the Atom E3800 series.
+Download this and get the .fd file (BAYTRAIL_FSP_GOLD_003_16-SEP-2014.fd at
+the time of writing). Put it in the board directory:
+board/intel/minnowmax/fsp.bin
+
+Obtain the VGA RAM (Vga.dat at the time of writing) and put it into the same
+directory: board/intel/minnowmax/vga.bin
+
+You still need two more binary blobs. These come from the sample SPI image
+provided in the FSP (SPI.bin at the time of writing).
+
+Use ifdtool in the U-Boot tools directory to extract the images from that
+file, for example:
+
+   $ ./tools/ifdtool -x BayleyBay/SPI.bin
+   $ cp flashregion_2_intel_me.bin board/intel/minnowmax/me.bin
+   $ cp flashregion_0_flashdescriptor.bin board/intel/minnowmax/descriptor.bin
+
+Now you can build U-Boot and obtain u-boot.rom
+
+$ make minnowmax_defconfig
+$ make all
+
+
 Test with coreboot
 ------------------
 For testing U-Boot as the coreboot payload, there are things that need be paid
@@ -130,6 +157,16 @@ symbol address of _start (in arch/x86/cpu/start.S).
 If you want to use ELF as the coreboot payload, change U-Boot configuration to
 use CONFIG_OF_EMBED instead of CONFIG_OF_SEPARATE.
 
+To enable video you must enable these options in Coreboot:
+
+   - Set framebuffer graphics resolution (1280x1024 32k-color (1:5:5))
+   - Keep VESA framebuffer
+
+At present it seems that for Minnowboard Max, coreboot does not pass through
+the video information correctly (it always says the resolution is 0x0). This
+works correctly for link though.
+
+
 CPU Microcode
 -------------
 Modern CPUs usually requires a special bit stream called microcode [5] to be
diff --git a/include/configs/minnowmax.h b/include/configs/minnowmax.h
new file mode 100644
index 0000000..507afb8
--- /dev/null
+++ b/include/configs/minnowmax.h
@@ -0,0 +1,69 @@
+/*
+ * Copyright (C) 2015 Google, Inc
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <configs/x86-common.h>
+
+#define CONFIG_SYS_MONITOR_LEN		(1 << 20)
+#define CONFIG_BOARD_EARLY_INIT_F
+
+#define CONFIG_NR_DRAM_BANKS		1
+
+#define CONFIG_X86_SERIAL
+#define CONFIG_SMSC_LPC47M
+
+#define CONFIG_PCI_MEM_BUS		0xd0000000
+#define CONFIG_PCI_MEM_PHYS		CONFIG_PCI_MEM_BUS
+#define CONFIG_PCI_MEM_SIZE		0x10000000
+
+#define CONFIG_PCI_PREF_BUS		0xc0000000
+#define CONFIG_PCI_PREF_PHYS		CONFIG_PCI_PREF_BUS
+#define CONFIG_PCI_PREF_SIZE		0x10000000
+
+#define CONFIG_PCI_IO_BUS		0x2000
+#define CONFIG_PCI_IO_PHYS		CONFIG_PCI_IO_BUS
+#define CONFIG_PCI_IO_SIZE		0xe000
+
+#define CONFIG_SYS_EARLY_PCI_INIT
+#define CONFIG_PCI_PNP
+#define CONFIG_RTL8169
+#define CONFIG_STD_DEVICES_SETTINGS     "stdin=usbkbd,vga,serial\0" \
+					"stdout=vga,serial\0" \
+					"stderr=vga,serial\0"
+
+#define CONFIG_SCSI_DEV_LIST            \
+	{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_VALLEYVIEW_SATA}
+#define CONFIG_SPI_FLASH_SST
+
+#define CONFIG_MMC
+#define CONFIG_SDHCI
+#define CONFIG_GENERIC_MMC
+#define CONFIG_MMC_SDMA
+#define CONFIG_CMD_MMC
+
+#undef CONFIG_USB_MAX_CONTROLLER_COUNT
+#define CONFIG_USB_MAX_CONTROLLER_COUNT		1
+
+#define CONFIG_X86_OPTION_ROM_FILE		vga.bin
+#define CONFIG_X86_OPTION_ROM_ADDR		0xfff90000
+
+#ifndef CONFIG_SYS_COREBOOT
+#define CONFIG_VIDEO_VESA
+#endif
+#define VIDEO_IO_OFFSET				0
+#define CONFIG_X86EMU_RAW_IO
+#define CONFIG_VGA_AS_SINGLE_DEVICE
+
+#define CONFIG_FIT_SIGNATURE
+#define CONFIG_RSA
+
+#endif	/* __CONFIG_H */
-- 
2.2.0.rc0.207.ga3a616c

[U-Boot] [PATCH 22/23] x86: Add some documentation on how to port U-Boot on x86

[Bin Meng]

Hi Simon,

On Tue, Jan 27, 2015 at 9:23 AM, Simon Glass <sjg@chromium.org> wrote:
> Some information has been gleaned on tools and procedures for porting
> U-Boot to different x86 platforms. Add a few notes to start things off.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> ---
>

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

A minor comment below.

>  doc/README.x86 | 63 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
>  1 file changed, 63 insertions(+)
>
> diff --git a/doc/README.x86 b/doc/README.x86
> index 809a291..0e4628a 100644
> --- a/doc/README.x86
> +++ b/doc/README.x86
> @@ -164,6 +164,69 @@ mtrr - List and set the Memory Type Range Registers (MTRR). These are used to
>          mode to use. U-Boot sets up some reasonable values but you can
>          adjust then with this command.
>
> +Development Flow
> +----------------
> +
> +These notes are for those who want to port U-Boot to a new x86 platform.
> +
> +Since x86 CPUs boot from SPI flash, a SPI flash emulator is a good investment.
> +The Dediprog em100 can be used on Linux. The em100 tool is available here:
> +
> +   http://review.coreboot.org/p/em100.git
> +
> +On Minnowboard Max the following command line can be used:
> +
> +   sudo em100 -s -p LOW -d u-boot.rom -c W25Q64DW -r
> +
> +A suitable clip for connecting over the SPI flash chip is here:
> +
> +   http://www.dediprog.com/pd/programmer-accessories/EM-TC-8
> +
> +This allows you to override the SPI flash contents for development purposes.
> +Typically you can write to the em100 in around 1200ms, considerably faster
> +than programming the real flash device each time. The only important
> +limitation of the em100 is that it only supports SPI bus speeds up to 20MHz.
> +This means that images must be set to boot with that speed (Intel-specific
> +feature).
> +

It would be better to document what this Intel-specific feature is in
order to support this SPI bus frequency.

> +If your chip/board uses an Intel Firmware Support Package (FSP) it is fairly
> +easy to fit it in. You can follow the Minnowboard Max implementation, for
> +example. Hopefully you will just need to create new files similar to those
> +in arch/x86/cpu/baytrail which provide Bay Trail support.
> +
> +If you are not using an FSP you have more freedom and more responsibility.
> +The ivybridge support works this way, although it still uses a ROM for
> +graphics and still has binary blobs containing Intel code. You should aim to
> +support all important peripherals on your platform including video and storage.
> +Use the device tree for configuration where possible.
> +
> +For the microcode you can create a suitable device tree file using the
> +microcode tool:
> +
> +  ./tools/microcode-tool -d microcode.dat create <model>
> +
> +or if you only have header files and not the full Intel microcode.dat database:
> +
> +  ./tools/microcode-tool -H BAY_TRAIL_FSP_KIT/Microcode/M0130673322.h \
> +       -H BAY_TRAIL_FSP_KIT/Microcode/M0130679901.h \
> +       create all
> +
> +These are written to arch/x86/dts/microcode/ by default.
> +
> +Note that it is possible to just add the micrcode for your CPU if you know its
> +model. U-Boot prints this information when it starts
> +
> +   CPU: x86_64, vendor Intel, device 30673h
> +
> +so here we can use the M0130673322 file.
> +
> +If you platform can display POST codes on two little 7-segment displays on
> +the board, then you can use post_code() calls from C or assembler to monitor
> +boot progress. This can be good for debugging.
> +
> +If not, you can try to get serial working as early as possible. The early
> +debug serial port may be useful here. See setup_early_uart() for an example.
> +
>  TODO List
>  ---------
>  - Audio
> --

Regards,
Bin

[U-Boot] [PATCH 01/23] x86: Enhance the microcode tool to support header files as input

[Bin Meng]

Hi Simon,

On Tue, Jan 27, 2015 at 9:22 AM, Simon Glass <sjg@chromium.org> wrote:
> Sometimes microcode is delivered as a header file. Allow the tool to
> support this as well as collecting multiple microcode blocks into a
> single update.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> ---

Tested-by: Bin Meng <bmeng.cn@gmail.com>

But please see my comments below.

>  tools/microcode-tool.py | 90 ++++++++++++++++++++++++++++++++++++++-----------
>  1 file changed, 70 insertions(+), 20 deletions(-)
>
> diff --git a/tools/microcode-tool.py b/tools/microcode-tool.py
> index 003716d..71c2e91 100755
> --- a/tools/microcode-tool.py
> +++ b/tools/microcode-tool.py
> @@ -76,6 +76,35 @@ def ParseFile(fname):
>          microcodes[name] = Microcode(name, data)
>      return date, license_text, microcodes
>
> +def ParseHeaderFiles(fname_list):
> +    """Parse a list of header files and return the component parts
> +
> +    Args:
> +        fname_list: List of files to parse
> +    Returns:
> +            date:         String containing date from the file's header
> +            license_text: List of text lines for the license file
> +            microcodes:   List of Microcode objects from the file
> +    """
> +    microcodes = {}
> +    license_text = []
> +    date = ''
> +    name = None
> +    for fname in fname_list:
> +        name = os.path.basename(fname).lower()
> +        name = os.path.splitext(name)[0]
> +        data = []
> +        with open(fname) as fd:
> +            for line in fd:
> +                line = line.rstrip()
> +
> +                # Omit anything after the last comma
> +                words = line.split(',')[:-1]
> +                data += [word + ',' for word in words]
> +        microcodes[name] = Microcode(name, data)
> +    return date, license_text, microcodes
> +
> +
>  def List(date, microcodes, model):
>      """List the available microcode chunks
>
> @@ -129,13 +158,13 @@ def FindMicrocode(microcodes, model):
>              break
>      return found, tried
>
> -def CreateFile(date, license_text, mcode, outfile):
> +def CreateFile(date, license_text, mcodes, outfile):
>      """Create a microcode file in U-Boot's .dtsi format
>
>      Args:
>          date:       String containing date of original microcode file
>          license:    List of text lines for the license file
> -        mcode:      Microcode object to write
> +        mcodes:      Microcode objects to write (normally only 1)
>          outfile:    Filename to write to ('-' for stdout)
>      """
>      out = '''/*%s
> @@ -159,15 +188,22 @@ intel,processor-flags = <%#x>;
>  data = <%s
>  \t>;'''
>      words = ''
> -    for i in range(len(mcode.words)):
> -        if not (i & 3):
> -            words += '\n'
> -        val = mcode.words[i]
> -        # Change each word so it will be little-endian in the FDT
> -        # This data is needed before RAM is available on some platforms so we
> -        # cannot do an endianness swap on boot.
> -        val = struct.unpack("<I", struct.pack(">I", val))[0]
> -        words += '\t%#010x' % val
> +    add_comments = len(mcodes) > 1
> +    for mcode in mcodes:
> +        if add_comments:
> +            words += '\n/* %s */' % mcode.name
> +        for i in range(len(mcode.words)):
> +            if not (i & 3):
> +                words += '\n'
> +            val = mcode.words[i]
> +            # Change each word so it will be little-endian in the FDT
> +            # This data is needed before RAM is available on some platforms so
> +            # we cannot do an endianness swap on boot.
> +            val = struct.unpack("<I", struct.pack(">I", val))[0]
> +            words += '\t%#010x' % val
> +
> +    # Use the first microcode for the headers
> +    mcode = mcodes[0]
>
>      # Take care to avoid adding a space before a tab
>      text = ''
> @@ -187,8 +223,8 @@ data = <%s
>                  print >> sys.stderr, "Creating directory '%s'" % MICROCODE_DIR
>                  os.makedirs(MICROCODE_DIR)
>              outfile = os.path.join(MICROCODE_DIR, mcode.name + '.dtsi')
> -            print >> sys.stderr, "Writing microcode for '%s' to '%s'" % (
> -                     mcode.name, outfile)
> +        print >> sys.stderr, "Writing microcode for '%s' to '%s'" % (
> +                ', '.join([mcode.name for mcode in mcodes]), outfile)
>          with open(outfile, 'w') as fd:
>              print >> fd, out % tuple(args)
>
> @@ -198,8 +234,12 @@ def MicrocodeTool():
>      parser = OptionParser()
>      parser.add_option('-d', '--mcfile', type='string', action='store',
>                      help='Name of microcode.dat file')
> +    parser.add_option('-H', '--headerfile', type='string', action='append',
> +                    help='Name of .h file containing microcode')
>      parser.add_option('-m', '--model', type='string', action='store',
> -                    help='Model name to extract')
> +                    help="Model name to extract ('all' for all)")
> +    parser.add_option('-M', '--multiple', type='string', action='store',
> +                    help="Allow output of multiple models")
>      parser.add_option('-o', '--outfile', type='string', action='store',
>                      help='Filename to use for output (- for stdout), default is'
>                      ' %s/<name>.dtsi' % MICROCODE_DIR)
> @@ -224,9 +264,14 @@ def MicrocodeTool():
>      if cmd not in commands:
>          parser.error("Unknown command '%s'" % cmd)
>
> -    if not options.mcfile:
> -        parser.error('You must specify a microcode file')
> -    date, license_text, microcodes = ParseFile(options.mcfile)
> +    if (not not options.mcfile) != (not not options.mcfile):
> +        parser.error("You must specify either header files or a microcode file, not both")
> +    if options.headerfile:
> +        date, license_text, microcodes = ParseHeaderFiles(options.headerfile)
> +    elif options.mcfile:
> +        date, license_text, microcodes = ParseFile(options.mcfile)
> +    else:
> +        parser.error('You must specify a microcode file (or header files)')
>
>      if cmd == 'list':
>          List(date, microcodes, options.model)
> @@ -236,16 +281,21 @@ def MicrocodeTool():
>          if not options.model:
>              parser.error('You must specify a model to create')
>          model = options.model.lower()
> -        mcode_list, tried = FindMicrocode(microcodes, model)
> +        if options.model == 'all':
> +            options.multiple = True
> +            mcode_list = microcodes.values()
> +            tried = []
> +        else:
> +            mcode_list, tried = FindMicrocode(microcodes, model)
>          if not mcode_list:
>              parser.error("Unknown model '%s' (%s) - try 'list' to list" %
>                          (model, ', '.join(tried)))
> -        if len(mcode_list) > 1:
> +        if not options.multiple and len(mcode_list) > 1:
>              parser.error("Ambiguous model '%s' (%s) matched %s - try 'list' "
>                          "to list or specify a particular file" %
>                          (model, ', '.join(tried),
>                          ', '.join([m.name for m in mcode_list])))
> -        CreateFile(date, license_text, mcode_list[0], options.outfile)
> +        CreateFile(date, license_text, mcode_list, options.outfile)
>      else:
>          parser.error("Unknown command '%s'" % cmd)
>
> --

My testing results show that, compared to '-d microcode.dat' approach,
generated microcode.dtsi using '-H' does not have license header and
date set. Is this intentional?

Regards,
Bin

[U-Boot] [PATCH 03/23] x86: pci: Add PCI IDs for Minnowboard Max

[Bin Meng]

On Tue, Jan 27, 2015 at 9:23 AM, Simon Glass <sjg@chromium.org> wrote:
> This board includes a few IDs we have not seen before.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> ---
>
>  include/pci_ids.h | 5 +++++
>  1 file changed, 5 insertions(+)
>
> diff --git a/include/pci_ids.h b/include/pci_ids.h
> index 26f4748..1012abe 100644
> --- a/include/pci_ids.h
> +++ b/include/pci_ids.h
> @@ -1346,6 +1346,7 @@
>
>  #define PCI_VENDOR_ID_REALTEK          0x10ec
>  #define PCI_DEVICE_ID_REALTEK_8139     0x8139
> +#define PCI_DEVICE_ID_REALTEK_8168     0x8168
>
>  #define PCI_VENDOR_ID_XILINX           0x10ee
>  #define PCI_DEVICE_ID_RME_DIGI96       0x3fc0
> @@ -2594,6 +2595,10 @@
>  #define PCI_DEVICE_ID_INTEL_I960       0x0960
>  #define PCI_DEVICE_ID_INTEL_I960RM     0x0962
>  #define PCI_DEVICE_ID_INTEL_CENTERTON_ILB      0x0c60
> +#define PCI_DEVICE_ID_INTEL_VALLEYVIEW_SDIO    0x0f15
> +#define PCI_DEVICE_ID_INTEL_VALLEYVIEW_SDCARD  0x0f16
> +#define PCI_DEVICE_ID_INTEL_VALLEYVIEW_LPC     0x0f1c
> +#define PCI_DEVICE_ID_INTEL_VALLEYVIEW_SATA    0x0f23
>  #define PCI_DEVICE_ID_INTEL_82541ER    0x1078
>  #define PCI_DEVICE_ID_INTEL_82541GI_LF 0x107c
>  #define PCI_DEVICE_ID_INTEL_82542      0x1000
> --

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

[U-Boot] [PATCH 04/23] x86: video: Enable video for Minnowboard Max

[Bin Meng]

On Tue, Jan 27, 2015 at 9:23 AM, Simon Glass <sjg@chromium.org> wrote:
> This board uses a new PCI ID.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> ---
>
>  drivers/video/vesa_fb.c | 1 +
>  1 file changed, 1 insertion(+)
>
> diff --git a/drivers/video/vesa_fb.c b/drivers/video/vesa_fb.c
> index 3dacafd..3a0fea2 100644
> --- a/drivers/video/vesa_fb.c
> +++ b/drivers/video/vesa_fb.c
> @@ -23,6 +23,7 @@ struct pci_device_id vesa_video_ids[] = {
>         { .vendor = 0x1002, .device = 0x5159 },
>         { .vendor = 0x1002, .device = 0x4752 },
>         { .vendor = 0x1002, .device = 0x5452 },
> +       { .vendor = 0x8086, .device = 0x0f31 },
>         {},
>  };
>
> --

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

[U-Boot] [PATCH 02/23] pci: Add a function to find a device by class

[Bin Meng]

Hi Simon,

On Tue, Jan 27, 2015 at 9:23 AM, Simon Glass <sjg@chromium.org> wrote:
> There is an existing function prototype in the header file but it is not
> implemented. Implement something similar.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> ---
>
>  drivers/pci/pci.c | 38 ++++++++++++++++++++++++++++++++++++++
>  include/pci.h     |  3 +--
>  2 files changed, 39 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
> index 950a247..215a092 100644
> --- a/drivers/pci/pci.c
> +++ b/drivers/pci/pci.c
> @@ -15,6 +15,7 @@
>  #include <common.h>
>
>  #include <command.h>
> +#include <errno.h>
>  #include <asm/processor.h>
>  #include <asm/io.h>
>  #include <pci.h>
> @@ -236,6 +237,43 @@ pci_dev_t pci_find_devices(struct pci_device_id *ids, int index)
>         return -1;
>  }
>
> +pci_dev_t pci_find_class(uint find_class, int index)
> +{
> +       int bus;
> +       int devnum;
> +       pci_dev_t bdf;
> +       uint32_t class;
> +
> +       for (bus = 0; bus <= pci_last_busno(); bus++) {
> +               for (devnum = 0; devnum < PCI_MAX_PCI_DEVICES-1; devnum++) {

space after PCI_MAX_PCI_DEVICES and before 1?

> +                       pci_read_config_dword(PCI_BDF(bus, devnum, 0),
> +                                             PCI_CLASS_REVISION, &class);
> +                       if (class >> 16 == 0xffff)
> +                               continue;
> +
> +                       for (bdf = PCI_BDF(bus, devnum, 0);
> +                                       bdf <= PCI_BDF(bus, devnum,
> +                                               PCI_MAX_PCI_FUNCTIONS - 1);
> +                                       bdf += PCI_BDF(0, 0, 1)) {
> +                               pci_read_config_dword(bdf, PCI_CLASS_REVISION,
> +                                                     &class);
> +                               class >>= 8;
> +
> +                               if (class != find_class)
> +                                       continue;
> +                               if (index) {
> +                                       index--;
> +                                       continue;

It is worth to have a comment block to explain the 'index' logic here.

> +                               }
> +                               /* Return index'th controller. */
> +                               return bdf;
> +                       }
> +               }
> +       }
> +
> +       return -ENODEV;
> +}
> +
>  pci_dev_t pci_find_device(unsigned int vendor, unsigned int device, int index)
>  {
>         struct pci_device_id ids[2] = { {}, {0, 0} };
> diff --git a/include/pci.h b/include/pci.h
> index 4fbb8f6..004a048 100644
> --- a/include/pci.h
> +++ b/include/pci.h
> @@ -644,8 +644,7 @@ extern int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev);
>
>  extern pci_dev_t pci_find_device (unsigned int vendor, unsigned int device, int index);
>  extern pci_dev_t pci_find_devices (struct pci_device_id *ids, int index);
> -extern pci_dev_t pci_find_class(int wanted_class, int wanted_sub_code,
> -                               int wanted_prog_if, int index);
> +pci_dev_t pci_find_class(unsigned int find_class, int index);
>
>  extern int pci_hose_config_device(struct pci_controller *hose,
>                                   pci_dev_t dev,
> --

Regards,
Bin

[U-Boot] [PATCH 05/23] usb: pci: Use pci_find_class() to find the device

[Bin Meng]

On Tue, Jan 27, 2015 at 9:23 AM, Simon Glass <sjg@chromium.org> wrote:
> Use the new utility function instead of local code.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> ---
>
>  drivers/usb/host/ehci-pci.c | 53 +--------------------------------------------
>  1 file changed, 1 insertion(+), 52 deletions(-)
>
> diff --git a/drivers/usb/host/ehci-pci.c b/drivers/usb/host/ehci-pci.c
> index 991b199..b9eabc5 100644
> --- a/drivers/usb/host/ehci-pci.c
> +++ b/drivers/usb/host/ehci-pci.c
> @@ -34,57 +34,6 @@ static struct pci_device_id ehci_pci_ids[] = {
>         {0, 0}
>  };
>  #else
> -static pci_dev_t ehci_find_class(int index)
> -{
> -       int bus;
> -       int devnum;
> -       pci_dev_t bdf;
> -       uint32_t class;
> -
> -       for (bus = 0; bus <= pci_last_busno(); bus++) {
> -               for (devnum = 0; devnum < PCI_MAX_PCI_DEVICES-1; devnum++) {
> -                       pci_read_config_dword(PCI_BDF(bus, devnum, 0),
> -                                             PCI_CLASS_REVISION, &class);
> -                       if (class >> 16 == 0xffff)
> -                               continue;
> -
> -                       for (bdf = PCI_BDF(bus, devnum, 0);
> -                                       bdf <= PCI_BDF(bus, devnum,
> -                                               PCI_MAX_PCI_FUNCTIONS - 1);
> -                                       bdf += PCI_BDF(0, 0, 1)) {
> -                               pci_read_config_dword(bdf, PCI_CLASS_REVISION,
> -                                                     &class);
> -                               class >>= 8;
> -                               /*
> -                                * Here be dragons! In case we have multiple
> -                                * PCI EHCI controllers, this function will
> -                                * be called multiple times as well. This
> -                                * function will scan the PCI busses, always
> -                                * starting from bus 0, device 0, function 0,
> -                                * until it finds an USB controller. The USB
> -                                * stack gives us an 'index' of a controller
> -                                * that is currently being registered, which
> -                                * is a number, starting from 0 and growing
> -                                * in ascending order as controllers are added.
> -                                * To avoid probing the same controller in tne
> -                                * subsequent runs of this function, we will
> -                                * skip 'index - 1' detected controllers and
> -                                * report the index'th controller.
> -                                */
> -                               if (class != PCI_CLASS_SERIAL_USB_EHCI)
> -                                       continue;
> -                               if (index) {
> -                                       index--;
> -                                       continue;
> -                               }
> -                               /* Return index'th controller. */
> -                               return bdf;
> -                       }
> -               }
> -       }
> -
> -       return -ENODEV;
> -}
>  #endif
>
>  /*
> @@ -102,7 +51,7 @@ int ehci_hcd_init(int index, enum usb_init_type init,
>  #ifdef CONFIG_PCI_EHCI_DEVICE
>         pdev = pci_find_devices(ehci_pci_ids, CONFIG_PCI_EHCI_DEVICE);
>  #else
> -       pdev = ehci_find_class(index);
> +       pdev = pci_find_class(PCI_CLASS_SERIAL_USB_EHCI, index);
>  #endif
>         if (pdev < 0) {
>                 printf("EHCI host controller not found\n");
> --

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

[U-Boot] [PATCH 06/23] usb: pci: Add XHCI driver for PCI

[Bin Meng]

On Tue, Jan 27, 2015 at 9:23 AM, Simon Glass <sjg@chromium.org> wrote:
> Add a driver which locates the available XHCI controllers on the PCI bus
> and makes them available.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> ---
>
>  drivers/usb/host/Makefile   |  1 +
>  drivers/usb/host/xhci-pci.c | 60 +++++++++++++++++++++++++++++++++++++++++++++
>  2 files changed, 61 insertions(+)
>  create mode 100644 drivers/usb/host/xhci-pci.c
>
> diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile
> index c11b551..66d6e9a 100644
> --- a/drivers/usb/host/Makefile
> +++ b/drivers/usb/host/Makefile
> @@ -47,6 +47,7 @@ obj-$(CONFIG_USB_XHCI) += xhci.o xhci-mem.o xhci-ring.o
>  obj-$(CONFIG_USB_XHCI_KEYSTONE) += xhci-keystone.o
>  obj-$(CONFIG_USB_XHCI_EXYNOS) += xhci-exynos5.o
>  obj-$(CONFIG_USB_XHCI_OMAP) += xhci-omap.o
> +obj-$(CONFIG_USB_XHCI_PCI) += xhci-pci.o
>
>  # designware
>  obj-$(CONFIG_USB_DWC2) += dwc2.o
> diff --git a/drivers/usb/host/xhci-pci.c b/drivers/usb/host/xhci-pci.c
> new file mode 100644
> index 0000000..361fcce
> --- /dev/null
> +++ b/drivers/usb/host/xhci-pci.c
> @@ -0,0 +1,60 @@
> +/*
> + * Copyright (c) 2015, Google, Inc
> + * Written by Simon Glass <sjg@chromium.org>
> + * All rights reserved.
> + *
> + * SPDX-License-Identifier:    GPL-2.0
> + */
> +
> +#include <common.h>
> +#include <errno.h>
> +#include <pci.h>
> +#include <usb.h>
> +
> +#include "xhci.h"
> +
> +/*
> + * Create the appropriate control structures to manage a new XHCI host
> + * controller.
> + */
> +int xhci_hcd_init(int index, struct xhci_hccr **ret_hccr,
> +                 struct xhci_hcor **ret_hcor)
> +{
> +       struct xhci_hccr *hccr;
> +       struct xhci_hcor *hcor;
> +       pci_dev_t pdev;
> +       uint32_t cmd;
> +       int len;
> +
> +       pdev = pci_find_class(PCI_CLASS_SERIAL_USB_XHCI, index);
> +       if (pdev < 0) {
> +               printf("XHCI host controller not found\n");
> +               return -1;
> +       }
> +
> +       hccr = (struct xhci_hccr *)pci_map_bar(pdev,
> +                       PCI_BASE_ADDRESS_0, PCI_REGION_MEM);
> +       len = HC_LENGTH(xhci_readl(&hccr->cr_capbase));
> +       hcor = (struct xhci_hcor *)((uint32_t)hccr + len);
> +
> +       debug("XHCI-PCI init hccr 0x%x and hcor 0x%x hc_length %d\n",
> +             (uint32_t)hccr, (uint32_t)hcor, len);
> +
> +       *ret_hccr = hccr;
> +       *ret_hcor = hcor;
> +
> +       /* enable busmaster */
> +       pci_read_config_dword(pdev, PCI_COMMAND, &cmd);
> +       cmd |= PCI_COMMAND_MASTER;
> +       pci_write_config_dword(pdev, PCI_COMMAND, cmd);
> +
> +       return 0;
> +}
> +
> +/*
> + * Destroy the appropriate control structures corresponding * to the XHCI host
> + * controller
> + */
> +void xhci_hcd_stop(int index)
> +{
> +}
> --

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

[U-Boot] [PATCH 07/23] x86: Add an option to enabling building a ROM file

[Bin Meng]

Hi Simon,

On Tue, Jan 27, 2015 at 9:23 AM, Simon Glass <sjg@chromium.org> wrote:
> Rather than requiring the Makefile to be modified, provide a build option to
> enable the ROM to be built.
>
> We cannot do this by default since it requires binary blobs. Without these
> the build will fail.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> ---
>
>  Makefile       |  5 +++--
>  doc/README.x86 | 10 ++++++----
>  2 files changed, 9 insertions(+), 6 deletions(-)
>
> diff --git a/Makefile b/Makefile
> index a876f1f..c6e4ad1 100644
> --- a/Makefile
> +++ b/Makefile
> @@ -729,8 +729,9 @@ ALL-$(CONFIG_SPL) += $(CONFIG_SPL_TARGET:"%"=%)
>  endif
>  ALL-$(CONFIG_REMAKE_ELF) += u-boot.elf
>
> -# We can't do this yet due to the need for binary blobs
> -# ALL-$(CONFIG_X86_RESET_VECTOR) += u-boot.rom
> +ifneq ($(BUILD_ROM),)
> +ALL-$(CONFIG_X86_RESET_VECTOR) += u-boot.rom
> +endif
>
>  # enable combined SPL/u-boot/dtb rules for tegra
>  ifneq ($(CONFIG_TEGRA),)
> diff --git a/doc/README.x86 b/doc/README.x86
> index 7df8cc5..809a291 100644
> --- a/doc/README.x86
> +++ b/doc/README.x86
> @@ -51,9 +51,11 @@ Building ROM version of U-Boot (hereafter referred to as u-boot.rom) is a
>  little bit tricky, as generally it requires several binary blobs which are not
>  shipped in the U-Boot source tree. Due to this reason, the u-boot.rom build is
>  not turned on by default in the U-Boot source tree. Firstly, you need turn it
> -on by uncommenting the following line in the main U-Boot Makefile:
> +on by enabling the ROM board:

the ROM 'board', or the ROM 'build'?

>
> -# ALL-$(CONFIG_X86_RESET_VECTOR) += u-boot.rom
> +$ export BUILD_ROM=y
> +
> +This tells the Makefile to build u-boot.rom as a target.
>
>  Link-specific instructions:
>
> @@ -126,11 +128,11 @@ Make sure 0x1110000 matches CONFIG_SYS_TEXT_BASE and 0x1110015 matches the
>  symbol address of _start (in arch/x86/cpu/start.S).
>
>  If you want to use ELF as the coreboot payload, change U-Boot configuration to
> -use CONFIG_OF_EMBED.
> +use CONFIG_OF_EMBED instead of CONFIG_OF_SEPARATE.
>
>  CPU Microcode
>  -------------
> -Modern CPU usually requires a special bit stream called microcode [5] to be
> +Modern CPUs usually requires a special bit stream called microcode [5] to be

I don't understand the changes. 'CPUs requires'?

>  loaded on the processor after power up in order to function properly. U-Boot
>  has already integrated these as hex dumps in the source tree.
>
> --

Regards,
Bin

[U-Boot] [PATCH 08/23] x86: Make MMCONF_BASE_ADDRESS common across x86

[Bin Meng]

Hi Simon,

On Tue, Jan 27, 2015 at 9:23 AM, Simon Glass <sjg@chromium.org> wrote:
> This setting will be used by more than just ivybridge so make it common.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> ---
>
>  arch/x86/Kconfig                     | 12 ++++++++++++
>  board/google/chromebook_link/Kconfig |  1 -
>  2 files changed, 12 insertions(+), 1 deletion(-)
>
> diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
> index 90e828a..1523c91 100644
> --- a/arch/x86/Kconfig
> +++ b/arch/x86/Kconfig
> @@ -356,4 +356,16 @@ source "board/google/chromebook_link/Kconfig"
>
>  source "board/intel/crownbay/Kconfig"
>
> +config MMCONF_BASE_ADDRESS

This name is sort of generic. How about PCIE_ECAM_BASE?

> +       hex
> +        default 0xe0000000
> +       help
> +         This is the address of PCI configuration space. It can be set up

Would it be better to write: This is the memory-mapped address of PCI
configuration space, which is only available through Enhanced
Configuration Access Mechanism (ECAM) with PCI Express.

> +         amost anywhere. Before it is set up, it is possible to access PCI

Typo of 'almost'. How about it is 'only' possible?

> +         configuration space through I/O access, but memory access is more
> +         convenient. Using this, PCI can be scanned and configured. This
> +         should be set to a region that does not conflict with memory
> +         assigned to PCI devices - i.e. the memory and prefetch regions, as
> +         passed to pci_set_region().
> +
>  endmenu
> diff --git a/board/google/chromebook_link/Kconfig b/board/google/chromebook_link/Kconfig
> index 33a31f3..948af59 100644
> --- a/board/google/chromebook_link/Kconfig
> +++ b/board/google/chromebook_link/Kconfig
> @@ -23,7 +23,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
>         select BOARD_ROMSIZE_KB_8192
>
>  config MMCONF_BASE_ADDRESS
> -       hex
>         default 0xf0000000
>
>  config EARLY_POST_CROS_EC
> --

Regards,
Bin

[U-Boot] [PATCH 09/23] x86: video: Allow video ROM execution to fall back to the other method

[Bin Meng]

Hi Simon,

On Tue, Jan 27, 2015 at 9:23 AM, Simon Glass <sjg@chromium.org> wrote:
> If the BIOS emulator is not available, allow use of native execution if
> available, and vice versa. This can be controlled by the caller.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> ---
>

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

But please see a minor comment below.

>  arch/x86/cpu/ivybridge/gma.c |  3 ++-
>  drivers/pci/pci_rom.c        | 32 +++++++++++++++++++++++++-------
>  drivers/video/vesa_fb.c      |  6 +++---
>  include/pci_rom.h            | 15 +++++++++++++--
>  4 files changed, 43 insertions(+), 13 deletions(-)
>
> diff --git a/arch/x86/cpu/ivybridge/gma.c b/arch/x86/cpu/ivybridge/gma.c
> index 6cf9654..821ea25 100644
> --- a/arch/x86/cpu/ivybridge/gma.c
> +++ b/arch/x86/cpu/ivybridge/gma.c
> @@ -758,7 +758,8 @@ int gma_func0_init(pci_dev_t dev, struct pci_controller *hose,
>
>  #ifdef CONFIG_VIDEO
>         start = get_timer(0);
> -       ret = pci_run_vga_bios(dev, int15_handler, false);
> +       ret = pci_run_vga_bios(dev, int15_handler, PCI_ROM_USE_NATIVE |
> +                              PCI_ROM_ALLOW_FALLBACK);
>         debug("BIOS ran in %lums\n", get_timer(start));
>  #endif
>         /* Post VBIOS init */
> diff --git a/drivers/pci/pci_rom.c b/drivers/pci/pci_rom.c
> index eb76591..0796179 100644
> --- a/drivers/pci/pci_rom.c
> +++ b/drivers/pci/pci_rom.c
> @@ -228,11 +228,12 @@ int vbe_get_video_info(struct graphic_device *gdev)
>  #endif
>  }
>
> -int pci_run_vga_bios(pci_dev_t dev, int (*int15_handler)(void), bool emulate)
> +int pci_run_vga_bios(pci_dev_t dev, int (*int15_handler)(void), int exec_method)
>  {
>         struct pci_rom_header *rom, *ram;
>         int vesa_mode = -1;
>         uint16_t class;
> +       bool emulate;
>         int ret;
>
>         /* Only execute VGA ROMs */
> @@ -262,6 +263,29 @@ int pci_run_vga_bios(pci_dev_t dev, int (*int15_handler)(void), bool emulate)
>         vesa_mode = CONFIG_FRAMEBUFFER_VESA_MODE;
>  #endif
>         debug("Selected vesa mode %#x\n", vesa_mode);
> +
> +       if (exec_method & PCI_ROM_USE_NATIVE) {
> +#ifdef CONFIG_X86
> +               emulate = false;
> +#else
> +               if (!(exec_method & PCI_ROM_ALLOW_FALLBACK)) {
> +                       printf("BIOS native execution is only available on x86\n");
> +                       return -ENOSYS;
> +               }
> +               emulate = true;
> +#endif
> +       } else {
> +#ifdef CONFIG_BIOSEMU
> +               emulate = true;
> +#else
> +               if (!(exec_method & PCI_ROM_ALLOW_FALLBACK)) {
> +                       printf("BIOS emulation not available - see CONFIG_BIOSEMU\n");
> +                       return -ENOSYS;
> +               }
> +               emulate = false;
> +#endif
> +       }
> +
>         if (emulate) {
>  #ifdef CONFIG_BIOSEMU
>                 BE_VGAInfo *info;
> @@ -274,9 +298,6 @@ int pci_run_vga_bios(pci_dev_t dev, int (*int15_handler)(void), bool emulate)
>                                   vesa_mode, &mode_info);
>                 if (ret)
>                         return ret;
> -#else
> -               printf("BIOS emulation not available - see CONFIG_BIOSEMU\n");
> -               return -ENOSYS;
>  #endif
>         } else {
>  #ifdef CONFIG_X86
> @@ -284,9 +305,6 @@ int pci_run_vga_bios(pci_dev_t dev, int (*int15_handler)(void), bool emulate)
>
>                 bios_run_on_x86(dev, (unsigned long)ram, vesa_mode,
>                                 &mode_info);
> -#else
> -               printf("BIOS native execution is only available on x86\n");
> -               return -ENOSYS;
>  #endif
>         }
>         debug("Final vesa mode %#x\n", mode_info.video_mode);
> diff --git a/drivers/video/vesa_fb.c b/drivers/video/vesa_fb.c
> index 3a0fea2..9164f8d 100644
> --- a/drivers/video/vesa_fb.c
> +++ b/drivers/video/vesa_fb.c
> @@ -42,8 +42,8 @@ void *video_hw_init(void)
>                         printf("no card detected\n");
>                         return NULL;
>                 }
> -               printf("bdf %x\n", dev);
> -               ret = pci_run_vga_bios(dev, NULL, true);
> +               ret = pci_run_vga_bios(dev, NULL, PCI_ROM_USE_NATIVE |
> +                                      PCI_ROM_ALLOW_FALLBACK);
>                 if (ret) {
>                         printf("failed to run video BIOS: %d\n", ret);
>                         return NULL;
> @@ -59,7 +59,7 @@ void *video_hw_init(void)
>         sprintf(gdev->modeIdent, "%dx%dx%d", gdev->winSizeX, gdev->winSizeY,
>                 bits_per_pixel);
>         printf("%s\n", gdev->modeIdent);
> -       debug("Framex buffer at %x\n", gdev->pciBase);
> +       debug("Frame buffer at %x\n", gdev->pciBase);
>
>         return (void *)gdev;
>  }
> diff --git a/include/pci_rom.h b/include/pci_rom.h
> index 4ba36eb..d24c52a 100644
> --- a/include/pci_rom.h
> +++ b/include/pci_rom.h
> @@ -33,14 +33,25 @@ struct pci_rom_data {
>         uint16_t reserved_2;
>  };
>
> +/*
> + * Determines which execution method is used and whether we allow falling back
> + * to the other if the requested method is not available.
> + */
> +enum pci_rom_emul_t {

I think we don't need the _t suffix?

> +       PCI_ROM_EMULATE         = 0 << 0,
> +       PCI_ROM_USE_NATIVE      = 1 << 0,
> +       PCI_ROM_ALLOW_FALLBACK  = 1 << 1,
> +};
> +
>   /**
>   * pci_run_vga_bios() - Run the VGA BIOS in an x86 PC
>   *
>   * @dev:       Video device containing the BIOS
>   * @int15_handler:     Function to call to handle int 0x15
> - * @emulate:   true to use the x86 emulator, false to run native
> + * @exec_method:       flags from enum pci_rom_emul_t
>   */
> -int pci_run_vga_bios(pci_dev_t dev, int (*int15_handler)(void), bool emulate);
> +int pci_run_vga_bios(pci_dev_t dev, int (*int15_handler)(void),
> +                    int exec_method);
>
>  /**
>   * board_map_oprom_vendev() - map several PCI IDs to the one the ROM expects
> --

Regards,
Bin

[U-Boot] [PATCH 10/23] x86: bootstage: Add time measurement for vesa start-up

[Bin Meng]

On Tue, Jan 27, 2015 at 9:23 AM, Simon Glass <sjg@chromium.org> wrote:
> Since we must run a PCI BIOS ROM, and this can take a calamitous amount of
> time, measure it using bootstage.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> ---
>
>  drivers/video/vesa_fb.c | 2 ++
>  1 file changed, 2 insertions(+)
>
> diff --git a/drivers/video/vesa_fb.c b/drivers/video/vesa_fb.c
> index 9164f8d..47f824a 100644
> --- a/drivers/video/vesa_fb.c
> +++ b/drivers/video/vesa_fb.c
> @@ -42,8 +42,10 @@ void *video_hw_init(void)
>                         printf("no card detected\n");
>                         return NULL;
>                 }
> +               bootstage_start(BOOTSTAGE_ID_ACCUM_LCD, "vesa display");
>                 ret = pci_run_vga_bios(dev, NULL, PCI_ROM_USE_NATIVE |
>                                        PCI_ROM_ALLOW_FALLBACK);
> +               bootstage_accum(BOOTSTAGE_ID_ACCUM_LCD);
>                 if (ret) {
>                         printf("failed to run video BIOS: %d\n", ret);
>                         return NULL;
> --

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

[U-Boot] [PATCH 11/23] x86: Move common FSP code into a common location

[Bin Meng]

Hi Simon,

On Tue, Jan 27, 2015 at 9:23 AM, Simon Glass <sjg@chromium.org> wrote:
> Signed-off-by: Simon Glass <sjg@chromium.org>
> ---
>

Nice to see the existing FSP support codes are common for new platforms.

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>

>  arch/x86/cpu/queensbay/Makefile                                | 2 +-
>  arch/x86/cpu/queensbay/fsp_configs.c                           | 2 +-
>  arch/x86/cpu/queensbay/tnc.c                                   | 2 +-
>  arch/x86/cpu/queensbay/tnc_dram.c                              | 2 +-
>  arch/x86/cpu/queensbay/tnc_pci.c                               | 2 +-
>  arch/x86/include/asm/{arch-queensbay => }/fsp/fsp_api.h        | 0
>  arch/x86/include/asm/{arch-queensbay => }/fsp/fsp_bootmode.h   | 0
>  arch/x86/include/asm/{arch-queensbay => }/fsp/fsp_ffs.h        | 0
>  arch/x86/include/asm/{arch-queensbay => }/fsp/fsp_fv.h         | 0
>  arch/x86/include/asm/{arch-queensbay => }/fsp/fsp_hob.h        | 0
>  arch/x86/include/asm/{arch-queensbay => }/fsp/fsp_infoheader.h | 0
>  arch/x86/include/asm/{arch-queensbay => }/fsp/fsp_platform.h   | 0
>  arch/x86/include/asm/{arch-queensbay => }/fsp/fsp_support.h    | 2 +-
>  arch/x86/include/asm/{arch-queensbay => }/fsp/fsp_types.h      | 0
>  arch/x86/lib/Makefile                                          | 1 +
>  arch/x86/lib/cmd_hob.c                                         | 2 +-
>  arch/x86/lib/fsp/Makefile                                      | 7 +++++++
>  arch/x86/{cpu/queensbay => lib/fsp}/fsp_support.c              | 2 +-
>  18 files changed, 16 insertions(+), 8 deletions(-)
>  rename arch/x86/include/asm/{arch-queensbay => }/fsp/fsp_api.h (100%)
>  rename arch/x86/include/asm/{arch-queensbay => }/fsp/fsp_bootmode.h (100%)
>  rename arch/x86/include/asm/{arch-queensbay => }/fsp/fsp_ffs.h (100%)
>  rename arch/x86/include/asm/{arch-queensbay => }/fsp/fsp_fv.h (100%)
>  rename arch/x86/include/asm/{arch-queensbay => }/fsp/fsp_hob.h (100%)
>  rename arch/x86/include/asm/{arch-queensbay => }/fsp/fsp_infoheader.h (100%)
>  rename arch/x86/include/asm/{arch-queensbay => }/fsp/fsp_platform.h (100%)
>  rename arch/x86/include/asm/{arch-queensbay => }/fsp/fsp_support.h (99%)
>  rename arch/x86/include/asm/{arch-queensbay => }/fsp/fsp_types.h (100%)
>  create mode 100644 arch/x86/lib/fsp/Makefile
>  rename arch/x86/{cpu/queensbay => lib/fsp}/fsp_support.c (99%)
>
> diff --git a/arch/x86/cpu/queensbay/Makefile b/arch/x86/cpu/queensbay/Makefile
> index 2c2ec01..b3e7d87 100644
> --- a/arch/x86/cpu/queensbay/Makefile
> +++ b/arch/x86/cpu/queensbay/Makefile
> @@ -5,5 +5,5 @@
>  #
>
>  obj-y += tnc_car.o tnc_dram.o tnc.o topcliff.o
> -obj-y += fsp_configs.o fsp_support.o
> +obj-y += fsp_configs.o
>  obj-$(CONFIG_PCI) += tnc_pci.o
> diff --git a/arch/x86/cpu/queensbay/fsp_configs.c b/arch/x86/cpu/queensbay/fsp_configs.c
> index af28e45..78bc966 100644
> --- a/arch/x86/cpu/queensbay/fsp_configs.c
> +++ b/arch/x86/cpu/queensbay/fsp_configs.c
> @@ -6,7 +6,7 @@
>   */
>
>  #include <common.h>
> -#include <asm/arch/fsp/fsp_support.h>
> +#include <asm/fsp/fsp_support.h>
>
>  void update_fsp_upd(struct upd_region *fsp_upd)
>  {
> diff --git a/arch/x86/cpu/queensbay/tnc.c b/arch/x86/cpu/queensbay/tnc.c
> index 8637cdc..f9b3bfa 100644
> --- a/arch/x86/cpu/queensbay/tnc.c
> +++ b/arch/x86/cpu/queensbay/tnc.c
> @@ -9,7 +9,7 @@
>  #include <asm/pci.h>
>  #include <asm/post.h>
>  #include <asm/arch/tnc.h>
> -#include <asm/arch/fsp/fsp_support.h>
> +#include <asm/fsp/fsp_support.h>
>  #include <asm/processor.h>
>
>  static void unprotect_spi_flash(void)
> diff --git a/arch/x86/cpu/queensbay/tnc_dram.c b/arch/x86/cpu/queensbay/tnc_dram.c
> index df79a39..4c0a7c8 100644
> --- a/arch/x86/cpu/queensbay/tnc_dram.c
> +++ b/arch/x86/cpu/queensbay/tnc_dram.c
> @@ -5,7 +5,7 @@
>   */
>
>  #include <common.h>
> -#include <asm/arch/fsp/fsp_support.h>
> +#include <asm/fsp/fsp_support.h>
>  #include <asm/e820.h>
>  #include <asm/post.h>
>
> diff --git a/arch/x86/cpu/queensbay/tnc_pci.c b/arch/x86/cpu/queensbay/tnc_pci.c
> index 39bff49..9b0b725 100644
> --- a/arch/x86/cpu/queensbay/tnc_pci.c
> +++ b/arch/x86/cpu/queensbay/tnc_pci.c
> @@ -7,7 +7,7 @@
>  #include <common.h>
>  #include <pci.h>
>  #include <asm/pci.h>
> -#include <asm/arch/fsp/fsp_support.h>
> +#include <asm/fsp/fsp_support.h>
>
>  DECLARE_GLOBAL_DATA_PTR;
>
> diff --git a/arch/x86/include/asm/arch-queensbay/fsp/fsp_api.h b/arch/x86/include/asm/fsp/fsp_api.h
> similarity index 100%
> rename from arch/x86/include/asm/arch-queensbay/fsp/fsp_api.h
> rename to arch/x86/include/asm/fsp/fsp_api.h
> diff --git a/arch/x86/include/asm/arch-queensbay/fsp/fsp_bootmode.h b/arch/x86/include/asm/fsp/fsp_bootmode.h
> similarity index 100%
> rename from arch/x86/include/asm/arch-queensbay/fsp/fsp_bootmode.h
> rename to arch/x86/include/asm/fsp/fsp_bootmode.h
> diff --git a/arch/x86/include/asm/arch-queensbay/fsp/fsp_ffs.h b/arch/x86/include/asm/fsp/fsp_ffs.h
> similarity index 100%
> rename from arch/x86/include/asm/arch-queensbay/fsp/fsp_ffs.h
> rename to arch/x86/include/asm/fsp/fsp_ffs.h
> diff --git a/arch/x86/include/asm/arch-queensbay/fsp/fsp_fv.h b/arch/x86/include/asm/fsp/fsp_fv.h
> similarity index 100%
> rename from arch/x86/include/asm/arch-queensbay/fsp/fsp_fv.h
> rename to arch/x86/include/asm/fsp/fsp_fv.h
> diff --git a/arch/x86/include/asm/arch-queensbay/fsp/fsp_hob.h b/arch/x86/include/asm/fsp/fsp_hob.h
> similarity index 100%
> rename from arch/x86/include/asm/arch-queensbay/fsp/fsp_hob.h
> rename to arch/x86/include/asm/fsp/fsp_hob.h
> diff --git a/arch/x86/include/asm/arch-queensbay/fsp/fsp_infoheader.h b/arch/x86/include/asm/fsp/fsp_infoheader.h
> similarity index 100%
> rename from arch/x86/include/asm/arch-queensbay/fsp/fsp_infoheader.h
> rename to arch/x86/include/asm/fsp/fsp_infoheader.h
> diff --git a/arch/x86/include/asm/arch-queensbay/fsp/fsp_platform.h b/arch/x86/include/asm/fsp/fsp_platform.h
> similarity index 100%
> rename from arch/x86/include/asm/arch-queensbay/fsp/fsp_platform.h
> rename to arch/x86/include/asm/fsp/fsp_platform.h
> diff --git a/arch/x86/include/asm/arch-queensbay/fsp/fsp_support.h b/arch/x86/include/asm/fsp/fsp_support.h
> similarity index 99%
> rename from arch/x86/include/asm/arch-queensbay/fsp/fsp_support.h
> rename to arch/x86/include/asm/fsp/fsp_support.h
> index ebdbd03..6329cfe 100644
> --- a/arch/x86/include/asm/arch-queensbay/fsp/fsp_support.h
> +++ b/arch/x86/include/asm/fsp/fsp_support.h
> @@ -16,7 +16,7 @@
>  #include "fsp_platform.h"
>  #include "fsp_infoheader.h"
>  #include "fsp_bootmode.h"
> -#include "fsp_vpd.h"
> +#include <asm/arch/fsp/fsp_vpd.h>
>
>  struct shared_data {
>         struct fsp_header       *fsp_hdr;
> diff --git a/arch/x86/include/asm/arch-queensbay/fsp/fsp_types.h b/arch/x86/include/asm/fsp/fsp_types.h
> similarity index 100%
> rename from arch/x86/include/asm/arch-queensbay/fsp/fsp_types.h
> rename to arch/x86/include/asm/fsp/fsp_types.h
> diff --git a/arch/x86/lib/Makefile b/arch/x86/lib/Makefile
> index 32d7b98..c17f7f0 100644
> --- a/arch/x86/lib/Makefile
> +++ b/arch/x86/lib/Makefile
> @@ -25,6 +25,7 @@ obj-y += string.o
>  obj-$(CONFIG_SYS_X86_TSC_TIMER)        += tsc_timer.o
>  obj-$(CONFIG_VIDEO_VGA)        += video.o
>  obj-$(CONFIG_CMD_ZBOOT)        += zimage.o
> +obj-$(CONFIG_HAVE_FSP) += fsp/
>
>  extra-$(CONFIG_USE_PRIVATE_LIBGCC) := lib.a
>
> diff --git a/arch/x86/lib/cmd_hob.c b/arch/x86/lib/cmd_hob.c
> index a0ef037..915746a 100644
> --- a/arch/x86/lib/cmd_hob.c
> +++ b/arch/x86/lib/cmd_hob.c
> @@ -7,7 +7,7 @@
>  #include <common.h>
>  #include <command.h>
>  #include <linux/compiler.h>
> -#include <asm/arch/fsp/fsp_support.h>
> +#include <asm/fsp/fsp_support.h>
>
>  DECLARE_GLOBAL_DATA_PTR;
>
> diff --git a/arch/x86/lib/fsp/Makefile b/arch/x86/lib/fsp/Makefile
> new file mode 100644
> index 0000000..1b9b0e2
> --- /dev/null
> +++ b/arch/x86/lib/fsp/Makefile
> @@ -0,0 +1,7 @@
> +#
> +# Copyright (C) 2015 Google, Inc
> +#
> +# SPDX-License-Identifier:     GPL-2.0+
> +#
> +
> +obj-y += fsp_support.o
> diff --git a/arch/x86/cpu/queensbay/fsp_support.c b/arch/x86/lib/fsp/fsp_support.c
> similarity index 99%
> rename from arch/x86/cpu/queensbay/fsp_support.c
> rename to arch/x86/lib/fsp/fsp_support.c
> index aed3e2b..f6ae85a 100644
> --- a/arch/x86/cpu/queensbay/fsp_support.c
> +++ b/arch/x86/lib/fsp/fsp_support.c
> @@ -6,7 +6,7 @@
>   */
>
>  #include <common.h>
> -#include <asm/arch/fsp/fsp_support.h>
> +#include <asm/fsp/fsp_support.h>
>  #include <asm/post.h>
>
>  /**
> --

Regards,
Bin

[U-Boot] [PATCH 14/23] x86: Move common FSP functions into a common file

[Bin Meng]

Hi Simon,

On Tue, Jan 27, 2015 at 9:23 AM, Simon Glass <sjg@chromium.org> wrote:
> Since these board functions seem to be the same for all boards which use
> FSP, move them into a common file. We can adjust this later if future FSPs
> need more flexibility.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> ---
>
>  arch/x86/cpu/queensbay/tnc.c      | 27 ------------
>  arch/x86/cpu/queensbay/tnc_pci.c  | 15 -------
>  arch/x86/cpu/queensbay/topcliff.c | 32 +-------------
>  arch/x86/include/asm/u-boot-x86.h | 17 ++++++++
>  arch/x86/lib/fsp/Makefile         |  1 +
>  arch/x86/lib/fsp/fsp_common.c     | 88 +++++++++++++++++++++++++++++++++++++++
>  6 files changed, 108 insertions(+), 72 deletions(-)
>  create mode 100644 arch/x86/lib/fsp/fsp_common.c
>
> diff --git a/arch/x86/cpu/queensbay/tnc.c b/arch/x86/cpu/queensbay/tnc.c
> index f9b3bfa..30ab725 100644
> --- a/arch/x86/cpu/queensbay/tnc.c
> +++ b/arch/x86/cpu/queensbay/tnc.c
> @@ -43,30 +43,3 @@ int arch_cpu_init(void)
>
>         return 0;
>  }
> -
> -int print_cpuinfo(void)
> -{
> -       post_code(POST_CPU_INFO);
> -       return default_print_cpuinfo();
> -}
> -
> -void reset_cpu(ulong addr)
> -{
> -       /* cold reset */
> -       outb(0x06, PORT_RESET);
> -}
> -
> -void board_final_cleanup(void)
> -{
> -       u32 status;
> -
> -       /* call into FspNotify */
> -       debug("Calling into FSP (notify phase INIT_PHASE_BOOT): ");
> -       status = fsp_notify(NULL, INIT_PHASE_BOOT);
> -       if (status != FSP_SUCCESS)
> -               debug("fail, error code %x\n", status);
> -       else
> -               debug("OK\n");
> -
> -       return;
> -}
> diff --git a/arch/x86/cpu/queensbay/tnc_pci.c b/arch/x86/cpu/queensbay/tnc_pci.c
> index 9b0b725..6c291f9 100644
> --- a/arch/x86/cpu/queensbay/tnc_pci.c
> +++ b/arch/x86/cpu/queensbay/tnc_pci.c
> @@ -44,18 +44,3 @@ void board_pci_setup_hose(struct pci_controller *hose)
>
>         hose->region_count = 4;
>  }
> -
> -int board_pci_post_scan(struct pci_controller *hose)
> -{
> -       u32 status;
> -
> -       /* call into FspNotify */
> -       debug("Calling into FSP (notify phase INIT_PHASE_PCI): ");
> -       status = fsp_notify(NULL, INIT_PHASE_PCI);
> -       if (status != FSP_SUCCESS)
> -               debug("fail, error code %x\n", status);
> -       else
> -               debug("OK\n");
> -
> -       return 0;
> -}
> diff --git a/arch/x86/cpu/queensbay/topcliff.c b/arch/x86/cpu/queensbay/topcliff.c
> index b01422a..25032cc 100644
> --- a/arch/x86/cpu/queensbay/topcliff.c
> +++ b/arch/x86/cpu/queensbay/topcliff.c
> @@ -5,43 +5,15 @@
>   */
>
>  #include <common.h>
> -#include <errno.h>
> -#include <malloc.h>
> -#include <pci.h>
>  #include <pci_ids.h>
> -#include <sdhci.h>
>
>  static struct pci_device_id mmc_supported[] = {
>         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TCF_SDIO_0 },
>         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TCF_SDIO_1 },
> -       { }
>  };
>
>  int cpu_mmc_init(bd_t *bis)
>  {
> -       struct sdhci_host *mmc_host;
> -       pci_dev_t devbusfn;
> -       u32 iobase;
> -       int ret;
> -       int i;
> -
> -       for (i = 0; i < ARRAY_SIZE(mmc_supported); i++) {
> -               devbusfn =  pci_find_devices(mmc_supported, i);
> -               if (devbusfn == -1)
> -                       return -ENODEV;
> -
> -               mmc_host = (struct sdhci_host *)malloc(sizeof(struct sdhci_host));
> -               if (!mmc_host)
> -                       return -ENOMEM;
> -
> -               mmc_host->name = "Topcliff SDHCI";
> -               pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_0, &iobase);
> -               mmc_host->ioaddr = (void *)iobase;
> -               mmc_host->quirks = 0;
> -               ret = add_sdhci(mmc_host, 0, 0);
> -               if (ret)
> -                       return ret;
> -       }
> -
> -       return 0;
> +       return fsp_cpu_mmc_init("Topcliff SDHCI", mmc_supported,
> +                               ARRAY_SIZE(mmc_supported));
>  }

I don't think this function should be moved to fsp_common.c as it has
nothing related to FSP. We can move this whole function to
drivers/mmc/, something like intel_mmc.c or intel_sdhc.c.

> diff --git a/arch/x86/include/asm/u-boot-x86.h b/arch/x86/include/asm/u-boot-x86.h
> index b98afa8..44c24ff 100644
> --- a/arch/x86/include/asm/u-boot-x86.h
> +++ b/arch/x86/include/asm/u-boot-x86.h
> @@ -45,6 +45,23 @@ ulong board_get_usable_ram_top(ulong total_size);
>  void dram_init_banksize(void);
>  int default_print_cpuinfo(void);
>
> +struct pci_device_id;
> +
> +/**
> + * fsp_cpu_mmc_init() - set up PCI MMC devices
> + *
> + * This finds all the matching PCI IDs and sets them up as MMC devices.
> + *
> + * @name:              Name to use for devices
> + * @mmc_supported:     PCI IDs to search for
> + * @num_ids:           Number of elements in @mmc_supported
> + */
> +int fsp_cpu_mmc_init(const char *name, struct pci_device_id mmc_supported[],
> +                    int num_ids);
> +
> +/* Set up a UART which can be used with printch(), printhex8(), etc. */
> +int setup_early_uart(void);
> +

Where is the setup_early_uart() function implementation?

>  void setup_pcat_compatibility(void);
>
>  void isa_unmap_rom(u32 addr);
> diff --git a/arch/x86/lib/fsp/Makefile b/arch/x86/lib/fsp/Makefile
> index 3a2bac0..5b12c12 100644
> --- a/arch/x86/lib/fsp/Makefile
> +++ b/arch/x86/lib/fsp/Makefile
> @@ -5,5 +5,6 @@
>  #
>
>  obj-y += fsp_car.o
> +obj-y += fsp_common.o
>  obj-y += fsp_dram.o
>  obj-y += fsp_support.o
> diff --git a/arch/x86/lib/fsp/fsp_common.c b/arch/x86/lib/fsp/fsp_common.c
> new file mode 100644
> index 0000000..846c136
> --- /dev/null
> +++ b/arch/x86/lib/fsp/fsp_common.c
> @@ -0,0 +1,88 @@
> +/*
> + * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
> + *
> + * SPDX-License-Identifier:    GPL-2.0+
> + */
> +
> +#include <common.h>
> +#include <errno.h>
> +#include <malloc.h>
> +#include <sdhci.h>
> +#include <asm/io.h>
> +#include <asm/pci.h>
> +#include <asm/post.h>
> +#include <asm/processor.h>
> +#include <asm/fsp/fsp_support.h>
> +
> +int print_cpuinfo(void)
> +{
> +       post_code(POST_CPU_INFO);
> +       return default_print_cpuinfo();
> +}
> +
> +void reset_cpu(ulong addr)
> +{
> +       /* cold reset */
> +       outb(0x06, PORT_RESET);
> +}
> +
> +
> +int board_pci_post_scan(struct pci_controller *hose)
> +{
> +       u32 status;
> +
> +       /* call into FspNotify */
> +       debug("Calling into FSP (notify phase INIT_PHASE_PCI): ");
> +       status = fsp_notify(NULL, INIT_PHASE_PCI);
> +       if (status != FSP_SUCCESS)
> +               debug("fail, error code %x\n", status);
> +       else
> +               debug("OK\n");
> +
> +       return 0;
> +}
> +
> +void board_final_cleanup(void)
> +{
> +       u32 status;
> +
> +       /* call into FspNotify */
> +       debug("Calling into FSP (notify phase INIT_PHASE_BOOT): ");
> +       status = fsp_notify(NULL, INIT_PHASE_BOOT);
> +       if (status != FSP_SUCCESS)
> +               debug("fail, error code %x\n", status);
> +       else
> +               debug("OK\n");
> +
> +       return;
> +}
> +
> +int fsp_cpu_mmc_init(const char *name, struct pci_device_id mmc_supported[],
> +                    int num_ids)
> +{
> +       struct sdhci_host *mmc_host;
> +       pci_dev_t devbusfn;
> +       u32 iobase;
> +       int ret;
> +       int i;
> +
> +       for (i = 0; i < num_ids; i++) {
> +               devbusfn = pci_find_devices(mmc_supported, i);
> +               if (devbusfn == -1)
> +                       return -ENODEV;
> +
> +               mmc_host = malloc(sizeof(struct sdhci_host));
> +               if (!mmc_host)
> +                       return -ENOMEM;
> +
> +               mmc_host->name = (char *)name;
> +               pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_0, &iobase);
> +               mmc_host->ioaddr = (void *)iobase;
> +               mmc_host->quirks = 0;
> +               ret = add_sdhci(mmc_host, 0, 0);
> +               if (ret)
> +                       return ret;
> +       }
> +
> +       return 0;
> +}
> --

Regards,
Bin

[U-Boot] [PATCH 12/23] x86: Adjust the FSP types slightly

[Bin Meng]

On Tue, Jan 27, 2015 at 9:23 AM, Simon Glass <sjg@chromium.org> wrote:
> To avoid casts, find_fsp_header() should return a pointer. Add asmlinkage
> to two API functions which use that convention. UPD_TERMINATOR is common
> so move it into a common file.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> ---
>
>  arch/x86/include/asm/arch-queensbay/fsp/fsp_vpd.h | 2 --
>  arch/x86/include/asm/fsp/fsp_api.h                | 6 ++++--
>  arch/x86/include/asm/fsp/fsp_support.h            | 4 +++-
>  arch/x86/lib/fsp/fsp_support.c                    | 4 ++--
>  4 files changed, 9 insertions(+), 7 deletions(-)
>
> diff --git a/arch/x86/include/asm/arch-queensbay/fsp/fsp_vpd.h b/arch/x86/include/asm/arch-queensbay/fsp/fsp_vpd.h
> index bce58b1..3c57558 100644
> --- a/arch/x86/include/asm/arch-queensbay/fsp/fsp_vpd.h
> +++ b/arch/x86/include/asm/arch-queensbay/fsp/fsp_vpd.h
> @@ -10,8 +10,6 @@
>  #ifndef __VPDHEADER_H__
>  #define __VPDHEADER_H__
>
> -#define UPD_TERMINATOR 0x55AA
> -
>  struct __packed upd_region {
>         u64     sign;                   /* Offset 0x0000 */
>         u64     reserved;               /* Offset 0x0008 */
> diff --git a/arch/x86/include/asm/fsp/fsp_api.h b/arch/x86/include/asm/fsp/fsp_api.h
> index a9d7156..2d34d13 100644
> --- a/arch/x86/include/asm/fsp/fsp_api.h
> +++ b/arch/x86/include/asm/fsp/fsp_api.h
> @@ -8,6 +8,8 @@
>  #ifndef __FSP_API_H__
>  #define __FSP_API_H__
>
> +#include <linux/linkage.h>
> +
>  /*
>   * FspInit continuation function prototype.
>   * Control will be returned to this callback function after FspInit API call.
> @@ -47,9 +49,9 @@ struct fsp_notify_params {
>  };
>
>  /* FspInit API function prototype */
> -typedef u32 (*fsp_init_f)(struct fsp_init_params *params);
> +typedef asmlinkage u32 (*fsp_init_f)(struct fsp_init_params *params);
>
>  /* FspNotify API function prototype */
> -typedef u32 (*fsp_notify_f)(struct fsp_notify_params *params);
> +typedef asmlinkage u32 (*fsp_notify_f)(struct fsp_notify_params *params);
>
>  #endif
> diff --git a/arch/x86/include/asm/fsp/fsp_support.h b/arch/x86/include/asm/fsp/fsp_support.h
> index 6329cfe..c6c7dc0 100644
> --- a/arch/x86/include/asm/fsp/fsp_support.h
> +++ b/arch/x86/include/asm/fsp/fsp_support.h
> @@ -26,6 +26,8 @@ struct shared_data {
>
>  #define FSP_LOWMEM_BASE                0x100000UL
>  #define FSP_HIGHMEM_BASE       0x100000000ULL
> +#define UPD_TERMINATOR         0x55AA
> +
>
>  /**
>   * FSP Continuation assembly helper routine
> @@ -61,7 +63,7 @@ void fsp_continue(struct shared_data *shared_data, u32 status,
>   *
>   * @retval: the offset of FSP header. If signature is invalid, returns 0.
>   */
> -u32 find_fsp_header(void);
> +struct fsp_header *find_fsp_header(void);
>
>  /**
>   * FSP initialization wrapper function.
> diff --git a/arch/x86/lib/fsp/fsp_support.c b/arch/x86/lib/fsp/fsp_support.c
> index f6ae85a..bf37807 100644
> --- a/arch/x86/lib/fsp/fsp_support.c
> +++ b/arch/x86/lib/fsp/fsp_support.c
> @@ -30,7 +30,7 @@ static bool compare_guid(const struct efi_guid *guid1,
>                 return false;
>  }
>
> -u32 __attribute__((optimize("O0"))) find_fsp_header(void)
> +struct fsp_header *__attribute__((optimize("O0"))) find_fsp_header(void)
>  {
>         /*
>          * This function may be called before the a stack is established,
> @@ -84,7 +84,7 @@ u32 __attribute__((optimize("O0"))) find_fsp_header(void)
>                 fsp = 0;
>         }
>
> -       return (u32)fsp;
> +       return (struct fsp_header *)fsp;
>  }
>
>  void fsp_continue(struct shared_data *shared_data, u32 status, void *hob_list)
> --

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>

[U-Boot] [PATCH 13/23] x86: Make CAR and DRAM FSP code common

[Bin Meng]

On Tue, Jan 27, 2015 at 9:23 AM, Simon Glass <sjg@chromium.org> wrote:
> For now this code seems to be the same for all FSP platforms. Make it
> common until we see what differences are required.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> ---
>
>  arch/x86/cpu/queensbay/Makefile                           | 2 +-
>  arch/x86/lib/fsp/Makefile                                 | 2 ++
>  arch/x86/{cpu/queensbay/tnc_car.S => lib/fsp/fsp_car.S}   | 0
>  arch/x86/{cpu/queensbay/tnc_dram.c => lib/fsp/fsp_dram.c} | 0
>  4 files changed, 3 insertions(+), 1 deletion(-)
>  rename arch/x86/{cpu/queensbay/tnc_car.S => lib/fsp/fsp_car.S} (100%)
>  rename arch/x86/{cpu/queensbay/tnc_dram.c => lib/fsp/fsp_dram.c} (100%)
>
> diff --git a/arch/x86/cpu/queensbay/Makefile b/arch/x86/cpu/queensbay/Makefile
> index b3e7d87..d8761fd 100644
> --- a/arch/x86/cpu/queensbay/Makefile
> +++ b/arch/x86/cpu/queensbay/Makefile
> @@ -4,6 +4,6 @@
>  # SPDX-License-Identifier:     GPL-2.0+
>  #
>
> -obj-y += tnc_car.o tnc_dram.o tnc.o topcliff.o
>  obj-y += fsp_configs.o
> +obj-y += tnc.o topcliff.o
>  obj-$(CONFIG_PCI) += tnc_pci.o
> diff --git a/arch/x86/lib/fsp/Makefile b/arch/x86/lib/fsp/Makefile
> index 1b9b0e2..3a2bac0 100644
> --- a/arch/x86/lib/fsp/Makefile
> +++ b/arch/x86/lib/fsp/Makefile
> @@ -4,4 +4,6 @@
>  # SPDX-License-Identifier:     GPL-2.0+
>  #
>
> +obj-y += fsp_car.o
> +obj-y += fsp_dram.o
>  obj-y += fsp_support.o
> diff --git a/arch/x86/cpu/queensbay/tnc_car.S b/arch/x86/lib/fsp/fsp_car.S
> similarity index 100%
> rename from arch/x86/cpu/queensbay/tnc_car.S
> rename to arch/x86/lib/fsp/fsp_car.S
> diff --git a/arch/x86/cpu/queensbay/tnc_dram.c b/arch/x86/lib/fsp/fsp_dram.c
> similarity index 100%
> rename from arch/x86/cpu/queensbay/tnc_dram.c
> rename to arch/x86/lib/fsp/fsp_dram.c
> --

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>

[U-Boot] [PATCH 15/23] x86: Remove unnecessary casts and fix comment typos

[Bin Meng]

On Tue, Jan 27, 2015 at 9:23 AM, Simon Glass <sjg@chromium.org> wrote:
> Tidy up the FSP support code a little.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> ---
>
>  arch/x86/lib/fsp/fsp_support.c | 10 +++++-----
>  1 file changed, 5 insertions(+), 5 deletions(-)
>
> diff --git a/arch/x86/lib/fsp/fsp_support.c b/arch/x86/lib/fsp/fsp_support.c
> index bf37807..8b639f7 100644
> --- a/arch/x86/lib/fsp/fsp_support.c
> +++ b/arch/x86/lib/fsp/fsp_support.c
> @@ -124,25 +124,25 @@ void fsp_init(u32 stack_top, u32 boot_mode, void *nvs_buf)
>         struct fsp_init_params *params_ptr;
>         struct upd_region *fsp_upd;
>
> -       fsp_hdr = (struct fsp_header *)find_fsp_header();
> +       fsp_hdr = find_fsp_header();
>         if (fsp_hdr == NULL) {
>                 /* No valid FSP info header was found */
>                 panic("Invalid FSP header");
>         }
>
> -       fsp_upd = (struct upd_region *)&shared_data.fsp_upd;
> +       fsp_upd = &shared_data.fsp_upd;
>         memset(&rt_buf, 0, sizeof(struct fspinit_rtbuf));
>
>         /* Reserve a gap in stack top */
>         rt_buf.common.stack_top = (u32 *)stack_top - 32;
>         rt_buf.common.boot_mode = boot_mode;
> -       rt_buf.common.upd_data = (struct upd_region *)fsp_upd;
> +       rt_buf.common.upd_data = fsp_upd;
>
>         /* Get VPD region start */
>         fsp_vpd = (struct vpd_region *)(fsp_hdr->img_base +
>                         fsp_hdr->cfg_region_off);
>
> -       /* Verifify the VPD data region is valid */
> +       /* Verify the VPD data region is valid */
>         assert((fsp_vpd->img_rev == VPD_IMAGE_REV) &&
>                (fsp_vpd->sign == VPD_IMAGE_ID));
>
> @@ -150,7 +150,7 @@ void fsp_init(u32 stack_top, u32 boot_mode, void *nvs_buf)
>         memcpy(fsp_upd, (void *)(fsp_hdr->img_base + fsp_vpd->upd_offset),
>                sizeof(struct upd_region));
>
> -       /* Verifify the UPD data region is valid */
> +       /* Verify the UPD data region is valid */
>         assert(fsp_upd->terminator == UPD_TERMINATOR);
>
>         /* Override any UPD setting if required */
> --

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

[U-Boot] [PATCH 16/23] x86: Allow FSP Kconfig settings for all x86

[Bin Meng]

On Tue, Jan 27, 2015 at 9:23 AM, Simon Glass <sjg@chromium.org> wrote:
> While queensbay is the first chip with these settings, others will want to
> use them too. Make them common.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> ---
>
>  arch/x86/Kconfig               | 38 ++++++++++++++++++++++++++++++++++++++
>  arch/x86/cpu/queensbay/Kconfig | 38 --------------------------------------
>  2 files changed, 38 insertions(+), 38 deletions(-)
>
> diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
> index 1523c91..73a7392 100644
> --- a/arch/x86/Kconfig
> +++ b/arch/x86/Kconfig
> @@ -344,6 +344,44 @@ config TSC_FREQ_IN_MHZ
>         help
>           The running frequency in MHz of Time-Stamp Counter (TSC).
>
> +config HAVE_FSP
> +       bool "Add an Firmware Support Package binary"
> +       help
> +         Select this option to add an Firmware Support Package binary to
> +         the resulting U-Boot image. It is a binary blob which U-Boot uses
> +         to set up SDRAM and other chipset specific initialization.
> +
> +         Note: Without this binary U-Boot will not be able to set up its
> +         SDRAM so will not boot.
> +
> +config FSP_FILE
> +       string "Firmware Support Package binary filename"
> +       depends on HAVE_FSP
> +       default "fsp.bin"
> +       help
> +         The filename of the file to use as Firmware Support Package binary
> +         in the board directory.
> +
> +config FSP_ADDR
> +       hex "Firmware Support Package binary location"
> +       depends on HAVE_FSP
> +       default 0xfffc0000
> +       help
> +         FSP is not Position Independent Code (PIC) and the whole FSP has to
> +         be rebased if it is placed at a location which is different from the
> +         perferred base address specified during the FSP build. Use Intel's
> +         Binary Configuration Tool (BCT) to do the rebase.
> +
> +         The default base address of 0xfffc0000 indicates that the binary must
> +         be located at offset 0xc0000 from the beginning of a 1MB flash device.
> +
> +config FSP_TEMP_RAM_ADDR
> +       hex
> +       default 0x2000000
> +       help
> +         Stack top address which is used in FspInit after DRAM is ready and
> +         CAR is disabled.
> +
>  source "arch/x86/cpu/coreboot/Kconfig"
>
>  source "arch/x86/cpu/ivybridge/Kconfig"
> diff --git a/arch/x86/cpu/queensbay/Kconfig b/arch/x86/cpu/queensbay/Kconfig
> index f6b5201..397e599 100644
> --- a/arch/x86/cpu/queensbay/Kconfig
> +++ b/arch/x86/cpu/queensbay/Kconfig
> @@ -11,44 +11,6 @@ config INTEL_QUEENSBAY
>
>  if INTEL_QUEENSBAY
>
> -config HAVE_FSP
> -       bool "Add an Firmware Support Package binary"
> -       help
> -         Select this option to add an Firmware Support Package binary to
> -         the resulting U-Boot image. It is a binary blob which U-Boot uses
> -         to set up SDRAM and other chipset specific initialization.
> -
> -         Note: Without this binary U-Boot will not be able to set up its
> -         SDRAM so will not boot.
> -
> -config FSP_FILE
> -       string "Firmware Support Package binary filename"
> -       depends on HAVE_FSP
> -       default "fsp.bin"
> -       help
> -         The filename of the file to use as Firmware Support Package binary
> -         in the board directory.
> -
> -config FSP_ADDR
> -       hex "Firmware Support Package binary location"
> -       depends on HAVE_FSP
> -       default 0xfffc0000
> -       help
> -         FSP is not Position Independent Code (PIC) and the whole FSP has to
> -         be rebased if it is placed at a location which is different from the
> -         perferred base address specified during the FSP build. Use Intel's
> -         Binary Configuration Tool (BCT) to do the rebase.
> -
> -         The default base address of 0xfffc0000 indicates that the binary must
> -         be located at offset 0xc0000 from the beginning of a 1MB flash device.
> -
> -config FSP_TEMP_RAM_ADDR
> -       hex
> -       default 0x2000000
> -       help
> -         Stack top address which is used in FspInit after DRAM is ready and
> -         CAR is disabled.
> -
>  config HAVE_CMC
>         bool "Add a Chipset Micro Code state machine binary"
>         help
> --

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

[U-Boot] [PATCH 17/23] x86: Define cache line size

[Bin Meng]

Hi Simon,

On Tue, Jan 27, 2015 at 9:23 AM, Simon Glass <sjg@chromium.org> wrote:
> This avoids a warning in the Realtek Ethernet driver. The value may not
> matter on x86.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> ---
>
>  arch/x86/include/asm/cache.h | 2 ++
>  1 file changed, 2 insertions(+)
>
> diff --git a/arch/x86/include/asm/cache.h b/arch/x86/include/asm/cache.h
> index 508b63f..fff1edd 100644
> --- a/arch/x86/include/asm/cache.h
> +++ b/arch/x86/include/asm/cache.h
> @@ -7,6 +7,8 @@
>  #ifndef __X86_CACHE_H__
>  #define __X86_CACHE_H__
>
> +#define CONFIG_SYS_CACHELINE_SIZE      16

I think we should either fix the Realtek ethernet driver, or just move
this '#define CONFIG_SYS_CACHELINE_SIZE 16' to include/configs/board.h
as a workaround. Simply defining cache line size to 16 to avoid the
driver warning does not look good to me, esecially it is not a correct
number in a generic arch header file.

> +
>  /*
>   * If CONFIG_SYS_CACHELINE_SIZE is defined use it for DMA alignment.  Otherwise
>   * use 64-bytes, a safe default for x86.
> --

Regards,
Bin

[U-Boot] [PATCH 18/23] x86: Allow a UART to be set up before the FSP is ready

[Bin Meng]

Hi Simon,

On Tue, Jan 27, 2015 at 9:23 AM, Simon Glass <sjg@chromium.org> wrote:
> Since the FSP is a black box it helps to have some sort of debugging
> available to check its inputs. If the debug UART is in use, set it up
> after CAR is available.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> ---
>
>  arch/x86/include/asm/u-boot-x86.h | 3 +++
>  arch/x86/lib/fsp/fsp_support.c    | 4 ++++
>  2 files changed, 7 insertions(+)
>
> diff --git a/arch/x86/include/asm/u-boot-x86.h b/arch/x86/include/asm/u-boot-x86.h
> index 44c24ff..85fafc0 100644
> --- a/arch/x86/include/asm/u-boot-x86.h
> +++ b/arch/x86/include/asm/u-boot-x86.h
> @@ -62,6 +62,9 @@ int fsp_cpu_mmc_init(const char *name, struct pci_device_id mmc_supported[],
>  /* Set up a UART which can be used with printch(), printhex8(), etc. */
>  int setup_early_uart(void);
>
> +/* Set up a UART which can be used with printch(), printhex8(), etc. */
> +int setup_early_uart(void);
> +

Duplicated setup_early_uart() here .. The first one was wrongly
introduced in patch#14 in this series.

>  void setup_pcat_compatibility(void);
>
>  void isa_unmap_rom(u32 addr);
> diff --git a/arch/x86/lib/fsp/fsp_support.c b/arch/x86/lib/fsp/fsp_support.c
> index 8b639f7..5f96da1 100644
> --- a/arch/x86/lib/fsp/fsp_support.c
> +++ b/arch/x86/lib/fsp/fsp_support.c
> @@ -124,6 +124,10 @@ void fsp_init(u32 stack_top, u32 boot_mode, void *nvs_buf)
>         struct fsp_init_params *params_ptr;
>         struct upd_region *fsp_upd;
>
> +#ifdef CONFIG_DEBUG_UART
> +       setup_early_uart();
> +#endif
> +
>         fsp_hdr = find_fsp_header();
>         if (fsp_hdr == NULL) {
>                 /* No valid FSP info header was found */
> --

Regards,
Bin

[U-Boot] [PATCH 20/23] scsi: bootstage: Measure time taken to scan the bus

[Bin Meng]

On Tue, Jan 27, 2015 at 9:23 AM, Simon Glass <sjg@chromium.org> wrote:
> On some hardware this time can be significant. Add bootstage support for
> measuring this. The result can be obtained using 'bootstage report' or
> passed on to the Linux via the device tree.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> ---
>
>  common/cmd_scsi.c   | 2 ++
>  include/bootstage.h | 1 +
>  2 files changed, 3 insertions(+)
>
> diff --git a/common/cmd_scsi.c b/common/cmd_scsi.c
> index cbc107e..a0a62eb 100644
> --- a/common/cmd_scsi.c
> +++ b/common/cmd_scsi.c
> @@ -217,8 +217,10 @@ void scsi_init(void)
>                        (busdevfunc >> 8) & 0x7);
>         }
>  #endif
> +       bootstage_start(BOOTSTAGE_ID_ACCUM_SCSI, "ahci");
>         scsi_low_level_init(busdevfunc);
>         scsi_scan(1);
> +       bootstage_accum(BOOTSTAGE_ID_ACCUM_SCSI);
>  }
>  #endif
>
> diff --git a/include/bootstage.h b/include/bootstage.h
> index df13ab2..6b7588d 100644
> --- a/include/bootstage.h
> +++ b/include/bootstage.h
> @@ -194,6 +194,7 @@ enum bootstage_id {
>         BOOTSTAGE_ID_MAIN_CPU_READY,
>
>         BOOTSTAGE_ID_ACCUM_LCD,
> +       BOOTSTAGE_ID_ACCUM_SCSI,
>
>         /* a few spare for the user, from here */
>         BOOTSTAGE_ID_USER,
> --

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

[U-Boot] [PATCH 21/23] x86: Enable bootstage features

[Bin Meng]

On Tue, Jan 27, 2015 at 9:23 AM, Simon Glass <sjg@chromium.org> wrote:
> Allow measuring of boot time using bootstage.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> ---
>
>  include/configs/x86-common.h | 3 +++
>  1 file changed, 3 insertions(+)
>
> diff --git a/include/configs/x86-common.h b/include/configs/x86-common.h
> index ecedfc3..66d4894 100644
> --- a/include/configs/x86-common.h
> +++ b/include/configs/x86-common.h
> @@ -245,6 +245,9 @@
>  #define CONFIG_BOOTP_GATEWAY
>  #define CONFIG_BOOTP_HOSTNAME
>
> +#define CONFIG_BOOTSTAGE
> +#define CONFIG_CMD_BOOTSTAGE
> +
>  #define CONFIG_CMD_USB
>
>  #define CONFIG_EXTRA_ENV_SETTINGS \
> --

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>

[U-Boot] [PATCH 19/23] x86: spi: Support ValleyView in ICH SPI driver

[Bin Meng]

Hi Simon,

On Tue, Jan 27, 2015 at 9:23 AM, Simon Glass <sjg@chromium.org> wrote:
> The base address is found in a different way and the protection bit is also
> in a different place. Otherwise it is very similar.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> ---
>
>  drivers/spi/ich.c | 56 ++++++++++++++++++++++++++++++++++++++++---------------
>  drivers/spi/ich.h | 11 ++++++-----
>  2 files changed, 47 insertions(+), 20 deletions(-)
>
> diff --git a/drivers/spi/ich.c b/drivers/spi/ich.c
> index fdff158..da85779 100644
> --- a/drivers/spi/ich.c
> +++ b/drivers/spi/ich.c
> @@ -7,6 +7,7 @@
>   */
>
>  #include <common.h>
> +#include <errno.h>
>  #include <malloc.h>
>  #include <spi.h>
>  #include <pci.h>
> @@ -21,6 +22,7 @@
>  struct ich_ctlr {
>         pci_dev_t dev;          /* PCI device number */
>         int ich_version;        /* Controller version, 7 or 9 */
> +       bool use_sbase;         /* Use SBASE instead of RCB */
>         int ichspi_lock;
>         int locked;
>         uint8_t *opmenu;
> @@ -145,7 +147,7 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
>          * ICH 7 SPI controller only supports array read command
>          * and byte program command for SST flash
>          */
> -       if (ctlr.ich_version == 7) {
> +       if (ctlr.ich_version == 7 || ctlr.use_sbase) {
>                 ich->slave.op_mode_rx = SPI_OPM_RX_AS;
>                 ich->slave.op_mode_tx = SPI_OPM_TX_BP;
>         }

So the Valleyview SPI controller (version 9) has the same behavior
that was seen on Tunnel Creek (version 7). I wonder whether the same
behavior was seen on chromebook_link which is also version 9? Or is
this only because the Minnowmax board has the same SST flash mounted
on board, just like the Crown Bay so that we need set these RX/TX
flags. If SPI controller on chromebook_link also has the simliar
behavior, we should consider set these flags for all Intel SPI
controller variants. This way, the 'use_sbase' variable may not be
necessary (see below for more comments).

> @@ -181,7 +183,8 @@ static int get_ich_version(uint16_t device_id)
>         if ((device_id >= PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_MIN &&
>              device_id <= PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_MAX) ||
>             (device_id >= PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_MIN &&
> -            device_id <= PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_MAX))
> +            device_id <= PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_MAX) ||
> +           device_id == PCI_DEVICE_ID_INTEL_VALLEYVIEW_LPC)

To avoid bigger and bigger test logic, should we consider using DT to
pass such information?

>                 return 9;
>
>         return 0;
> @@ -204,14 +207,14 @@ static int ich9_can_do_33mhz(pci_dev_t dev)
>         return speed == 1;
>  }
>
> -static int ich_find_spi_controller(pci_dev_t *devp, int *ich_versionp)
> +static int ich_find_spi_controller(struct ich_ctlr *ich)
>  {
>         int last_bus = pci_last_busno();
>         int bus;
>
>         if (last_bus == -1) {
>                 debug("No PCI busses?\n");
> -               return -1;
> +               return -ENODEV;
>         }
>
>         for (bus = 0; bus <= last_bus; bus++) {
> @@ -225,24 +228,33 @@ static int ich_find_spi_controller(pci_dev_t *devp, int *ich_versionp)
>                 device_id = ids >> 16;
>
>                 if (vendor_id == PCI_VENDOR_ID_INTEL) {
> -                       *devp = dev;
> -                       *ich_versionp = get_ich_version(device_id);
> -                       return 0;
> +                       ich->dev = dev;
> +                       ich->ich_version = get_ich_version(device_id);
> +                       if (device_id == PCI_DEVICE_ID_INTEL_VALLEYVIEW_LPC)
> +                               ich->use_sbase = true;
> +                       return ich->ich_version == 0 ? -ENODEV : 0;
>                 }
>         }
>
>         debug("ICH SPI: No ICH found.\n");
> -       return -1;
> +       return -ENODEV;
>  }
>
>  static int ich_init_controller(struct ich_ctlr *ctlr)
>  {
>         uint8_t *rcrb; /* Root Complex Register Block */
>         uint32_t rcba; /* Root Complex Base Address */
> +       uint32_t sbase_addr;
> +       uint8_t *sbase;
>
>         pci_read_config_dword(ctlr->dev, 0xf0, &rcba);
>         /* Bits 31-14 are the base address, 13-1 are reserved, 0 is enable. */
>         rcrb = (uint8_t *)(rcba & 0xffffc000);
> +
> +       /* SBASE is similar */
> +       pci_read_config_dword(ctlr->dev, 0x54, &sbase_addr);
> +       sbase = (uint8_t *)(sbase_addr & 0xfffffe00);
> +

Again, DT can be used to determine the base address.

>         if (ctlr->ich_version == 7) {
>                 struct ich7_spi_regs *ich7_spi;
>
> @@ -262,7 +274,10 @@ static int ich_init_controller(struct ich_ctlr *ctlr)
>         } else if (ctlr->ich_version == 9) {
>                 struct ich9_spi_regs *ich9_spi;
>
> -               ich9_spi = (struct ich9_spi_regs *)(rcrb + 0x3800);
> +               if (ctlr->use_sbase)
> +                       ich9_spi = (struct ich9_spi_regs *)sbase;
> +               else
> +                       ich9_spi = (struct ich9_spi_regs *)(rcrb + 0x3800);

Ditto.

>                 ctlr->ichspi_lock = ich_readw(&ich9_spi->hsfs) & HSFS_FLOCKDN;
>                 ctlr->opmenu = ich9_spi->opmenu;
>                 ctlr->menubytes = sizeof(ich9_spi->opmenu);
> @@ -282,12 +297,13 @@ static int ich_init_controller(struct ich_ctlr *ctlr)
>                       ctlr->ich_version);
>                 return -1;
>         }
> -       debug("ICH SPI: Version %d detected\n", ctlr->ich_version);
>
>         /* Work out the maximum speed we can support */
>         ctlr->max_speed = 20000000;
>         if (ctlr->ich_version == 9 && ich9_can_do_33mhz(ctlr->dev))
>                 ctlr->max_speed = 33000000;
> +       debug("ICH SPI: Version %d detected at %p, speed %ld\n",
> +             ctlr->ich_version, ctlr->base, ctlr->max_speed);
>
>         ich_set_bbar(ctlr, 0);
>
> @@ -298,7 +314,7 @@ void spi_init(void)
>  {
>         uint8_t bios_cntl;
>
> -       if (ich_find_spi_controller(&ctlr.dev, &ctlr.ich_version)) {
> +       if (ich_find_spi_controller(&ctlr)) {
>                 printf("ICH SPI: Cannot find device\n");
>                 return;
>         }
> @@ -312,10 +328,20 @@ void spi_init(void)
>          * Disable the BIOS write protect so write commands are allowed.  On
>          * v9, deassert SMM BIOS Write Protect Disable.
>          */
> -       pci_read_config_byte(ctlr.dev, 0xdc, &bios_cntl);
> -       if (ctlr.ich_version == 9)
> -               bios_cntl &= ~(1 << 5);
> -       pci_write_config_byte(ctlr.dev, 0xdc, bios_cntl | 0x1);
> +       if (ctlr.use_sbase) {
> +               struct ich9_spi_regs *ich9_spi;
> +
> +               ich9_spi = (struct ich9_spi_regs *)ctlr.base;
> +               bios_cntl = ich_readb(&ich9_spi->bcr);
> +               bios_cntl &= ~(1 << 5); /* clear Enable InSMM_STS (EISS) */
> +               bios_cntl |= 1;         /* Write Protect Disable (WPD) */
> +               ich_writeb(bios_cntl, &ich9_spi->bcr);

Basically the register bit layout is the same as the non-sbase
controller, only the register address is differnt (0xFC vs. 0xDC).
Again we can use DT to pass this to the driver.

> +       } else {
> +               pci_read_config_byte(ctlr.dev, 0xdc, &bios_cntl);
> +               if (ctlr.ich_version == 9)
> +                       bios_cntl &= ~(1 << 5);
> +               pci_write_config_byte(ctlr.dev, 0xdc, bios_cntl | 0x1);
> +       }
>  }
>
>  int spi_claim_bus(struct spi_slave *slave)
> diff --git a/drivers/spi/ich.h b/drivers/spi/ich.h
> index d2e4b85..1419b23 100644
> --- a/drivers/spi/ich.h
> +++ b/drivers/spi/ich.h
> @@ -37,18 +37,19 @@ struct ich9_spi_regs {
>         uint8_t opmenu[8];              /* 0x98 */
>         uint32_t bbar;
>         uint8_t _reserved3[12];
> -       uint32_t fdoc;
> +       uint32_t fdoc;                  /* 0xb0 */
>         uint32_t fdod;
>         uint8_t _reserved4[8];
> -       uint32_t afc;
> +       uint32_t afc;                   /* 0xc0 */
>         uint32_t lvscc;
>         uint32_t uvscc;
>         uint8_t _reserved5[4];
> -       uint32_t fpb;
> +       uint32_t fpb;                   /* 0xd0 */
>         uint8_t _reserved6[28];
> -       uint32_t srdl;
> +       uint32_t srdl;                  /* 0xf0 */
>         uint32_t srdc;
> -       uint32_t srd;
> +       uint32_t scs;
> +       uint32_t bcr;
>  } __packed;
>
>  enum {
> --

Regards,
Bin

[U-Boot] [PATCH 23/23] x86: Add support for Intel Minnowboard Max

[Bin Meng]

Hi Simon,

On Tue, Jan 27, 2015 at 9:23 AM, Simon Glass <sjg@chromium.org> wrote:
> This is a relatively low-cost x86 board in a small form factor. The main
> peripherals are uSD, USB, HDMI, Ethernet and SATA. It uses an Atom 3800
> series CPU. So far only the dual core 2GB variant is supported.
>
> This uses the existing FSP support. Binary blobs are required to make this
> board work. The microcode update is included as a patch (all 3000 lines of
> it).
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> ---
>
>  arch/x86/Kconfig                                 |   12 +
>  arch/x86/cpu/Makefile                            |    1 +
>  arch/x86/cpu/baytrail/Kconfig                    |    9 +
>  arch/x86/cpu/baytrail/Makefile                   |   10 +
>  arch/x86/cpu/baytrail/early_uart.c               |   82 +
>  arch/x86/cpu/baytrail/fsp_configs.c              |  156 +
>  arch/x86/cpu/baytrail/pci.c                      |   47 +
>  arch/x86/cpu/baytrail/valleyview.c               |   37 +
>  arch/x86/dts/Makefile                            |    3 +-
>  arch/x86/dts/microcode/m0130673322.dtsi          | 3284 ++++++++++++++++++++++
>  arch/x86/dts/minnowmax.dts                       |   45 +
>  arch/x86/dts/serial.dtsi                         |    2 +-
>  arch/x86/include/asm/arch-baytrail/fsp/azalia.h  |   39 +
>  arch/x86/include/asm/arch-baytrail/fsp/fsp_vpd.h |   95 +
>  arch/x86/include/asm/arch-baytrail/gpio.h        |   13 +
>  board/intel/minnowmax/Kconfig                    |   31 +
>  board/intel/minnowmax/MAINTAINERS                |    6 +
>  board/intel/minnowmax/Makefile                   |    7 +
>  board/intel/minnowmax/minnowmax.c                |   32 +
>  board/intel/minnowmax/start.S                    |    9 +
>  configs/minnowmax_defconfig                      |   13 +
>  doc/README.x86                                   |   49 +-
>  include/configs/minnowmax.h                      |   69 +
>  23 files changed, 4043 insertions(+), 8 deletions(-)
>  create mode 100644 arch/x86/cpu/baytrail/Kconfig
>  create mode 100644 arch/x86/cpu/baytrail/Makefile
>  create mode 100644 arch/x86/cpu/baytrail/early_uart.c
>  create mode 100644 arch/x86/cpu/baytrail/fsp_configs.c
>  create mode 100644 arch/x86/cpu/baytrail/pci.c
>  create mode 100644 arch/x86/cpu/baytrail/valleyview.c
>  create mode 100644 arch/x86/dts/microcode/m0130673322.dtsi
>  create mode 100644 arch/x86/dts/minnowmax.dts
>  create mode 100644 arch/x86/include/asm/arch-baytrail/fsp/azalia.h
>  create mode 100644 arch/x86/include/asm/arch-baytrail/fsp/fsp_vpd.h
>  create mode 100644 arch/x86/include/asm/arch-baytrail/gpio.h
>  create mode 100644 board/intel/minnowmax/Kconfig
>  create mode 100644 board/intel/minnowmax/MAINTAINERS
>  create mode 100644 board/intel/minnowmax/Makefile
>  create mode 100644 board/intel/minnowmax/minnowmax.c
>  create mode 100644 board/intel/minnowmax/start.S
>  create mode 100644 configs/minnowmax_defconfig
>  create mode 100644 include/configs/minnowmax.h
>
> diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
> index 73a7392..49bd76f 100644
> --- a/arch/x86/Kconfig
> +++ b/arch/x86/Kconfig
> @@ -41,6 +41,14 @@ config TARGET_CROWNBAY
>           Intel Platform Controller Hub EG20T, other system components and
>           peripheral connectors for PCIe/SATA/USB/LAN/SD/UART/Audio/LVDS.
>
> +config TARGET_MINNOWMAX
> +       bool "Support Intel Minnowboard MAX"
> +       help
> +         This is the Intel Minnowboard MAX. It contains an Atom E3800
> +         processor in a small form factor with Ethernet, micro-SD, USB 2,
> +         USB 3, SATA, serial console, some GPIOs and HDMI 1.3 video out.
> +         It requires some binary blobs - see README.x86 for details.
> +
>  endchoice
>
>  config RAMBASE
> @@ -388,12 +396,16 @@ source "arch/x86/cpu/ivybridge/Kconfig"
>
>  source "arch/x86/cpu/queensbay/Kconfig"
>
> +source "arch/x86/cpu/baytrail/Kconfig"
> +

I wonder if we need put this before queensbay, per alphabetical order?

>  source "board/coreboot/coreboot/Kconfig"
>
>  source "board/google/chromebook_link/Kconfig"
>
>  source "board/intel/crownbay/Kconfig"
>
> +source "board/intel/minnowmax/Kconfig"
> +
>  config MMCONF_BASE_ADDRESS
>         hex
>          default 0xe0000000
> diff --git a/arch/x86/cpu/Makefile b/arch/x86/cpu/Makefile
> index 62e43c0..5acf8bb 100644
> --- a/arch/x86/cpu/Makefile
> +++ b/arch/x86/cpu/Makefile
> @@ -12,6 +12,7 @@ extra-y       = start.o
>  obj-$(CONFIG_X86_RESET_VECTOR) += resetvec.o start16.o
>  obj-y  += interrupts.o cpu.o call64.o
>
> +obj-$(CONFIG_INTEL_BAYTRAIL) += baytrail/
>  obj-$(CONFIG_SYS_COREBOOT) += coreboot/
>  obj-$(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE) += ivybridge/
>  obj-$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE) += ivybridge/
> diff --git a/arch/x86/cpu/baytrail/Kconfig b/arch/x86/cpu/baytrail/Kconfig
> new file mode 100644
> index 0000000..e86cc01
> --- /dev/null
> +++ b/arch/x86/cpu/baytrail/Kconfig
> @@ -0,0 +1,9 @@
> +#
> +# Copyright (C) 2015 Google, Inc
> +#
> +# SPDX-License-Identifier:     GPL-2.0+
> +#
> +
> +config INTEL_BAYTRAIL
> +       bool
> +       select HAVE_FSP
> diff --git a/arch/x86/cpu/baytrail/Makefile b/arch/x86/cpu/baytrail/Makefile
> new file mode 100644
> index 0000000..8914e8b
> --- /dev/null
> +++ b/arch/x86/cpu/baytrail/Makefile
> @@ -0,0 +1,10 @@
> +#
> +# Copyright (C) 2015 Google, Inc
> +#
> +# SPDX-License-Identifier:     GPL-2.0+
> +#
> +
> +obj-y += early_uart.o
> +obj-y += fsp_configs.o
> +obj-y += pci.o
> +obj-y += valleyview.o
> diff --git a/arch/x86/cpu/baytrail/early_uart.c b/arch/x86/cpu/baytrail/early_uart.c
> new file mode 100644
> index 0000000..c54deb9
> --- /dev/null
> +++ b/arch/x86/cpu/baytrail/early_uart.c
> @@ -0,0 +1,82 @@
> +/*
> + * Copyright (C) 2015 Google, Inc
> + *
> + * SPDX-License-Identifier:    GPL-2.0+
> + */
> +
> +#include <common.h>
> +#include <debug_uart.h>
> +#include <errno.h>
> +#include <asm/io.h>
> +
> +#define PCI_DEV_CONFIG(segbus, dev, fn) ( \
> +               (((segbus) & 0xfff) << 20) | \
> +               (((dev) & 0x1f) << 15) | \
> +               (((fn)  & 0x07) << 12))
> +
> +/* Platform Controller Unit */
> +#define LPC_DEV                        0x1f
> +#define LPC_FUNC               0
> +
> +/* Enable UART */
> +#define UART_CONT              0x80
> +
> +/* SCORE Pad definitions */
> +#define UART_RXD_PAD                   82
> +#define UART_TXD_PAD                   83
> +
> +/* Pad base: PAD_CONF0[n]= PAD_BASE + 16 * n */
> +#define GPSCORE_PAD_BASE       (IO_BASE_ADDRESS + IO_BASE_OFFSET_GPSCORE)
> +
> +/* IO Memory */
> +#define IO_BASE_ADDRESS                        0xfed0c000
> +#define  IO_BASE_OFFSET_GPSCORE                0x0000
> +#define  IO_BASE_OFFSET_GPNCORE                0x1000
> +#define  IO_BASE_OFFSET_GPSSUS         0x2000
> +#define IO_BASE_SIZE                   0x4000
> +
> +static inline unsigned int score_pconf0(int pad_num)
> +{
> +       return GPSCORE_PAD_BASE + pad_num * 16;
> +}
> +
> +static void score_select_func(int pad, int func)
> +{
> +       uint32_t reg;
> +       uint32_t pconf0_addr = score_pconf0(pad);
> +
> +       reg = readl(pconf0_addr);
> +       reg &= ~0x7;
> +       reg |= func & 0x7;
> +       writel(reg, pconf0_addr);
> +}
> +
> +static void pci_write_config32(int dev, unsigned int where, u32 value)
> +{
> +       unsigned long addr;
> +
> +       addr = CONFIG_MMCONF_BASE_ADDRESS | dev | (where & ~3);
> +       writel(value, addr);
> +}

I don't see where CONFIG_MMCONF_BASE_ADDRESS value is programmed into
the chipset. There has to be a register to enable the PCIe ECAM. Is
this programmed by FSP's temp_ram_init()? If yes, then we need
document this somewhere (in BayTrail Kconfig help?)

> +
> +/* This can be called after memory-mapped PCI is working */
> +int setup_early_uart(void)
> +{
> +       if (!IS_ENABLED(CONFIG_DEBUG_UART))
> +               return -ENOSYS;
> +

setup_early_uart() is called only when CONFIG_DEBUG_UART is defined,
so there is no need to check this.

> +       /* Enable the legacy UART hardware. */
> +       pci_write_config32(PCI_DEV_CONFIG(0, LPC_DEV, LPC_FUNC), UART_CONT, 1);
> +
> +       /*
> +        * Set up the pads to the UART function. This allows the signals to
> +        * leave the chip
> +        */
> +       score_select_func(UART_RXD_PAD, 1);
> +       score_select_func(UART_TXD_PAD, 1);
> +
> +       debug_uart_init();
> +       printascii("Debug UART ready\r\n");
> +
> +       return 0;
> +}
> diff --git a/arch/x86/cpu/baytrail/fsp_configs.c b/arch/x86/cpu/baytrail/fsp_configs.c
> new file mode 100644
> index 0000000..86b6926
> --- /dev/null
> +++ b/arch/x86/cpu/baytrail/fsp_configs.c
> @@ -0,0 +1,156 @@
> +/*
> + * Copyright (C) 2013, Intel Corporation
> + * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
> + *
> + * SPDX-License-Identifier:    Intel
> + */
> +
> +#include <common.h>
> +#include <asm/arch/fsp/azalia.h>
> +#include <asm/fsp/fsp_support.h>
> +
> +/* ALC262 Verb Table - 10EC0262 */
> +static const uint32_t verb_table_data13[] = {
> +       /* Pin Complex (NID 0x11) */
> +       0x01171cf0,
> +       0x01171d11,
> +       0x01171e11,
> +       0x01171f41,
> +       /* Pin Complex (NID 0x12) */
> +       0x01271cf0,
> +       0x01271d11,
> +       0x01271e11,
> +       0x01271f41,
> +       /* Pin Complex (NID 0x14) */
> +       0x01471c10,
> +       0x01471d40,
> +       0x01471e01,
> +       0x01471f01,
> +       /* Pin Complex (NID 0x15) */
> +       0x01571cf0,
> +       0x01571d11,
> +       0x01571e11,
> +       0x01571f41,
> +       /* Pin Complex (NID 0x16) */
> +       0x01671cf0,
> +       0x01671d11,
> +       0x01671e11,
> +       0x01671f41,
> +       /* Pin Complex (NID 0x18) */
> +       0x01871c20,
> +       0x01871d98,
> +       0x01871ea1,
> +       0x01871f01,
> +       /* Pin Complex (NID 0x19) */
> +       0x01971c21,
> +       0x01971d98,
> +       0x01971ea1,
> +       0x01971f02,
> +       /* Pin Complex (NID 0x1A) */
> +       0x01a71c2f,
> +       0x01a71d30,
> +       0x01a71e81,
> +       0x01a71f01,
> +       /* Pin Complex */
> +       0x01b71c1f,
> +       0x01b71d40,
> +       0x01b71e21,
> +       0x01b71f02,
> +       /* Pin Complex */
> +       0x01c71cf0,
> +       0x01c71d11,
> +       0x01c71e11,
> +       0x01c71f41,
> +       /* Pin Complex */
> +       0x01d71c01,
> +       0x01d71dc6,
> +       0x01d71e14,
> +       0x01d71f40,
> +       /* Pin Complex */
> +       0x01e71cf0,
> +       0x01e71d11,
> +       0x01e71e11,
> +       0x01e71f41,
> +       /* Pin Complex */
> +       0x01f71cf0,
> +       0x01f71d11,
> +       0x01f71e11,
> +       0x01f71f41,
> +};
> +
> +/*
> + * This needs to be in ROM since if we put it in CAR, FSP init loses it when
> + * it drops CAR.
> + *
> + * TODO(sjg at chromium.org): Move to device tree when FSP allows it
> + *
> + * VerbTable: (RealTek ALC262)
> + * Revision ID = 0xFF, support all steps
> + * Codec Verb Table For AZALIA
> + * Codec Address: CAd value (0/1/2)
> + * Codec Vendor: 0x10EC0262
> + */
> +static const struct pch_azalia_verb_table azalia_verb_table[] = {
> +       {
> +               {
> +                       0x10ec0262,
> +                       0x0000,
> +                       0xff,
> +                       0x01,
> +                       0x000b,
> +                       0x0002,
> +               },
> +               verb_table_data13
> +       }
> +};
> +
> +const struct pch_azalia_config azalia_config = {
> +       .pme_enable = 1,
> +       .docking_supported = 1,
> +       .docking_attached = 0,
> +       .hdmi_codec_enable = 1,
> +       .azalia_v_ci_enable = 1,
> +       .rsvdbits = 0,
> +       .azalia_verb_table_num = 1,
> +       .azalia_verb_table = azalia_verb_table,
> +       .reset_wait_timer_us = 300
> +};
> +
> +void update_fsp_upd(struct upd_region *fsp_upd)
> +{
> +       struct memory_down_data *mem;
> +
> +       /*
> +        * Configure everything here to avoid the poor hard-pressed user
> +        * needing to run Intel's binary configuration tool. It may also allow
> +        * us to support the 1GB single core variant easily.
> +        *
> +        * TODO(sjg at chromium.org): Move to device tree
> +        */
> +       fsp_upd->mrc_init_tseg_size = 8;
> +       fsp_upd->mrc_init_mmio_size = 0x800;
> +       fsp_upd->emmc_boot_mode = 0xff;
> +       fsp_upd->enable_sdio = 1;
> +       fsp_upd->enable_sdcard = 1;
> +       fsp_upd->enable_hsuart0 = 1;
> +       fsp_upd->azalia_config_ptr = (uint32_t)&azalia_config;
> +       fsp_upd->enable_i2_c0 = 0;
> +       fsp_upd->enable_i2_c2 = 0;
> +       fsp_upd->enable_i2_c3 = 0;
> +       fsp_upd->enable_i2_c4 = 0;
> +       fsp_upd->enable_xhci = 0;
> +       fsp_upd->igd_render_standby = 1;
> +
> +       mem = &fsp_upd->memory_params;
> +       mem->enable_memory_down = 1;
> +       mem->dram_speed = 1;
> +       mem->dimm_width = 1;
> +       mem->dimm_density = 2;
> +       mem->dimm_tcl = 0xb;
> +       mem->dimm_trpt_rcd = 0xb;
> +       mem->dimm_twr = 0xc;
> +       mem->dimm_twtr = 6;
> +       mem->dimm_trrd = 6;
> +       mem->dimm_trtp = 6;
> +       mem->dimm_tfaw = 0x14;
> +}
> diff --git a/arch/x86/cpu/baytrail/pci.c b/arch/x86/cpu/baytrail/pci.c
> new file mode 100644
> index 0000000..7032c97
> --- /dev/null
> +++ b/arch/x86/cpu/baytrail/pci.c
> @@ -0,0 +1,47 @@
> +/*
> + * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
> + *
> + * SPDX-License-Identifier:    GPL-2.0+
> + */
> +
> +#include <common.h>
> +#include <debug_uart.h>
> +#include <pci.h>
> +#include <asm/pci.h>
> +#include <asm/fsp/fsp_support.h>
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +void board_pci_setup_hose(struct pci_controller *hose)
> +{
> +       hose->first_busno = 0;
> +       hose->last_busno = 0;
> +
> +       /* PCI memory space */
> +       pci_set_region(hose->regions + 0,
> +                      CONFIG_PCI_MEM_BUS,
> +                      CONFIG_PCI_MEM_PHYS,
> +                      CONFIG_PCI_MEM_SIZE,
> +                      PCI_REGION_MEM);
> +
> +       /* PCI IO space */
> +       pci_set_region(hose->regions + 1,
> +                      CONFIG_PCI_IO_BUS,
> +                      CONFIG_PCI_IO_PHYS,
> +                      CONFIG_PCI_IO_SIZE,
> +                      PCI_REGION_IO);
> +
> +       pci_set_region(hose->regions + 2,
> +                      CONFIG_PCI_PREF_BUS,
> +                      CONFIG_PCI_PREF_PHYS,
> +                      CONFIG_PCI_PREF_SIZE,
> +                      PCI_REGION_PREFETCH);
> +
> +       pci_set_region(hose->regions + 3,
> +                      0,
> +                      0,
> +                      gd->ram_size,
> +                      PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
> +
> +       hose->region_count = 4;
> +}
> diff --git a/arch/x86/cpu/baytrail/valleyview.c b/arch/x86/cpu/baytrail/valleyview.c
> new file mode 100644
> index 0000000..ab89b54
> --- /dev/null
> +++ b/arch/x86/cpu/baytrail/valleyview.c
> @@ -0,0 +1,37 @@
> +/*
> + * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
> + *
> + * SPDX-License-Identifier:    GPL-2.0+
> + */
> +
> +#include <common.h>
> +#include <pci_ids.h>
> +#include <asm/post.h>
> +
> +static struct pci_device_id mmc_supported[] = {
> +       { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_VALLEYVIEW_SDIO },
> +       { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_VALLEYVIEW_SDCARD },
> +};
> +
> +int cpu_mmc_init(bd_t *bis)
> +{
> +       printf("mmc init\n");
> +       return fsp_cpu_mmc_init("ValleyView SDHCI", mmc_supported,
> +                               ARRAY_SIZE(mmc_supported));
> +}
> +
> +int arch_cpu_init(void)
> +{
> +       int ret;
> +
> +       post_code(POST_CPU_INIT);
> +#ifdef CONFIG_SYS_X86_TSC_TIMER
> +       timer_set_base(rdtsc());
> +#endif
> +
> +       ret = x86_cpu_init_f();
> +       if (ret)
> +               return ret;
> +
> +       return 0;
> +}
> diff --git a/arch/x86/dts/Makefile b/arch/x86/dts/Makefile
> index 97ed884..4e0171a 100644
> --- a/arch/x86/dts/Makefile
> +++ b/arch/x86/dts/Makefile
> @@ -1,5 +1,6 @@
>  dtb-y += chromebook_link.dtb \
> -       crownbay.dtb
> +       crownbay.dtb \
> +       minnowmax.dtb
>
>  targets += $(dtb-y)
>
> diff --git a/arch/x86/dts/microcode/m0130673322.dtsi b/arch/x86/dts/microcode/m0130673322.dtsi
> new file mode 100644
> index 0000000..90bf2fb
> --- /dev/null
> +++ b/arch/x86/dts/microcode/m0130673322.dtsi
> @@ -0,0 +1,3284 @@
> +/*
> + * ---
> + * This is a device tree fragment. Use #include to add these properties to a
> + * node.
> + *
> + * Date:
> + */
> +
> +compatible = "intel,microcode";
> +intel,header-version = <1>;
> +intel,update-revision = <0x322>;
> +intel,date-code = <0x4012014>;
> +intel,processor-signature = <0x30673>;
> +intel,checksum = <0x17b0d914>;
> +intel,loader-revision = <1>;
> +intel,processor-flags = <0x1>;
> +
> +/* The first 48-bytes are the public header which repeats the above data */
> +data = <
> +       0x01000000      0x22030000      0x14200104      0x73060300
> +       0x14d9b017      0x01000000      0x01000000      0xd0cb0000
> +       0x00cc0000      0x00000000      0x00000000      0x00000000
> +       0x00000000      0xa1000000      0x01000200      0x22030000
> +       0x00000000      0x00000000      0x31031420      0x11320000
> +       0x01000000      0x73060300      0x00000000      0x00000000
> +       0x00000000      0x00000000      0x00000000      0x00000000
> +       0x00000000      0xf4320000      0x00000000      0x00000000
> +       0x00000000      0x00000000      0x00000000      0x00000000
> +       0x0ae10178      0x7c98f9d1      0x41962d85      0x19391270
> +       0xcf3c0336      0xc1f13d6f      0xe46abaf6      0x3b65ca6b
> +       0xdb666815      0x5a17bfc4      0x4fca009d      0x099ae8b3
> +       0x198e2c7d      0x7c665bbf      0xc07a1a7a      0x7dbcee26
> +       0x867296b2      0xc885b6ce      0xe602baff      0x68544b14
> +       0xc928c400      0x3add156d      0x531946f9      0x92a03216
> +       0xda352322      0xd967ee1f      0x3c5170a7      0xf6de834e
> +       0x5a2ed8b3      0x9fb8f050      0x450de17f      0xfd5ef070
> +       0x4954575f      0xa3a071ab      0xb56e2afb      0xe2b48302
> +       0x6655a958      0x57c9a438      0x1b2f688a      0x09309bc4
> +       0x0be95612      0x529c1633      0xc48515d9      0x29eb78df
> +       0x9933409f      0xda58dea9      0x58c805fd      0xbc110f5a
> +       0x40780ec0      0x6ad59bb3      0xc7387fb8      0x591c1490
> +       0xf9335932      0x32130e0b      0xef4b3c96      0xacd903f2
> +       0x5b362539      0xe7f85529      0xcb17c41f      0xe7e440d8
> +       0xfaf7e925      0x969b76fb      0x5edab8c7      0xf00012e8
> +       0x121c2971      0xe5b18959      0xadfd07c0      0x1f09c9d7
> +       0x9781006a      0x39550073      0x6c438b6d      0x436f60bc
> +       0x11000000      0x8514b971      0x40df7b4a      0x6a6b7285
> +       0x7978ef59      0x319bddf5      0x04c68e5a      0xe1c28b10
> +       0x172f63dc      0x306fb95d      0x31d881e8      0x69f8e08d
> +       0x617a99e1      0x1ab6b574      0x2951fa5b      0xcc7e3e94
> +       0xff379d19      0x5c035dec      0xe28ed726      0x22b8a5ac
> +       0xd08b3ac5      0x45c03b9e      0xcea4083c      0xc26758aa
> +       0xbe7cf81e      0x43d898f3      0x5c45a635      0xc9cac095
> +       0xb89aea20      0x2c02b40e      0xe3a8b48d      0xeabfb60e
> +       0x776ed2a9      0x080ae6d5      0x7f64b1df      0x00e40ee6
> +       0x0f1c10f4      0x792e5423      0x787f5459      0x63a8b02c
> +       0x3fd6a255      0x049cae26      0x0949f5ff      0x9aebb236
> +       0xecc01775      0x91b57b84      0xe0e45ea3      0x5a8bf79e
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> +       0x9f314e1b      0x248a5272      0xa40b8424      0xe42af07a
> +       0xa180f331      0x904f3c05      0x98455bc5      0x46198ed7
> +       0x03e208e5      0xcf670099      0x7a85b08c      0xba921ae2
> +       0x1e6947d0      0xddffa6ec      0xea6330d3      0xcda6957e
> +       0x19525cd3      0x311fb407      0x796c1ff4      0x3a2760fb
> +       0xde4bdd71      0xdb289b69      0x9811773c      0xa72cd839
> +       0x03da90de      0xd42912e8      0x8da1fb0a      0x985d4132
> +       0x5890ae40      0x1f7724d0      0xa336824f      0xca19df32
> +       0xf8ac73d1      0x61c370a9      0xe152b073      0xdafc6461
> +       0x23672042      0x9e6982b6      0x1256c6b4      0xe6bf2c9c
> +       0x9dae123e      0x30896b8f      0x99acf3a3      0xaa05d384
> +       0xea3b7bb7      0xe711d473      0xa9053351      0x71a85cb4
> +       0x3a0f5d25      0x2db3cb48      0x86314a6e      0xf7a2265b
> +       0xf7dc1cc3      0x548f56cf      0x4028a1ee      0x7d2e25d5
> +       0x68c87e37      0xbced6b8c      0x536cc252      0x68bab5ca
> +       0x1158c6c5      0xae0e9509      0x66fa6885      0x22bf2b9a
> +       0xa7a60a97      0x18f4f609      0x348623eb      0x773e705f
> +       0xb3d6622f      0x8f348186      0x81cb9856      0x64bf21ba
> +       0x47e1f96d      0xc95a5843      0xeff6cfce      0x08cb092c
> +       0xf214e48d      0xce272fec      0x57bf90df      0x3c425ea8
> +       0x856e1f5e      0x5c21d1b6      0x105488a3      0x553971eb
> +       0xde614ee5      0xdfa3ac81      0xc5eca5b1      0x69d02d23
> +       0x2a0fefb7      0xf9a01854      0xdd99f277      0x75014d7d
> +       0x3830e3dd      0x7dd8f1e7      0xdac5ac92      0xbf57c03a
> +       0xa5e6a6c7      0xb7c1b7a9      0xc8c8405e      0xfd1977da
> +       0x1e6a7ca4      0x299e1025      0x651a0e55      0x53d624a7
> +       0xccc9e861      0x901bce45      0x1de5a1ab      0x6140dcef
> +       0x3e09eafb      0x20c63cd0      0xff642faa      0xbc91a0a7
> +       0xe373e111      0x857236e7      0xe3e61037      0x0b6cc497
> +       0xca1da7e6      0x60e53803      0xb68663db      0x42e9956a
> +       0xbf4a1650      0xb43f25ec      0xc1232a3a      0x283c2ff3
> +       0xcd233183      0x17ccdfc0      0x03ac3e6d      0xa68ced48
> +       0xe38217d5      0x03c6472d      0x6a623afc      0xfce0d117
> +       0x448ee829      0x0909efd4      0x843a3b4a      0x9ad07683
> +       0x2250af2a      0x01ecc053      0x29684919      0x4ee0c62e
> +       0xa326a904      0x3ec83943      0xc42b0663      0x966379b2
> +       0xc672ece4      0x39391ad3      0x689a10f9      0xd3e9cbd6
> +       0x4bfa8446      0xd1ef6375      0xfe01b6a9      0xbda7d01a
> +       0x1e6879bf      0x05bdf46e      0x14ccab04      0xb02ae668
> +       0x58b51752      0x5eb8e83c      0x753d99de      0x87e4235b
> +       0x80b2afe7      0x127439fe      0x127a98a4      0xe5934c92
> +       0x86044bc0      0xa9664abb      0x91365b53      0x35b14bda
> +       0x67755842      0x7239651a      0x49e0b2e6      0xbb1d25fe
> +       0x51ca7213      0xaff2fd82      0xc1223aba      0x02941bcf
> +       0xb6ec2cfe      0xaa817dc0      0xe0475250      0x78098112
> +       0x750ae102      0x0b3135fa      0x23b648d4      0xbc9d78bd
> +       0xc5d7e046      0xe90ef47c      0x7f21eb75      0xdb304b0b
> +       0xa2c12ee2      0xb45e62ed      0x9f50feb6      0xe036ff55
> +       0x422f410b      0x2385de45      0xb37df6a5      0x4c2abf10
> +       0x6a2c7370      0xf35197ac      0x381face9      0x694761c6
> +       0xb2275097      0x208824c7      0x945300a0      0x4ad3f83d
> +       0x38a7aa12      0x00daaf41      0xcd4b2c19      0x25b2e8f7
> +       0x60d3e39b      0xb3dd8220      0x152f86ab      0xd1ec4233
> +       0x1c3df78a      0x5aeac74e      0xdeea2fe3      0xcfcf9b2e
> +       0x6efc8b2a      0x12a8c5c3      0xb56384e4      0x1b1fe549
> +       0xc55acb4d      0x78e7306a      0x733b0f70      0xf4afe6be
> +       0x6d904b03      0x7ddd7862      0x4da02602      0xfce1e904
> +       0x78773a4b      0x9083e908      0xda8a7593      0xafd8776e
> +       0x9e5ae37a      0xd6e7c557      0xad27adaa      0xd0f1a995
> +       0x1c84e046      0x3319b21a      0xd24c0d03      0x1789df77
> +       0x0f02b9ff      0xdb911f76      0xb2df7654      0x2e75a7bd
> +       0x8acc6fd3      0x3c16ec0b      0xe0d7ac22      0x3ddd1ce1
> +       0xfa9ec67a      0x48f2c409      0xf8099606      0xd73a459d
> +       0x9b2b3fa5      0x8e3c3e9c      0x8b99286a      0x006c0e07
> +       0xc299ded3      0x8a2bd400      0x74508dd4      0x609b4afc
> +       0x1a532838      0xb352a629      0xd390d8af      0x440a5798
> +       0xd31f6ad5      0x161aa48e      0x24a4359f      0xf39f49f7
> +       0xff160d2a      0x27a24637      0x84c46d40      0x988d026a
> +       0x5697a68f      0xeae970a0      0x42689e3d      0xc84ee62f
> +       0x764aabd5      0xb6d74ba5      0x8efc05a6      0xf2d0eccb
> +       0x2b4fa41c      0xad24799f      0xf73b8353      0x76bcd448
> +       0x08172d5e      0x5c6be301      0x926ffdd6      0xfa31009f
> +       0x8339c5f9      0x9dde2840      0x00c2d730      0x6402335f
> +       0xf6f84eda      0x5b0e628a      0x140dbafb      0x0533ee67
> +       0xa7523e60      0x20ca14b3      0x1145d280      0xb0c0ba41
> +       0x81f174d1      0xb80fc64e      0xe8321cfe      0x5762e501
> +       0x9e266b75      0x2695a738      0xe3104779      0x1d1ea19e
> +       0x15fd1d53      0xf0fbd4ee      0xc82f4552      0x4ea98e23
> +       0xec892d69      0x66ccadeb      0x2fdf99b4      0xafffec15
> +       0x2de5ee13      0x5e6ead7f      0x20b111cd      0x752254d1
> +       0xc0126f43      0xe2695fd8      0x38651d40      0x15b708ce
> +       0xf2c2ffdc      0xec24c68c      0x04351ddc      0xceac029b
> +       0x0525fc89      0x90e28526      0x0a23a4c2      0xbb33a5c4
> +       0x13f1fc38      0x66d79cd9      0x0acabe80      0x8d4ef5d8
> +       0x4091808e      0x02f7150b      0xf550597e      0x52703c3f
> +       0xfc954b68      0xe9ebaccb      0xd4f35b2a      0x93793446
> +       0xc40799e6      0xa963fc0c      0x92c8d8f1      0xbc8218dc
> +       0x9ec5c30a      0x8a6a2217      0x63d13dfe      0xea664e1e
> +       0x487192a7      0x1c8f8610      0x88e20f93      0xc54a6de3
> +       0x0111ae79      0x1335f02e      0xa2e2d37d      0xc2563697
> +       0x5fffcdec      0x233919ab      0x3bab1329      0x61943e99
> +       0xea7940f7      0x3cc62cf4      0xaedc5bc4      0x41b63f2c
> +       0x6dbf285f      0xb4793534      0x0e1013f2      0xc54d8c2d
> +       0x23c587f7      0x75df0092      0xc055254a      0x55db2c71
> +       0x518eaa5b      0x55c810d6      0x9c44ca37      0x034287ea
> +       0xe06a0567      0x221a0d8c      0x037a9164      0x36693ef9
> +       0xb7d270a6      0xa8d84a63      0xe8862970      0x484077b7
> +       0xab426cb7      0x37db7c9e      0xb34e1752      0x35444958
> +       0x00d48e90      0x8142602d      0x8ca28e2c      0x714598c9
> +       0xb1cce1be      0xbb98db74      0x400e1029      0x330cb2b6
> +       0x1fd3f8ce      0x2abf7516      0xc2d07e5c      0x2b1d2b80
> +       0xf06bd895      0x2fa7bc09      0xbdbdf893      0xd8466f85
> +       0x61e551b0      0x5b99bfb8      0x86ea5ee7      0xfd82ff9a
> +       0xd7c6344a      0x1fa144d8      0x650f0f02      0x71bd73cf
> +       0x2825177d      0x56c76399      0x2e0b873e      0xc3bf939d
> +       0xf8bc3c1b      0x468482e7      0x33cb98a7      0xa679eaf4
> +       0x32ba9b49      0xde86d50c      0x9eeeeee5      0x94a306e5
> +       0x432e1c9c      0x37997d0c      0xa84d981f      0xbe07b56d
> +       0x4ab6d465      0xa3cd92c4      0x5dea82ab      0xf771249d
> +       0x78f87ba5      0x8105df1c      0x3d74e1c1      0xf48cd4c1
> +       0x8ad010e1      0x9e9a2758      0x509c8953      0xeaaed79a
> +       0x97a4ecb7      0x23ffceb0      0xb3e42e61      0x5f41b4eb
> +       0x14d2804c      0x2d635ad3      0xe1314781      0x3921ec18
> +       0x3dbebec3      0x94e0df22      0xb0b4724e      0x0e7f986b
> +       0x83dd7694      0x7041a22e      0x3c942757      0xd6ff5cbb
> +       0x048b0426      0xa5d6c4cb      0x1f4e3bbd      0x78d5924e
> +       0x6a857d77      0x1d115ecc      0x73c6a888      0xefb934ee
> +       0xa7d1702b      0x6794a668      0x03715b90      0xfbab19f9
> +       0xd5a433df      0x12f4d421      0x40519650      0x636a093e
> +       0x1601be15      0xe0fbef6f      0x79d775bc      0x789c3a30
> +       0x4d9fa618      0xedf8fa70      0xb0fa402d      0x692ee91b
> +       0x5a593e5c      0x0fa3667f      0x3f51a636      0x935e28c7
> +       0x230b725a      0x4929bc83      0x76de40ad      0x2d9a5f7f
> +       0x8799e033      0xbf2700b0      0x5220159d      0x1ed71ca5
> +       0xcc66f114      0x15fd868d      0x4236645a      0xded2558e
> +       0xa561cc0d      0x02822e5b      0xd0177f80      0xf09badd9
> +       0xd5380ae3      0xcfc11a46      0x36713416      0x7f3d60cc
> +       0x4018797e      0xc6b23941      0xcb5a4861      0x614ce6df
> +       0xabfc0629      0xa519bcfc      0x911f04f0      0xe509b546
> +       0xbb411eb9      0x9e6b921c      0xbf0b1c70      0x80c2901c
> +       0x85786713      0xad2aafec      0x62711ba7      0x6edb4971
> +       0x214eb137      0x45b1b313      0x6742d5e9      0x7daf37a6
> +       0x21d6a27a      0x059424f7      0x2c8c3dfb      0xe7a06c77
> +       0x10815625      0xb4dc69e8      0x52767f66      0x44d48738
> +       0x84d26c93      0x09008893      0xfc21394a      0x82155a72
> +       0xc4fd7512      0x6d43cd2f      0xcae99e08      0x453175ae
> +       0xc6ee93a3      0x2fed0eac      0xe48fb73d      0x0afe2d2a
> +       0x5966735e      0xdc7e5fb6      0xed1ef13d      0x7e08a106
> +       0xd3ca0e6b      0x4ce5ca02      0xa0beebed      0xe982c609
> +       0x1ee9e5a2      0x24ae26cb      0xfd4c08d4      0x5e85e850
> +       0x11b54b3b      0x87209692      0x4a5b0c35      0xcd25dd6f
> +       0xd9570253      0xaad0b9fe      0xaf984fee      0x6cf7ae2d
> +       0x45d9926c      0x07a66ac6      0x8e7aacdc      0xaf587d66
> +       0x53972a4e      0x8da4a6c9      0x2bc311e5      0x36938ae8
> +       0x179b965d      0x515743f7      0xb5bbbdcd      0xd8602715
> +       0x9e43049f      0x4e78a080      0xba3f1750      0x68635cf0
> +       0x85823047      0xbb03b5fd      0xb0d747c8      0x58d214af
> +       0x94b1ba85      0x6d2cf8ac      0x2bc1faeb      0x6bd7c1e3
> +       0x127658e9      0x8b499020      0xab8f0f62      0xee665a6a
> +       0x89240e4d      0x8a95342b      0x00b38ccc      0xe6b14d9d
> +       0x32a2af71      0x4c9ecb69      0xc8de2685      0xd7385184
> +       0x8e943872      0x809b2c79      0x108511da      0x08b4f54d
> +       0x95f52442      0x26fe296f      0xf7e037c0      0xa1aecdd3
> +       0x89774a91      0xde67c55f      0x1f9816dc      0x1469a4c2
> +       0x28240be2      0x5fd0ad14      0x0949db3a      0x451b94d3
> +       0x637e6d49      0x8a4771c8      0xf65104b7      0xc3058c40
> +       0x592fe4d0      0xe26129f0      0xe66e6ce9      0x26ab39b8
> +       0x308da532      0x205afe77      0x6dc78664      0x84d4890f
> +       0x9d49fcb0      0xcac8f2ed      0xe713d798      0xfed7c75b
> +       0xe441a0d4      0xdf60df37      0xc2eed2f5      0x2d68b20e
> +       0x7827c89a      0x9d4cb9f2      0xb8912cce      0x07516335
> +       0x976ffbb6      0x5cd0de48      0xed716f54      0x6f3c9f7f
> +       0x34cf42d1      0xc1027cbb      0xde67c065      0xe0a229af
> +       0xfc8bd2e8      0xd62ca176      0x8bfb76b2      0x54a1388f
> +       0xe0650bb6      0x6d60682b      0xe16cf130      0xbd7c3ca2
> +       0xea642814      0xa25f4d44      0x27013786      0x7316aa38
> +       0x571511c8      0xf1b6b789      0xb7bfe72b      0x8fd2652c
> +       0xbfc7771a      0x51a2e551      0x3bd738c2      0x2698b495
> +       0xec69a196      0xd5ecb5c4      0x9bd3224c      0x6d9ab4cf
> +       0x326c9942      0x4d711191      0xde9be50a      0xa980ca0b
> +       0xe8e59dd0      0x4439e4ae      0x35de914d      0xee499a84
> +       0xd1ca0c9d      0xfe6ee96d      0x5b1f4fd0      0xabf0621a
> +       0x0c8220c7      0xcb6dbb1e      0xa5116036      0xe858d3c3
> +       0x728e3a56      0x3b33e818      0xbe2643c1      0x497bbcc7
> +       0xeb369828      0x9a4a01be      0x8c7e72a6      0xaf052f25
> +       0x8d3ca85b      0x4703e55e      0x45647d4c      0x86d1e3e8
> +       0x40ab59f9      0x3259b195      0xf979a147      0xb8961870
> +       0x88b024f9      0x366e26bc      0xd6811525      0x252910c2
> +       0x4223a20e      0x7fc971a3      0x4a639bf3      0xb6550c3b
> +       0xfe05e552      0xbdc98897      0x509923ff      0xf51a5abc
> +       0xc6cc0891      0x61cdac05      0x03a68664      0x1b80cc76
> +       0xe18d8ee1      0x798bb4d2      0xd7769bf9      0x9ab4c02d
> +       0x7484774b      0xa9ee2c8b      0x87d34c85      0x15697682
> +       0x9f6a4a55      0x9d7a731c      0x10014d6a      0xb9798070
> +       0xd42f79cb      0x89db59b3      0xd5b0a0b6      0xf60864a5
> +       0x2d6fb084      0x1cb607b2      0x48232701      0x9310cbc6
> +       0x5bc81c98      0x6b25016c      0x2014b99d      0x0836e60b
> +       0x0addbc4c      0x3b8bac7c      0x8d95ac77      0x1d56c3c7
> +       0x58333104      0x3d6eb719      0x676eb951      0xd5c2d1a3
> +       0x239dae86      0x92181ab8      0xbdde9741      0x7995d452
> +       0xe0020661      0x2f80c8b7      0xeedcd4fc      0xe4bde175
> +       0xb98fdf78      0x84b9228f      0x78ecb4f3      0xe99e5d46
> +       0xa33b9b96      0xe2cbc71c      0xc19e2146      0xdc0ee758
> +       0x2d8f8767      0x2036685b      0x149df155      0x2e7ab376
> +       0xb13b4266      0xf5c8a3b0      0x02ca1e19      0x1badd81b
> +       0xb9c1832a      0x73b31f75      0x69979b55      0x567070a2
> +       0x2edeb3dc      0x26b55921      0x461df49f      0xc1aba883
> +       0x25d6faec      0x5260e9bf      0xa8ccdd4c      0x04291961
> +       0xfaf7a1b8      0xbc2d36e3      0xd6c86385      0x2757fbb9
> +       0x62c7107c      0x87dac461      0x0c006454      0x0e971e49
> +       0x4749afca      0x7f1fb389      0xdc0b69d3      0xc69fab09
> +       0x12c372c9      0x78480a51      0x8ab03a94      0xb37022ca
> +       0x1d00e893      0x0989de45      0x8c819503      0x8e0e1c06
> +       0x11cfef86      0x3c2386a6      0x66c0e6c8      0x1befa478
> +       0xd2e7a4a7      0x9a8b5917      0x2cfa1816      0xaf7e6c7a
> +       0xd6c9f0ff      0x1aada3e0      0xbe36a471      0x5a91f3c7
> +       0x6c61ea95      0x5246ef7c      0x20bc86c4      0xcfd87abd
> +       0xdc61f595      0x8310a684      0x0477e35c      0xe59e776f
> +       0xfa403863      0xdaf7bcb1      0xd6084825      0xb90bb047
> +       0xeb9ff684      0x7223fbca      0x6b4af987      0x6b2553f8
> +       0xdaabc6d2      0x82e2ebc3      0xa7c1c054      0x667eb0a7
> +       0x53a0c7d4      0x3fcba743      0x38170187      0x2a2e5830
> +       0xee134608      0xcd6e0112      0xac0831f9      0x9537d532
> +       0x1e176b9c      0xe3fcb69f      0x17a2eee9      0xa9e6467f
> +       0xbf6b0246      0x6a08c0fb      0x7fb943b6      0xb8f67c0e
> +       0x2b3b4ffc      0xb155d20c      0x4eb5de53      0xf078715b
> +       >;
> diff --git a/arch/x86/dts/minnowmax.dts b/arch/x86/dts/minnowmax.dts
> new file mode 100644
> index 0000000..7e15c26
> --- /dev/null
> +++ b/arch/x86/dts/minnowmax.dts
> @@ -0,0 +1,45 @@
> +/*
> + * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
> + *
> + * SPDX-License-Identifier:    GPL-2.0+
> + */
> +
> +/dts-v1/;
> +
> +/include/ "skeleton.dtsi"
> +/include/ "serial.dtsi"
> +
> +/ {
> +       model = "Intel Minnowboard Max";
> +       compatible = "intel,minnowmax", "intel,baytrail";
> +
> +       aliases {
> +               serial0 = &serial;
> +       };
> +
> +       config {
> +               silent_console = <0>;
> +       };
> +
> +       chosen {
> +               stdout-path = "/serial";
> +       };
> +
> +       spi {
> +               #address-cells = <1>;
> +               #size-cells = <0>;
> +               compatible = "intel,ich7";

Although currently the ich spi driver does not use this compatible
string, should this be "intel,ich9"?

> +               spi-flash at 0 {
> +                       reg = <0>;
> +                       compatible = "sst,25vf016b", "spi-flash";
> +                       memory-map = <0xff800000 0x00800000>;
> +               };
> +       };
> +
> +       microcode {
> +               update at 0 {
> +#include "microcode/m0130673322.dtsi"
> +               };
> +       };
> +
> +};
> diff --git a/arch/x86/dts/serial.dtsi b/arch/x86/dts/serial.dtsi
> index 9b097f4..6865eed 100644
> --- a/arch/x86/dts/serial.dtsi
> +++ b/arch/x86/dts/serial.dtsi
> @@ -1,5 +1,5 @@
>  / {
> -       serial {
> +       serial: serial {

I don't see anywhere in this patch refers to this new label?

>                 compatible = "x86-uart";
>                 reg = <0x3f8 8>;
>                 reg-shift = <0>;
> diff --git a/arch/x86/include/asm/arch-baytrail/fsp/azalia.h b/arch/x86/include/asm/arch-baytrail/fsp/azalia.h
> new file mode 100644
> index 0000000..d96a20f
> --- /dev/null
> +++ b/arch/x86/include/asm/arch-baytrail/fsp/azalia.h
> @@ -0,0 +1,39 @@
> +/*
> + * Copyright (C) 2013, Intel Corporation
> + * Copyright (C) 2015 Google, Inc
> + *
> + * SPDX-License-Identifier:    Intel
> + */
> +
> +#ifndef _FSP_AZALIA_H_
> +#define _FSP_AZALIA_H_
> +
> +struct __packed pch_azalia_verb_table_header {
> +       uint32_t vendor_device_id;
> +       uint16_t sub_system_id;
> +       uint8_t revision_id;            /* 0xff applies to all steppings */
> +       uint8_t front_panel_support;
> +       uint16_t number_of_rear_jacks;
> +       uint16_t number_of_front_jacks;
> +};
> +
> +struct __packed pch_azalia_verb_table {
> +       struct pch_azalia_verb_table_header verb_table_header;
> +       const uint32_t *verb_table_data;
> +};
> +
> +struct __packed pch_azalia_config {
> +       uint8_t pme_enable:1;
> +       uint8_t docking_supported:1;
> +       uint8_t docking_attached:1;
> +       uint8_t hdmi_codec_enable:1;
> +       uint8_t azalia_v_ci_enable:1;
> +       uint8_t rsvdbits:3;
> +       /* number of verb tables provided by platform */
> +       uint8_t azalia_verb_table_num;
> +       const struct pch_azalia_verb_table *azalia_verb_table;
> +       /* delay timer after azalia reset */
> +       uint16_t reset_wait_timer_us;
> +};
> +
> +#endif
> diff --git a/arch/x86/include/asm/arch-baytrail/fsp/fsp_vpd.h b/arch/x86/include/asm/arch-baytrail/fsp/fsp_vpd.h
> new file mode 100644
> index 0000000..82862f6
> --- /dev/null
> +++ b/arch/x86/include/asm/arch-baytrail/fsp/fsp_vpd.h
> @@ -0,0 +1,95 @@
> +/*
> + * Copyright (C) 2013, Intel Corporation
> + * Copyright (C) 2015 Google, Inc
> + *
> + * SPDX-License-Identifier:    Intel
> + */
> +
> +#ifndef __FSP_VPD_H
> +#define __FSP_VPD_H
> +
> +struct memory_down_data {
> +       uint8_t enable_memory_down;
> +       uint8_t dram_speed;
> +       uint8_t dram_type;
> +       uint8_t dimm_0_enable;
> +       uint8_t dimm_1_enable;
> +       uint8_t dimm_width;
> +       uint8_t dimm_density;
> +       uint8_t dimm_bus_width;
> +       uint8_t dimm_sides;                     /* Ranks Per dimm_ */
> +       uint8_t dimm_tcl;                       /* tCL */
> +       /* tRP and tRCD in DRAM clk - 5:12.5ns, 6:15ns, etc. */
> +       uint8_t dimm_trpt_rcd;
> +       uint8_t dimm_twr;                       /* tWR in DRAM clk  */
> +       uint8_t dimm_twtr;                      /* tWTR in DRAM clk */
> +       uint8_t dimm_trrd;                      /* tRRD in DRAM clk */
> +       uint8_t dimm_trtp;                      /* tRTP in DRAM clk */
> +       uint8_t dimm_tfaw;                      /* tFAW in DRAM clk */
> +};
> +
> +struct __packed upd_region {
> +       uint64_t signature;                     /* Offset 0x0000 */
> +       uint8_t reserved0[24];                  /* Offset 0x0008 */
> +       uint16_t mrc_init_tseg_size;            /* Offset 0x0020 */
> +       uint16_t mrc_init_mmio_size;            /* Offset 0x0022 */
> +       uint8_t mrc_init_spd_addr1;             /* Offset 0x0024 */
> +       uint8_t mrc_init_spd_addr2;             /* Offset 0x0025 */
> +       uint8_t emmc_boot_mode;                 /* Offset 0x0026 */
> +       uint8_t enable_sdio;                    /* Offset 0x0027 */
> +       uint8_t enable_sdcard;                  /* Offset 0x0028 */
> +       uint8_t enable_hsuart0;                 /* Offset 0x0029 */
> +       uint8_t enable_hsuart1;                 /* Offset 0x002a */
> +       uint8_t enable_spi;                     /* Offset 0x002b */
> +       uint8_t reserved1;                      /* Offset 0x002c */
> +       uint8_t enable_sata;                    /* Offset 0x002d */
> +       uint8_t sata_mode;                      /* Offset 0x002e */
> +       uint8_t enable_azalia;                  /* Offset 0x002f */
> +       uint32_t azalia_config_ptr;             /* Offset 0x0030 */
> +       uint8_t enable_xhci;                    /* Offset 0x0034 */
> +       uint8_t enable_lpe;                     /* Offset 0x0035 */
> +       uint8_t lpss_sio_enable_pci_mode;       /* Offset 0x0036 */
> +       uint8_t enable_dma0;                    /* Offset 0x0037 */
> +       uint8_t enable_dma1;                    /* Offset 0x0038 */
> +       uint8_t enable_i2_c0;                   /* Offset 0x0039 */
> +       uint8_t enable_i2_c1;                   /* Offset 0x003a */
> +       uint8_t enable_i2_c2;                   /* Offset 0x003b */
> +       uint8_t enable_i2_c3;                   /* Offset 0x003c */
> +       uint8_t enable_i2_c4;                   /* Offset 0x003d */
> +       uint8_t enable_i2_c5;                   /* Offset 0x003e */
> +       uint8_t enable_i2_c6;                   /* Offset 0x003f */
> +       uint8_t enable_pwm0;                    /* Offset 0x0040 */
> +       uint8_t enable_pwm1;                    /* Offset 0x0041 */
> +       uint8_t enable_hsi;                     /* Offset 0x0042 */
> +       uint8_t igd_dvmt50_pre_alloc;           /* Offset 0x0043 */
> +       uint8_t aperture_size;                  /* Offset 0x0044 */
> +       uint8_t gtt_size;                       /* Offset 0x0045 */
> +       uint32_t serial_debug_port_address;     /* Offset 0x0046 */
> +       uint8_t serial_debug_port_type;         /* Offset 0x004a */
> +       uint8_t mrc_debug_msg;                  /* Offset 0x004b */
> +       uint8_t isp_enable;                     /* Offset 0x004c */
> +       uint8_t scc_enable_pci_mode;            /* Offset 0x004d */
> +       uint8_t igd_render_standby;             /* Offset 0x004e */
> +       uint8_t txe_uma_enable;                 /* Offset 0x004f */
> +       uint8_t os_selection;                   /* Offset 0x0050 */
> +       uint8_t emmc45_ddr50_enabled;           /* Offset 0x0051 */
> +       uint8_t emmc45_hs200_enabled;           /* Offset 0x0052 */
> +       uint8_t emmc45_retune_timer_value;      /* Offset 0x0053 */
> +       uint8_t unused_upd_space1[156];         /* Offset 0x0054 */
> +       struct memory_down_data memory_params;  /* Offset 0x00f0 */
> +       uint16_t terminator;                    /* Offset 0x0100 */
> +};
> +
> +#define VPD_IMAGE_ID           0x3157454956594C56      /* 'VLYVIEW1' */
> +#define VPD_IMAGE_REV          0x00000303
> +
> +struct __packed vpd_region {
> +       uint64_t sign;                          /* Offset 0x0000 */
> +       uint32_t img_rev;                       /* Offset 0x0008 */
> +       uint32_t upd_offset;                    /* Offset 0x000c */
> +       uint8_t unused[16];                     /* Offset 0x0010 */
> +       uint32_t fsp_res_memlen;                /* Offset 0x0020 */
> +       uint8_t platform_type;                  /* Offset 0x0024 */
> +       uint8_t enable_secure_boot;             /* Offset 0x0025 */
> +};
> +#endif
> diff --git a/arch/x86/include/asm/arch-baytrail/gpio.h b/arch/x86/include/asm/arch-baytrail/gpio.h
> new file mode 100644
> index 0000000..ab4e059
> --- /dev/null
> +++ b/arch/x86/include/asm/arch-baytrail/gpio.h
> @@ -0,0 +1,13 @@
> +/*
> + * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
> + *
> + * SPDX-License-Identifier:    GPL-2.0+
> + */
> +
> +#ifndef _X86_ARCH_GPIO_H_
> +#define _X86_ARCH_GPIO_H_
> +
> +/* Where in config space is the register that points to the GPIO registers? */
> +#define PCI_CFG_GPIOBASE 0x44
> +
> +#endif /* _X86_ARCH_GPIO_H_ */
> diff --git a/board/intel/minnowmax/Kconfig b/board/intel/minnowmax/Kconfig
> new file mode 100644
> index 0000000..7c2b927
> --- /dev/null
> +++ b/board/intel/minnowmax/Kconfig
> @@ -0,0 +1,31 @@
> +if TARGET_MINNOWMAX
> +
> +config SYS_BOARD
> +       default "minnowmax"
> +
> +config SYS_VENDOR
> +       default "intel"
> +
> +config SYS_SOC
> +       default "baytrail"
> +
> +config SYS_CONFIG_NAME
> +       default "minnowmax"
> +
> +config BOARD_SPECIFIC_OPTIONS # dummy
> +       def_bool y
> +       select X86_RESET_VECTOR
> +       select INTEL_BAYTRAIL
> +       select BOARD_ROMSIZE_KB_8192
> +
> +config MMCONF_BASE_ADDRESS
> +       default 0xe0000000
> +
> +config DEBUG_UART_BASE
> +       default 0x3f8
> +
> +config DEBUG_UART_CLOCK
> +       default 1843200
> +#      default 115200

115200 is the baud rate, not the clock. Should be removed to avoid confusion.

> +
> +endif
> diff --git a/board/intel/minnowmax/MAINTAINERS b/board/intel/minnowmax/MAINTAINERS
> new file mode 100644
> index 0000000..d655761
> --- /dev/null
> +++ b/board/intel/minnowmax/MAINTAINERS
> @@ -0,0 +1,6 @@
> +CircuitCo Minnowboard Max
> +M:     Simon Glass <sjg@chromium.org>
> +S:     Maintained
> +F:     board/intel/minnowmax
> +F:     include/configs/minnowmax.h
> +F:     configs/minnowmax_defconfig
> diff --git a/board/intel/minnowmax/Makefile b/board/intel/minnowmax/Makefile
> new file mode 100644
> index 0000000..1a61432
> --- /dev/null
> +++ b/board/intel/minnowmax/Makefile
> @@ -0,0 +1,7 @@
> +#
> +# Copyright (C) 2015, Google, Inc
> +#
> +# SPDX-License-Identifier:     GPL-2.0+
> +#
> +
> +obj-y  += minnowmax.o start.o
> diff --git a/board/intel/minnowmax/minnowmax.c b/board/intel/minnowmax/minnowmax.c
> new file mode 100644
> index 0000000..6e82b16
> --- /dev/null
> +++ b/board/intel/minnowmax/minnowmax.c
> @@ -0,0 +1,32 @@
> +/*
> + * Copyright (C) 2015, Google, Inc
> + *
> + * SPDX-License-Identifier:    GPL-2.0+
> + */
> +
> +#include <common.h>
> +#include <asm/ibmpc.h>
> +#include <asm/pnp_def.h>
> +#include <netdev.h>
> +#include <smsc_lpc47m.h>
> +
> +#define SERIAL_DEV PNP_DEV(0x2e, 4)
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +int board_early_init_f(void)
> +{
> +       lpc47m_enable_serial(SERIAL_DEV, UART0_BASE);
> +
> +       return 0;
> +}
> +
> +void setup_pch_gpios(u16 gpiobase, const struct pch_gpio_map *gpio)
> +{
> +       return;
> +}
> +
> +int board_eth_init(bd_t *bis)
> +{
> +       return pci_eth_init(bis);
> +}
> diff --git a/board/intel/minnowmax/start.S b/board/intel/minnowmax/start.S
> new file mode 100644
> index 0000000..2c941a4
> --- /dev/null
> +++ b/board/intel/minnowmax/start.S
> @@ -0,0 +1,9 @@
> +/*
> + * Copyright (C) 2015, Google, Inc
> + *
> + * SPDX-License-Identifier:    GPL-2.0+
> + */
> +
> +.globl early_board_init
> +early_board_init:
> +       jmp     early_board_init_ret
> diff --git a/configs/minnowmax_defconfig b/configs/minnowmax_defconfig
> new file mode 100644
> index 0000000..7bc9085
> --- /dev/null
> +++ b/configs/minnowmax_defconfig
> @@ -0,0 +1,13 @@
> +CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0xfff00000"
> +CONFIG_X86=y
> +CONFIG_TARGET_MINNOWMAX=y
> +CONFIG_OF_CONTROL=y
> +CONFIG_OF_SEPARATE=y
> +CONFIG_DEFAULT_DEVICE_TREE="minnowmax"
> +CONFIG_VIDEO_X86=y
> +CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
> +CONFIG_FRAMEBUFFER_VESA_MODE_11A=y
> +CONFIG_DEBUG_UART_NS16550=y
> +CONFIG_DEBUG_UART=y
> +CONFIG_MMCONF_BASE_ADDRESS=0xe0000000
> +CONFIG_HAVE_INTEL_ME=y
> diff --git a/doc/README.x86 b/doc/README.x86
> index 0e4628a..cd9a926 100644
> --- a/doc/README.x86
> +++ b/doc/README.x86
> @@ -18,11 +18,11 @@ U-Boot supports running as a coreboot [1] payload on x86. So far only Link
>  on other x86 boards since coreboot deals with most of the low-level details.
>
>  U-Boot also supports booting directly from x86 reset vector without coreboot,
> -aka raw support or bare support. Currently Link and Intel Crown Bay board
> -support running U-Boot 'bare metal'.
> +aka raw support or bare support. Currently Link, Intel Crown Bay and Intel
> +Minnowboard Max support running U-Boot 'bare metal'.
>
> -As for loading OS, U-Boot supports directly booting a 32-bit or 64-bit Linux
> -kernel as part of a FIT image. It also supports a compressed zImage.
> +As for loading an OS, U-Boot supports directly booting a 32-bit or 64-bit
> +Linux kernel as part of a FIT image. It also supports a compressed zImage.
>
>  Build Instructions
>  ------------------
> @@ -47,11 +47,11 @@ Change the 'Board configuration file' and 'Board Device Tree Source (dts) file'
>  to point to a new board. You can also change the Cache-As-RAM (CAR) related
>  settings here if the default values do not fit your new board.
>
> -Building ROM version of U-Boot (hereafter referred to as u-boot.rom) is a
> +Building a ROM version of U-Boot (hereafter referred to as u-boot.rom) is a
>  little bit tricky, as generally it requires several binary blobs which are not
>  shipped in the U-Boot source tree. Due to this reason, the u-boot.rom build is
>  not turned on by default in the U-Boot source tree. Firstly, you need turn it
> -on by enabling the ROM board:
> +on by enabling the ROM build

OK, get if fixed here :)

>
>  $ export BUILD_ROM=y
>
> @@ -110,6 +110,33 @@ Now you can build U-Boot and obtain u-boot.rom
>  $ make crownbay_defconfig
>  $ make all
>
> +
> +Intel Minnowboard Max instructions:
> +
> +This uses as FSP as with Crown Bay, except it is for the Atom E3800 series.
> +Download this and get the .fd file (BAYTRAIL_FSP_GOLD_003_16-SEP-2014.fd at
> +the time of writing). Put it in the board directory:
> +board/intel/minnowmax/fsp.bin
> +
> +Obtain the VGA RAM (Vga.dat at the time of writing) and put it into the same
> +directory: board/intel/minnowmax/vga.bin
> +
> +You still need two more binary blobs. These come from the sample SPI image
> +provided in the FSP (SPI.bin at the time of writing).
> +
> +Use ifdtool in the U-Boot tools directory to extract the images from that
> +file, for example:
> +
> +   $ ./tools/ifdtool -x BayleyBay/SPI.bin
> +   $ cp flashregion_2_intel_me.bin board/intel/minnowmax/me.bin
> +   $ cp flashregion_0_flashdescriptor.bin board/intel/minnowmax/descriptor.bin
> +
> +Now you can build U-Boot and obtain u-boot.rom
> +
> +$ make minnowmax_defconfig
> +$ make all
> +
> +
>  Test with coreboot
>  ------------------
>  For testing U-Boot as the coreboot payload, there are things that need be paid
> @@ -130,6 +157,16 @@ symbol address of _start (in arch/x86/cpu/start.S).
>  If you want to use ELF as the coreboot payload, change U-Boot configuration to
>  use CONFIG_OF_EMBED instead of CONFIG_OF_SEPARATE.
>
> +To enable video you must enable these options in Coreboot:

Coreboot -> coreboot

> +
> +   - Set framebuffer graphics resolution (1280x1024 32k-color (1:5:5))
> +   - Keep VESA framebuffer
> +
> +At present it seems that for Minnowboard Max, coreboot does not pass through
> +the video information correctly (it always says the resolution is 0x0). This
> +works correctly for link though.
> +
> +
>  CPU Microcode
>  -------------
>  Modern CPUs usually requires a special bit stream called microcode [5] to be
> diff --git a/include/configs/minnowmax.h b/include/configs/minnowmax.h
> new file mode 100644
> index 0000000..507afb8
> --- /dev/null
> +++ b/include/configs/minnowmax.h
> @@ -0,0 +1,69 @@
> +/*
> + * Copyright (C) 2015 Google, Inc
> + *
> + * SPDX-License-Identifier:    GPL-2.0+
> + */
> +
> +/*
> + * board/config.h - configuration options, board specific
> + */
> +
> +#ifndef __CONFIG_H
> +#define __CONFIG_H
> +
> +#include <configs/x86-common.h>
> +
> +#define CONFIG_SYS_MONITOR_LEN         (1 << 20)
> +#define CONFIG_BOARD_EARLY_INIT_F
> +
> +#define CONFIG_NR_DRAM_BANKS           1
> +
> +#define CONFIG_X86_SERIAL
> +#define CONFIG_SMSC_LPC47M
> +
> +#define CONFIG_PCI_MEM_BUS             0xd0000000
> +#define CONFIG_PCI_MEM_PHYS            CONFIG_PCI_MEM_BUS
> +#define CONFIG_PCI_MEM_SIZE            0x10000000
> +
> +#define CONFIG_PCI_PREF_BUS            0xc0000000
> +#define CONFIG_PCI_PREF_PHYS           CONFIG_PCI_PREF_BUS
> +#define CONFIG_PCI_PREF_SIZE           0x10000000
> +
> +#define CONFIG_PCI_IO_BUS              0x2000
> +#define CONFIG_PCI_IO_PHYS             CONFIG_PCI_IO_BUS
> +#define CONFIG_PCI_IO_SIZE             0xe000
> +
> +#define CONFIG_SYS_EARLY_PCI_INIT
> +#define CONFIG_PCI_PNP
> +#define CONFIG_RTL8169
> +#define CONFIG_STD_DEVICES_SETTINGS     "stdin=usbkbd,vga,serial\0" \
> +                                       "stdout=vga,serial\0" \
> +                                       "stderr=vga,serial\0"
> +
> +#define CONFIG_SCSI_DEV_LIST            \
> +       {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_VALLEYVIEW_SATA}
> +#define CONFIG_SPI_FLASH_SST
> +
> +#define CONFIG_MMC
> +#define CONFIG_SDHCI
> +#define CONFIG_GENERIC_MMC
> +#define CONFIG_MMC_SDMA
> +#define CONFIG_CMD_MMC
> +
> +#undef CONFIG_USB_MAX_CONTROLLER_COUNT
> +#define CONFIG_USB_MAX_CONTROLLER_COUNT                1
> +
> +#define CONFIG_X86_OPTION_ROM_FILE             vga.bin
> +#define CONFIG_X86_OPTION_ROM_ADDR             0xfff90000
> +
> +#ifndef CONFIG_SYS_COREBOOT
> +#define CONFIG_VIDEO_VESA
> +#endif
> +#define VIDEO_IO_OFFSET                                0
> +#define CONFIG_X86EMU_RAW_IO
> +#define CONFIG_VGA_AS_SINGLE_DEVICE
> +
> +#define CONFIG_FIT_SIGNATURE
> +#define CONFIG_RSA
> +
> +#endif /* __CONFIG_H */
> --

Regards,
Bin

[U-Boot] [PATCH 0/23] x86: Add bare support for Intel Minnowboard Max

[Bin Meng]

Hi Simon,

On Tue, Jan 27, 2015 at 9:22 AM, Simon Glass <sjg@chromium.org> wrote:
> This series adds support for the Intel Minnowboard Max (called Minnowmax
> for short). Along the way a few refactors and additions are made:
>
> - The Intel Firmware Support Package support is moved from queensbay to a
> common location
> - PCI support for XHCI is added
> - A few tweaks are made to the PCI support
> - Support for the debug UART (early debug output) is provided
> - The microcode tool now also supports reading in header files
>
> This board has been lightly tested. The following seem to work:
>
> - USB2 on the blue port (not USB3), e.g. for keyboard
> - Ethernet
> - HDMI out and console
> - UART
> - uSD card
> - SPI
>
> SATA is detected but I have not attached a drive to try it. USB3 shows signs
> of life but does not detect a USB stick, and crashes when trying to use a
> USB Ethernet adaptor.
>
> For SPI some parts cannot be read and others cannot be written. This seems
> to be a feature of the Intel hardware configuration. It may be possible to
> fix this using the SPI registers but I cannot work out how / lost interest
> trying. So far, addresses from 500000 to 700000 can be used.
>
> I have not tried the ICH GPIO driver but it likely needs work before it will
> function. I2C is not supported as there is currently no U-Boot driver for
> this.
>
> The zboot command can be used to start a bzImage kernel. Verified boot is
> supported - use mkimage to sign images as described in this walk-through:
> doc/uImage.FIT/beaglebone_vboot.txt
>
> Boot time is grim:
> - 1423ms to set up display (Intel FSP)
> - 454ms to scan AHCI (when no devices are connected)
> - ~1000ms to power up and start cache-as-RAM init (Intel FSP)
>      (this is not benchmarked, may be inaccurate)
> - ~950ms to set up memory and initial machine configuration (Intel FSP)
>      (this is not benchmarked, may be inaccurate)
>
> So it takes over 4 seconds to get to booting a kernel.
>
> Implementing the Memory Reference Code (MRC) cache should improve this
> slightly (perhaps a reduction of 500-1000ms). This cache is implemented for
> ivybridge so that code needs to be moved into a generic x86 directory and
> plumbed into the FSP code. This has not been done in this series. Also the
> video and SATA/AHCI can be disabled if preferred.
>
> It is also possible to run as a coreboot payload. See the instructions in
> README.x86 for this. In this case video does not work since coreboot does
> not pass through the VESA display information.
>
> To support the single-core 1GB variant, changes would need to be made to
> arch/x86/cpu/baytrail/fsp_configs.c to select different values for the
> memory. The microcode update may need to change also.
>
> This series is available at u-boot-x86 branch minnow-working.
>

I have finished the review of this patch series. Generally they look
pretty good. Glad to see we have another new Intel board supported
running U-Boot 'bare'!

[snip]

Regards,
Bin

[U-Boot] [PATCH 01/23] x86: Enhance the microcode tool to support header files as input

[Simon Glass]

Hi Bin,

On 27 January 2015 at 01:59, Bin Meng <bmeng.cn@gmail.com> wrote:
> Hi Simon,
>
> On Tue, Jan 27, 2015 at 9:22 AM, Simon Glass <sjg@chromium.org> wrote:
>> Sometimes microcode is delivered as a header file. Allow the tool to
>> support this as well as collecting multiple microcode blocks into a
>> single update.
>>
>> Signed-off-by: Simon Glass <sjg@chromium.org>
>> ---
>
> Tested-by: Bin Meng <bmeng.cn@gmail.com>
>
> But please see my comments below.
>
>>  tools/microcode-tool.py | 90 ++++++++++++++++++++++++++++++++++++++-----------
>>  1 file changed, 70 insertions(+), 20 deletions(-)
>>
>> diff --git a/tools/microcode-tool.py b/tools/microcode-tool.py
>> index 003716d..71c2e91 100755
>> --- a/tools/microcode-tool.py
>> +++ b/tools/microcode-tool.py
>> @@ -76,6 +76,35 @@ def ParseFile(fname):
>>          microcodes[name] = Microcode(name, data)
>>      return date, license_text, microcodes
>>
>> +def ParseHeaderFiles(fname_list):
>> +    """Parse a list of header files and return the component parts
>> +
>> +    Args:
>> +        fname_list: List of files to parse
>> +    Returns:
>> +            date:         String containing date from the file's header
>> +            license_text: List of text lines for the license file
>> +            microcodes:   List of Microcode objects from the file
>> +    """
>> +    microcodes = {}
>> +    license_text = []
>> +    date = ''
>> +    name = None
>> +    for fname in fname_list:
>> +        name = os.path.basename(fname).lower()
>> +        name = os.path.splitext(name)[0]
>> +        data = []
>> +        with open(fname) as fd:
>> +            for line in fd:
>> +                line = line.rstrip()
>> +
>> +                # Omit anything after the last comma
>> +                words = line.split(',')[:-1]
>> +                data += [word + ',' for word in words]
>> +        microcodes[name] = Microcode(name, data)
>> +    return date, license_text, microcodes
>> +
>> +
>>  def List(date, microcodes, model):
>>      """List the available microcode chunks
>>
>> @@ -129,13 +158,13 @@ def FindMicrocode(microcodes, model):
>>              break
>>      return found, tried
>>
>> -def CreateFile(date, license_text, mcode, outfile):
>> +def CreateFile(date, license_text, mcodes, outfile):
>>      """Create a microcode file in U-Boot's .dtsi format
>>
>>      Args:
>>          date:       String containing date of original microcode file
>>          license:    List of text lines for the license file
>> -        mcode:      Microcode object to write
>> +        mcodes:      Microcode objects to write (normally only 1)
>>          outfile:    Filename to write to ('-' for stdout)
>>      """
>>      out = '''/*%s
>> @@ -159,15 +188,22 @@ intel,processor-flags = <%#x>;
>>  data = <%s
>>  \t>;'''
>>      words = ''
>> -    for i in range(len(mcode.words)):
>> -        if not (i & 3):
>> -            words += '\n'
>> -        val = mcode.words[i]
>> -        # Change each word so it will be little-endian in the FDT
>> -        # This data is needed before RAM is available on some platforms so we
>> -        # cannot do an endianness swap on boot.
>> -        val = struct.unpack("<I", struct.pack(">I", val))[0]
>> -        words += '\t%#010x' % val
>> +    add_comments = len(mcodes) > 1
>> +    for mcode in mcodes:
>> +        if add_comments:
>> +            words += '\n/* %s */' % mcode.name
>> +        for i in range(len(mcode.words)):
>> +            if not (i & 3):
>> +                words += '\n'
>> +            val = mcode.words[i]
>> +            # Change each word so it will be little-endian in the FDT
>> +            # This data is needed before RAM is available on some platforms so
>> +            # we cannot do an endianness swap on boot.
>> +            val = struct.unpack("<I", struct.pack(">I", val))[0]
>> +            words += '\t%#010x' % val
>> +
>> +    # Use the first microcode for the headers
>> +    mcode = mcodes[0]
>>
>>      # Take care to avoid adding a space before a tab
>>      text = ''
>> @@ -187,8 +223,8 @@ data = <%s
>>                  print >> sys.stderr, "Creating directory '%s'" % MICROCODE_DIR
>>                  os.makedirs(MICROCODE_DIR)
>>              outfile = os.path.join(MICROCODE_DIR, mcode.name + '.dtsi')
>> -            print >> sys.stderr, "Writing microcode for '%s' to '%s'" % (
>> -                     mcode.name, outfile)
>> +        print >> sys.stderr, "Writing microcode for '%s' to '%s'" % (
>> +                ', '.join([mcode.name for mcode in mcodes]), outfile)
>>          with open(outfile, 'w') as fd:
>>              print >> fd, out % tuple(args)
>>
>> @@ -198,8 +234,12 @@ def MicrocodeTool():
>>      parser = OptionParser()
>>      parser.add_option('-d', '--mcfile', type='string', action='store',
>>                      help='Name of microcode.dat file')
>> +    parser.add_option('-H', '--headerfile', type='string', action='append',
>> +                    help='Name of .h file containing microcode')
>>      parser.add_option('-m', '--model', type='string', action='store',
>> -                    help='Model name to extract')
>> +                    help="Model name to extract ('all' for all)")
>> +    parser.add_option('-M', '--multiple', type='string', action='store',
>> +                    help="Allow output of multiple models")
>>      parser.add_option('-o', '--outfile', type='string', action='store',
>>                      help='Filename to use for output (- for stdout), default is'
>>                      ' %s/<name>.dtsi' % MICROCODE_DIR)
>> @@ -224,9 +264,14 @@ def MicrocodeTool():
>>      if cmd not in commands:
>>          parser.error("Unknown command '%s'" % cmd)
>>
>> -    if not options.mcfile:
>> -        parser.error('You must specify a microcode file')
>> -    date, license_text, microcodes = ParseFile(options.mcfile)
>> +    if (not not options.mcfile) != (not not options.mcfile):
>> +        parser.error("You must specify either header files or a microcode file, not both")
>> +    if options.headerfile:
>> +        date, license_text, microcodes = ParseHeaderFiles(options.headerfile)
>> +    elif options.mcfile:
>> +        date, license_text, microcodes = ParseFile(options.mcfile)
>> +    else:
>> +        parser.error('You must specify a microcode file (or header files)')
>>
>>      if cmd == 'list':
>>          List(date, microcodes, options.model)
>> @@ -236,16 +281,21 @@ def MicrocodeTool():
>>          if not options.model:
>>              parser.error('You must specify a model to create')
>>          model = options.model.lower()
>> -        mcode_list, tried = FindMicrocode(microcodes, model)
>> +        if options.model == 'all':
>> +            options.multiple = True
>> +            mcode_list = microcodes.values()
>> +            tried = []
>> +        else:
>> +            mcode_list, tried = FindMicrocode(microcodes, model)
>>          if not mcode_list:
>>              parser.error("Unknown model '%s' (%s) - try 'list' to list" %
>>                          (model, ', '.join(tried)))
>> -        if len(mcode_list) > 1:
>> +        if not options.multiple and len(mcode_list) > 1:
>>              parser.error("Ambiguous model '%s' (%s) matched %s - try 'list' "
>>                          "to list or specify a particular file" %
>>                          (model, ', '.join(tried),
>>                          ', '.join([m.name for m in mcode_list])))
>> -        CreateFile(date, license_text, mcode_list[0], options.outfile)
>> +        CreateFile(date, license_text, mcode_list, options.outfile)
>>      else:
>>          parser.error("Unknown command '%s'" % cmd)
>>
>> --
>
> My testing results show that, compared to '-d microcode.dat' approach,
> generated microcode.dtsi using '-H' does not have license header and
> date set. Is this intentional?

Not really, but the header I tested with has no license info.

I suspect we could enable use of -d also to pick this up. But we still
wouldn't get the date. I'm not sure what automation we should have for
this case.

Regards,
Simon

[U-Boot] [PATCH 14/23] x86: Move common FSP functions into a common file

[Simon Glass]

Hi Bin,

On 27 January 2015 at 05:20, Bin Meng <bmeng.cn@gmail.com> wrote:
> Hi Simon,
>
> On Tue, Jan 27, 2015 at 9:23 AM, Simon Glass <sjg@chromium.org> wrote:
>> Since these board functions seem to be the same for all boards which use
>> FSP, move them into a common file. We can adjust this later if future FSPs
>> need more flexibility.
>>
>> Signed-off-by: Simon Glass <sjg@chromium.org>
>> ---
>>
>>  arch/x86/cpu/queensbay/tnc.c      | 27 ------------
>>  arch/x86/cpu/queensbay/tnc_pci.c  | 15 -------
>>  arch/x86/cpu/queensbay/topcliff.c | 32 +-------------
>>  arch/x86/include/asm/u-boot-x86.h | 17 ++++++++
>>  arch/x86/lib/fsp/Makefile         |  1 +
>>  arch/x86/lib/fsp/fsp_common.c     | 88 +++++++++++++++++++++++++++++++++++++++
>>  6 files changed, 108 insertions(+), 72 deletions(-)
>>  create mode 100644 arch/x86/lib/fsp/fsp_common.c
>>
>> diff --git a/arch/x86/cpu/queensbay/tnc.c b/arch/x86/cpu/queensbay/tnc.c
>> index f9b3bfa..30ab725 100644
>> --- a/arch/x86/cpu/queensbay/tnc.c
>> +++ b/arch/x86/cpu/queensbay/tnc.c
>> @@ -43,30 +43,3 @@ int arch_cpu_init(void)
>>
>>         return 0;
>>  }
>> -
>> -int print_cpuinfo(void)
>> -{
>> -       post_code(POST_CPU_INFO);
>> -       return default_print_cpuinfo();
>> -}
>> -
>> -void reset_cpu(ulong addr)
>> -{
>> -       /* cold reset */
>> -       outb(0x06, PORT_RESET);
>> -}
>> -
>> -void board_final_cleanup(void)
>> -{
>> -       u32 status;
>> -
>> -       /* call into FspNotify */
>> -       debug("Calling into FSP (notify phase INIT_PHASE_BOOT): ");
>> -       status = fsp_notify(NULL, INIT_PHASE_BOOT);
>> -       if (status != FSP_SUCCESS)
>> -               debug("fail, error code %x\n", status);
>> -       else
>> -               debug("OK\n");
>> -
>> -       return;
>> -}
>> diff --git a/arch/x86/cpu/queensbay/tnc_pci.c b/arch/x86/cpu/queensbay/tnc_pci.c
>> index 9b0b725..6c291f9 100644
>> --- a/arch/x86/cpu/queensbay/tnc_pci.c
>> +++ b/arch/x86/cpu/queensbay/tnc_pci.c
>> @@ -44,18 +44,3 @@ void board_pci_setup_hose(struct pci_controller *hose)
>>
>>         hose->region_count = 4;
>>  }
>> -
>> -int board_pci_post_scan(struct pci_controller *hose)
>> -{
>> -       u32 status;
>> -
>> -       /* call into FspNotify */
>> -       debug("Calling into FSP (notify phase INIT_PHASE_PCI): ");
>> -       status = fsp_notify(NULL, INIT_PHASE_PCI);
>> -       if (status != FSP_SUCCESS)
>> -               debug("fail, error code %x\n", status);
>> -       else
>> -               debug("OK\n");
>> -
>> -       return 0;
>> -}
>> diff --git a/arch/x86/cpu/queensbay/topcliff.c b/arch/x86/cpu/queensbay/topcliff.c
>> index b01422a..25032cc 100644
>> --- a/arch/x86/cpu/queensbay/topcliff.c
>> +++ b/arch/x86/cpu/queensbay/topcliff.c
>> @@ -5,43 +5,15 @@
>>   */
>>
>>  #include <common.h>
>> -#include <errno.h>
>> -#include <malloc.h>
>> -#include <pci.h>
>>  #include <pci_ids.h>
>> -#include <sdhci.h>
>>
>>  static struct pci_device_id mmc_supported[] = {
>>         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TCF_SDIO_0 },
>>         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TCF_SDIO_1 },
>> -       { }
>>  };
>>
>>  int cpu_mmc_init(bd_t *bis)
>>  {
>> -       struct sdhci_host *mmc_host;
>> -       pci_dev_t devbusfn;
>> -       u32 iobase;
>> -       int ret;
>> -       int i;
>> -
>> -       for (i = 0; i < ARRAY_SIZE(mmc_supported); i++) {
>> -               devbusfn =  pci_find_devices(mmc_supported, i);
>> -               if (devbusfn == -1)
>> -                       return -ENODEV;
>> -
>> -               mmc_host = (struct sdhci_host *)malloc(sizeof(struct sdhci_host));
>> -               if (!mmc_host)
>> -                       return -ENOMEM;
>> -
>> -               mmc_host->name = "Topcliff SDHCI";
>> -               pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_0, &iobase);
>> -               mmc_host->ioaddr = (void *)iobase;
>> -               mmc_host->quirks = 0;
>> -               ret = add_sdhci(mmc_host, 0, 0);
>> -               if (ret)
>> -                       return ret;
>> -       }
>> -
>> -       return 0;
>> +       return fsp_cpu_mmc_init("Topcliff SDHCI", mmc_supported,
>> +                               ARRAY_SIZE(mmc_supported));
>>  }
>
> I don't think this function should be moved to fsp_common.c as it has
> nothing related to FSP. We can move this whole function to
> drivers/mmc/, something like intel_mmc.c or intel_sdhc.c.

How about pci_mmc.c if it is generic to PCI?

>
>> diff --git a/arch/x86/include/asm/u-boot-x86.h b/arch/x86/include/asm/u-boot-x86.h
>> index b98afa8..44c24ff 100644
>> --- a/arch/x86/include/asm/u-boot-x86.h
>> +++ b/arch/x86/include/asm/u-boot-x86.h
>> @@ -45,6 +45,23 @@ ulong board_get_usable_ram_top(ulong total_size);
>>  void dram_init_banksize(void);
>>  int default_print_cpuinfo(void);
>>
>> +struct pci_device_id;
>> +
>> +/**
>> + * fsp_cpu_mmc_init() - set up PCI MMC devices
>> + *
>> + * This finds all the matching PCI IDs and sets them up as MMC devices.
>> + *
>> + * @name:              Name to use for devices
>> + * @mmc_supported:     PCI IDs to search for
>> + * @num_ids:           Number of elements in @mmc_supported
>> + */
>> +int fsp_cpu_mmc_init(const char *name, struct pci_device_id mmc_supported[],
>> +                    int num_ids);
>> +
>> +/* Set up a UART which can be used with printch(), printhex8(), etc. */
>> +int setup_early_uart(void);
>> +
>
> Where is the setup_early_uart() function implementation?

I think you found it later. I will fix this.

>
>>  void setup_pcat_compatibility(void);
>>
>>  void isa_unmap_rom(u32 addr);
>> diff --git a/arch/x86/lib/fsp/Makefile b/arch/x86/lib/fsp/Makefile
>> index 3a2bac0..5b12c12 100644
>> --- a/arch/x86/lib/fsp/Makefile
>> +++ b/arch/x86/lib/fsp/Makefile
>> @@ -5,5 +5,6 @@
>>  #
>>
>>  obj-y += fsp_car.o
>> +obj-y += fsp_common.o
>>  obj-y += fsp_dram.o
>>  obj-y += fsp_support.o
>> diff --git a/arch/x86/lib/fsp/fsp_common.c b/arch/x86/lib/fsp/fsp_common.c
>> new file mode 100644
>> index 0000000..846c136
>> --- /dev/null
>> +++ b/arch/x86/lib/fsp/fsp_common.c
>> @@ -0,0 +1,88 @@
>> +/*
>> + * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
>> + *
>> + * SPDX-License-Identifier:    GPL-2.0+
>> + */
>> +
>> +#include <common.h>
>> +#include <errno.h>
>> +#include <malloc.h>
>> +#include <sdhci.h>
>> +#include <asm/io.h>
>> +#include <asm/pci.h>
>> +#include <asm/post.h>
>> +#include <asm/processor.h>
>> +#include <asm/fsp/fsp_support.h>
>> +
>> +int print_cpuinfo(void)
>> +{
>> +       post_code(POST_CPU_INFO);
>> +       return default_print_cpuinfo();
>> +}
>> +
>> +void reset_cpu(ulong addr)
>> +{
>> +       /* cold reset */
>> +       outb(0x06, PORT_RESET);
>> +}
>> +
>> +
>> +int board_pci_post_scan(struct pci_controller *hose)
>> +{
>> +       u32 status;
>> +
>> +       /* call into FspNotify */
>> +       debug("Calling into FSP (notify phase INIT_PHASE_PCI): ");
>> +       status = fsp_notify(NULL, INIT_PHASE_PCI);
>> +       if (status != FSP_SUCCESS)
>> +               debug("fail, error code %x\n", status);
>> +       else
>> +               debug("OK\n");
>> +
>> +       return 0;
>> +}
>> +
>> +void board_final_cleanup(void)
>> +{
>> +       u32 status;
>> +
>> +       /* call into FspNotify */
>> +       debug("Calling into FSP (notify phase INIT_PHASE_BOOT): ");
>> +       status = fsp_notify(NULL, INIT_PHASE_BOOT);
>> +       if (status != FSP_SUCCESS)
>> +               debug("fail, error code %x\n", status);
>> +       else
>> +               debug("OK\n");
>> +
>> +       return;
>> +}
>> +
>> +int fsp_cpu_mmc_init(const char *name, struct pci_device_id mmc_supported[],
>> +                    int num_ids)
>> +{
>> +       struct sdhci_host *mmc_host;
>> +       pci_dev_t devbusfn;
>> +       u32 iobase;
>> +       int ret;
>> +       int i;
>> +
>> +       for (i = 0; i < num_ids; i++) {
>> +               devbusfn = pci_find_devices(mmc_supported, i);
>> +               if (devbusfn == -1)
>> +                       return -ENODEV;
>> +
>> +               mmc_host = malloc(sizeof(struct sdhci_host));
>> +               if (!mmc_host)
>> +                       return -ENOMEM;
>> +
>> +               mmc_host->name = (char *)name;
>> +               pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_0, &iobase);
>> +               mmc_host->ioaddr = (void *)iobase;
>> +               mmc_host->quirks = 0;
>> +               ret = add_sdhci(mmc_host, 0, 0);
>> +               if (ret)
>> +                       return ret;
>> +       }
>> +
>> +       return 0;
>> +}
>> --
>
> Regards,
> Bin

Regards,
Simon

[U-Boot] [PATCH 20/23] scsi: bootstage: Measure time taken to scan the bus

[Rob Herring]

On Mon, Jan 26, 2015 at 7:23 PM, Simon Glass <sjg@chromium.org> wrote:
> On some hardware this time can be significant. Add bootstage support for
> measuring this. The result can be obtained using 'bootstage report' or
> passed on to the Linux via the device tree.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> ---
>
>  common/cmd_scsi.c   | 2 ++
>  include/bootstage.h | 1 +
>  2 files changed, 3 insertions(+)
>
> diff --git a/common/cmd_scsi.c b/common/cmd_scsi.c
> index cbc107e..a0a62eb 100644
> --- a/common/cmd_scsi.c
> +++ b/common/cmd_scsi.c
> @@ -217,8 +217,10 @@ void scsi_init(void)
>                        (busdevfunc >> 8) & 0x7);
>         }
>  #endif
> +       bootstage_start(BOOTSTAGE_ID_ACCUM_SCSI, "ahci");
>         scsi_low_level_init(busdevfunc);
>         scsi_scan(1);
> +       bootstage_accum(BOOTSTAGE_ID_ACCUM_SCSI);

This does not cover the case if the platform calls scsi_scan at boot.
The first time is the important one as that will include disk spin-up
time.

Perhaps they shouldn't be and "scsi scan" should always be in boot scripts.

Rob

[U-Boot] [PATCH 05/23] usb: pci: Use pci_find_class() to find the device

[Marek Vasut]

On Tuesday, January 27, 2015 at 02:23:03 AM, Simon Glass wrote:
> Use the new utility function instead of local code.
> 
> Signed-off-by: Simon Glass <sjg@chromium.org>
> ---
> 
>  drivers/usb/host/ehci-pci.c | 53
> +-------------------------------------------- 1 file changed, 1
> insertion(+), 52 deletions(-)

Nice!

Acked-by: Marek Vasut <marex@denx.de>

Do you want to pick it through the x86 tree or shall I pick it through USB ?

Best regards,
Marek Vasut

[U-Boot] [PATCH 06/23] usb: pci: Add XHCI driver for PCI

[Marek Vasut]

On Tuesday, January 27, 2015 at 02:23:04 AM, Simon Glass wrote:
> Add a driver which locates the available XHCI controllers on the PCI bus
> and makes them available.
> 
> Signed-off-by: Simon Glass <sjg@chromium.org>

Hi!

Which xhci controllers did you test with this patch and on which platform 
please? Is it just the minnow max + the integrated usb 3.0 controller on
it? I recall I tried this, but had trouble getting the xhci-pci going on
MX6 with a PCIe card with renesas controller.

Thanks for working on this !

Best regards,
Marek Vasut

[U-Boot] [PATCH 06/23] usb: pci: Add XHCI driver for PCI

[Simon Glass]

Hi Marek,

On 27 January 2015 at 10:57, Marek Vasut <marex@denx.de> wrote:
> On Tuesday, January 27, 2015 at 02:23:04 AM, Simon Glass wrote:
>> Add a driver which locates the available XHCI controllers on the PCI bus
>> and makes them available.
>>
>> Signed-off-by: Simon Glass <sjg@chromium.org>
>
> Hi!
>
> Which xhci controllers did you test with this patch and on which platform
> please? Is it just the minnow max + the integrated usb 3.0 controller on
> it? I recall I tried this, but had trouble getting the xhci-pci going on
> MX6 with a PCIe card with renesas controller.
>
> Thanks for working on this !

I tested it on an Intel controller (MinnowMax board). As mentioned in
the cover letter it doesn't actually work, but I suspect that could be
an XHCI stack issue. Not 100% sure though. At least this is a starting
point.

Regards,
Simon

[U-Boot] [PATCH 05/23] usb: pci: Use pci_find_class() to find the device

[Simon Glass]

Hi Marek,

On 27 January 2015 at 10:50, Marek Vasut <marex@denx.de> wrote:
> On Tuesday, January 27, 2015 at 02:23:03 AM, Simon Glass wrote:
>> Use the new utility function instead of local code.
>>
>> Signed-off-by: Simon Glass <sjg@chromium.org>
>> ---
>>
>>  drivers/usb/host/ehci-pci.c | 53
>> +-------------------------------------------- 1 file changed, 1
>> insertion(+), 52 deletions(-)
>
> Nice!
>
> Acked-by: Marek Vasut <marex@denx.de>
>
> Do you want to pick it through the x86 tree or shall I pick it through USB ?
>

I think x86 is better since it is part of a series.

Regards,
Simon

[U-Boot] [PATCH 05/23] usb: pci: Use pci_find_class() to find the device

[Marek Vasut]

On Tuesday, January 27, 2015 at 09:53:01 PM, Simon Glass wrote:
> Hi Marek,

Hi Simon,

> On 27 January 2015 at 10:50, Marek Vasut <marex@denx.de> wrote:
> > On Tuesday, January 27, 2015 at 02:23:03 AM, Simon Glass wrote:
> >> Use the new utility function instead of local code.
> >> 
> >> Signed-off-by: Simon Glass <sjg@chromium.org>
> >> ---
> >> 
> >>  drivers/usb/host/ehci-pci.c | 53
> >> 
> >> +-------------------------------------------- 1 file changed, 1
> >> insertion(+), 52 deletions(-)
> > 
> > Nice!
> > 
> > Acked-by: Marek Vasut <marex@denx.de>
> > 
> > Do you want to pick it through the x86 tree or shall I pick it through
> > USB ?
> 
> I think x86 is better since it is part of a series.

I agree, thanks!

Best regards,
Marek Vasut

[U-Boot] [PATCH 06/23] usb: pci: Add XHCI driver for PCI

[Marek Vasut]

On Tuesday, January 27, 2015 at 09:52:14 PM, Simon Glass wrote:
> Hi Marek,

Hi!

> On 27 January 2015 at 10:57, Marek Vasut <marex@denx.de> wrote:
> > On Tuesday, January 27, 2015 at 02:23:04 AM, Simon Glass wrote:
> >> Add a driver which locates the available XHCI controllers on the PCI bus
> >> and makes them available.
> >> 
> >> Signed-off-by: Simon Glass <sjg@chromium.org>
> > 
> > Hi!
> > 
> > Which xhci controllers did you test with this patch and on which platform
> > please? Is it just the minnow max + the integrated usb 3.0 controller on
> > it? I recall I tried this, but had trouble getting the xhci-pci going on
> > MX6 with a PCIe card with renesas controller.
> > 
> > Thanks for working on this !
> 
> I tested it on an Intel controller (MinnowMax board). As mentioned in
> the cover letter it doesn't actually work, but I suspect that could be
> an XHCI stack issue. Not 100% sure though. At least this is a starting
> point.

Ah, I must have missed that, sorry. Good luck with this USB3 stuff!

Best regards,
Marek Vasut

[U-Boot] [PATCH 01/23] x86: Enhance the microcode tool to support header files as input

[Bin Meng]

Hi Simon,

On Tue, Jan 27, 2015 at 11:12 PM, Simon Glass <sjg@chromium.org> wrote:
> Hi Bin,
>
> On 27 January 2015 at 01:59, Bin Meng <bmeng.cn@gmail.com> wrote:
>> Hi Simon,
>>
>> On Tue, Jan 27, 2015 at 9:22 AM, Simon Glass <sjg@chromium.org> wrote:
>>> Sometimes microcode is delivered as a header file. Allow the tool to
>>> support this as well as collecting multiple microcode blocks into a
>>> single update.
>>>
>>> Signed-off-by: Simon Glass <sjg@chromium.org>
>>> ---
>>
>> Tested-by: Bin Meng <bmeng.cn@gmail.com>
>>
>> But please see my comments below.
>>
>>>  tools/microcode-tool.py | 90 ++++++++++++++++++++++++++++++++++++++-----------
>>>  1 file changed, 70 insertions(+), 20 deletions(-)
>>>
>>> diff --git a/tools/microcode-tool.py b/tools/microcode-tool.py
>>> index 003716d..71c2e91 100755
>>> --- a/tools/microcode-tool.py
>>> +++ b/tools/microcode-tool.py
>>> @@ -76,6 +76,35 @@ def ParseFile(fname):
>>>          microcodes[name] = Microcode(name, data)
>>>      return date, license_text, microcodes
>>>
>>> +def ParseHeaderFiles(fname_list):
>>> +    """Parse a list of header files and return the component parts
>>> +
>>> +    Args:
>>> +        fname_list: List of files to parse
>>> +    Returns:
>>> +            date:         String containing date from the file's header
>>> +            license_text: List of text lines for the license file
>>> +            microcodes:   List of Microcode objects from the file
>>> +    """
>>> +    microcodes = {}
>>> +    license_text = []
>>> +    date = ''
>>> +    name = None
>>> +    for fname in fname_list:
>>> +        name = os.path.basename(fname).lower()
>>> +        name = os.path.splitext(name)[0]
>>> +        data = []
>>> +        with open(fname) as fd:
>>> +            for line in fd:
>>> +                line = line.rstrip()
>>> +
>>> +                # Omit anything after the last comma
>>> +                words = line.split(',')[:-1]
>>> +                data += [word + ',' for word in words]
>>> +        microcodes[name] = Microcode(name, data)
>>> +    return date, license_text, microcodes
>>> +
>>> +
>>>  def List(date, microcodes, model):
>>>      """List the available microcode chunks
>>>
>>> @@ -129,13 +158,13 @@ def FindMicrocode(microcodes, model):
>>>              break
>>>      return found, tried
>>>
>>> -def CreateFile(date, license_text, mcode, outfile):
>>> +def CreateFile(date, license_text, mcodes, outfile):
>>>      """Create a microcode file in U-Boot's .dtsi format
>>>
>>>      Args:
>>>          date:       String containing date of original microcode file
>>>          license:    List of text lines for the license file
>>> -        mcode:      Microcode object to write
>>> +        mcodes:      Microcode objects to write (normally only 1)
>>>          outfile:    Filename to write to ('-' for stdout)
>>>      """
>>>      out = '''/*%s
>>> @@ -159,15 +188,22 @@ intel,processor-flags = <%#x>;
>>>  data = <%s
>>>  \t>;'''
>>>      words = ''
>>> -    for i in range(len(mcode.words)):
>>> -        if not (i & 3):
>>> -            words += '\n'
>>> -        val = mcode.words[i]
>>> -        # Change each word so it will be little-endian in the FDT
>>> -        # This data is needed before RAM is available on some platforms so we
>>> -        # cannot do an endianness swap on boot.
>>> -        val = struct.unpack("<I", struct.pack(">I", val))[0]
>>> -        words += '\t%#010x' % val
>>> +    add_comments = len(mcodes) > 1
>>> +    for mcode in mcodes:
>>> +        if add_comments:
>>> +            words += '\n/* %s */' % mcode.name
>>> +        for i in range(len(mcode.words)):
>>> +            if not (i & 3):
>>> +                words += '\n'
>>> +            val = mcode.words[i]
>>> +            # Change each word so it will be little-endian in the FDT
>>> +            # This data is needed before RAM is available on some platforms so
>>> +            # we cannot do an endianness swap on boot.
>>> +            val = struct.unpack("<I", struct.pack(">I", val))[0]
>>> +            words += '\t%#010x' % val
>>> +
>>> +    # Use the first microcode for the headers
>>> +    mcode = mcodes[0]
>>>
>>>      # Take care to avoid adding a space before a tab
>>>      text = ''
>>> @@ -187,8 +223,8 @@ data = <%s
>>>                  print >> sys.stderr, "Creating directory '%s'" % MICROCODE_DIR
>>>                  os.makedirs(MICROCODE_DIR)
>>>              outfile = os.path.join(MICROCODE_DIR, mcode.name + '.dtsi')
>>> -            print >> sys.stderr, "Writing microcode for '%s' to '%s'" % (
>>> -                     mcode.name, outfile)
>>> +        print >> sys.stderr, "Writing microcode for '%s' to '%s'" % (
>>> +                ', '.join([mcode.name for mcode in mcodes]), outfile)
>>>          with open(outfile, 'w') as fd:
>>>              print >> fd, out % tuple(args)
>>>
>>> @@ -198,8 +234,12 @@ def MicrocodeTool():
>>>      parser = OptionParser()
>>>      parser.add_option('-d', '--mcfile', type='string', action='store',
>>>                      help='Name of microcode.dat file')
>>> +    parser.add_option('-H', '--headerfile', type='string', action='append',
>>> +                    help='Name of .h file containing microcode')
>>>      parser.add_option('-m', '--model', type='string', action='store',
>>> -                    help='Model name to extract')
>>> +                    help="Model name to extract ('all' for all)")
>>> +    parser.add_option('-M', '--multiple', type='string', action='store',
>>> +                    help="Allow output of multiple models")
>>>      parser.add_option('-o', '--outfile', type='string', action='store',
>>>                      help='Filename to use for output (- for stdout), default is'
>>>                      ' %s/<name>.dtsi' % MICROCODE_DIR)
>>> @@ -224,9 +264,14 @@ def MicrocodeTool():
>>>      if cmd not in commands:
>>>          parser.error("Unknown command '%s'" % cmd)
>>>
>>> -    if not options.mcfile:
>>> -        parser.error('You must specify a microcode file')
>>> -    date, license_text, microcodes = ParseFile(options.mcfile)
>>> +    if (not not options.mcfile) != (not not options.mcfile):
>>> +        parser.error("You must specify either header files or a microcode file, not both")
>>> +    if options.headerfile:
>>> +        date, license_text, microcodes = ParseHeaderFiles(options.headerfile)
>>> +    elif options.mcfile:
>>> +        date, license_text, microcodes = ParseFile(options.mcfile)
>>> +    else:
>>> +        parser.error('You must specify a microcode file (or header files)')
>>>
>>>      if cmd == 'list':
>>>          List(date, microcodes, options.model)
>>> @@ -236,16 +281,21 @@ def MicrocodeTool():
>>>          if not options.model:
>>>              parser.error('You must specify a model to create')
>>>          model = options.model.lower()
>>> -        mcode_list, tried = FindMicrocode(microcodes, model)
>>> +        if options.model == 'all':
>>> +            options.multiple = True
>>> +            mcode_list = microcodes.values()
>>> +            tried = []
>>> +        else:
>>> +            mcode_list, tried = FindMicrocode(microcodes, model)
>>>          if not mcode_list:
>>>              parser.error("Unknown model '%s' (%s) - try 'list' to list" %
>>>                          (model, ', '.join(tried)))
>>> -        if len(mcode_list) > 1:
>>> +        if not options.multiple and len(mcode_list) > 1:
>>>              parser.error("Ambiguous model '%s' (%s) matched %s - try 'list' "
>>>                          "to list or specify a particular file" %
>>>                          (model, ', '.join(tried),
>>>                          ', '.join([m.name for m in mcode_list])))
>>> -        CreateFile(date, license_text, mcode_list[0], options.outfile)
>>> +        CreateFile(date, license_text, mcode_list, options.outfile)
>>>      else:
>>>          parser.error("Unknown command '%s'" % cmd)
>>>
>>> --
>>
>> My testing results show that, compared to '-d microcode.dat' approach,
>> generated microcode.dtsi using '-H' does not have license header and
>> date set. Is this intentional?
>
> Not really, but the header I tested with has no license info.
>

OK.

> I suspect we could enable use of -d also to pick this up. But we still
> wouldn't get the date. I'm not sure what automation we should have for
> this case.
>

Specifying '-d' might be confusing. Let's just go with current
implementation without license and date.

Regards,
Bin

[U-Boot] [PATCH 14/23] x86: Move common FSP functions into a common file

[Bin Meng]

Hi Simon,

On Tue, Jan 27, 2015 at 11:15 PM, Simon Glass <sjg@chromium.org> wrote:
> Hi Bin,
>
> On 27 January 2015 at 05:20, Bin Meng <bmeng.cn@gmail.com> wrote:
>> Hi Simon,
>>
>> On Tue, Jan 27, 2015 at 9:23 AM, Simon Glass <sjg@chromium.org> wrote:
>>> Since these board functions seem to be the same for all boards which use
>>> FSP, move them into a common file. We can adjust this later if future FSPs
>>> need more flexibility.
>>>
>>> Signed-off-by: Simon Glass <sjg@chromium.org>
>>> ---
>>>
>>>  arch/x86/cpu/queensbay/tnc.c      | 27 ------------
>>>  arch/x86/cpu/queensbay/tnc_pci.c  | 15 -------
>>>  arch/x86/cpu/queensbay/topcliff.c | 32 +-------------
>>>  arch/x86/include/asm/u-boot-x86.h | 17 ++++++++
>>>  arch/x86/lib/fsp/Makefile         |  1 +
>>>  arch/x86/lib/fsp/fsp_common.c     | 88 +++++++++++++++++++++++++++++++++++++++
>>>  6 files changed, 108 insertions(+), 72 deletions(-)
>>>  create mode 100644 arch/x86/lib/fsp/fsp_common.c
>>>
>>> diff --git a/arch/x86/cpu/queensbay/tnc.c b/arch/x86/cpu/queensbay/tnc.c
>>> index f9b3bfa..30ab725 100644
>>> --- a/arch/x86/cpu/queensbay/tnc.c
>>> +++ b/arch/x86/cpu/queensbay/tnc.c
>>> @@ -43,30 +43,3 @@ int arch_cpu_init(void)
>>>
>>>         return 0;
>>>  }
>>> -
>>> -int print_cpuinfo(void)
>>> -{
>>> -       post_code(POST_CPU_INFO);
>>> -       return default_print_cpuinfo();
>>> -}
>>> -
>>> -void reset_cpu(ulong addr)
>>> -{
>>> -       /* cold reset */
>>> -       outb(0x06, PORT_RESET);
>>> -}
>>> -
>>> -void board_final_cleanup(void)
>>> -{
>>> -       u32 status;
>>> -
>>> -       /* call into FspNotify */
>>> -       debug("Calling into FSP (notify phase INIT_PHASE_BOOT): ");
>>> -       status = fsp_notify(NULL, INIT_PHASE_BOOT);
>>> -       if (status != FSP_SUCCESS)
>>> -               debug("fail, error code %x\n", status);
>>> -       else
>>> -               debug("OK\n");
>>> -
>>> -       return;
>>> -}
>>> diff --git a/arch/x86/cpu/queensbay/tnc_pci.c b/arch/x86/cpu/queensbay/tnc_pci.c
>>> index 9b0b725..6c291f9 100644
>>> --- a/arch/x86/cpu/queensbay/tnc_pci.c
>>> +++ b/arch/x86/cpu/queensbay/tnc_pci.c
>>> @@ -44,18 +44,3 @@ void board_pci_setup_hose(struct pci_controller *hose)
>>>
>>>         hose->region_count = 4;
>>>  }
>>> -
>>> -int board_pci_post_scan(struct pci_controller *hose)
>>> -{
>>> -       u32 status;
>>> -
>>> -       /* call into FspNotify */
>>> -       debug("Calling into FSP (notify phase INIT_PHASE_PCI): ");
>>> -       status = fsp_notify(NULL, INIT_PHASE_PCI);
>>> -       if (status != FSP_SUCCESS)
>>> -               debug("fail, error code %x\n", status);
>>> -       else
>>> -               debug("OK\n");
>>> -
>>> -       return 0;
>>> -}
>>> diff --git a/arch/x86/cpu/queensbay/topcliff.c b/arch/x86/cpu/queensbay/topcliff.c
>>> index b01422a..25032cc 100644
>>> --- a/arch/x86/cpu/queensbay/topcliff.c
>>> +++ b/arch/x86/cpu/queensbay/topcliff.c
>>> @@ -5,43 +5,15 @@
>>>   */
>>>
>>>  #include <common.h>
>>> -#include <errno.h>
>>> -#include <malloc.h>
>>> -#include <pci.h>
>>>  #include <pci_ids.h>
>>> -#include <sdhci.h>
>>>
>>>  static struct pci_device_id mmc_supported[] = {
>>>         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TCF_SDIO_0 },
>>>         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TCF_SDIO_1 },
>>> -       { }
>>>  };
>>>
>>>  int cpu_mmc_init(bd_t *bis)
>>>  {
>>> -       struct sdhci_host *mmc_host;
>>> -       pci_dev_t devbusfn;
>>> -       u32 iobase;
>>> -       int ret;
>>> -       int i;
>>> -
>>> -       for (i = 0; i < ARRAY_SIZE(mmc_supported); i++) {
>>> -               devbusfn =  pci_find_devices(mmc_supported, i);
>>> -               if (devbusfn == -1)
>>> -                       return -ENODEV;
>>> -
>>> -               mmc_host = (struct sdhci_host *)malloc(sizeof(struct sdhci_host));
>>> -               if (!mmc_host)
>>> -                       return -ENOMEM;
>>> -
>>> -               mmc_host->name = "Topcliff SDHCI";
>>> -               pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_0, &iobase);
>>> -               mmc_host->ioaddr = (void *)iobase;
>>> -               mmc_host->quirks = 0;
>>> -               ret = add_sdhci(mmc_host, 0, 0);
>>> -               if (ret)
>>> -                       return ret;
>>> -       }
>>> -
>>> -       return 0;
>>> +       return fsp_cpu_mmc_init("Topcliff SDHCI", mmc_supported,
>>> +                               ARRAY_SIZE(mmc_supported));
>>>  }
>>
>> I don't think this function should be moved to fsp_common.c as it has
>> nothing related to FSP. We can move this whole function to
>> drivers/mmc/, something like intel_mmc.c or intel_sdhc.c.
>
> How about pci_mmc.c if it is generic to PCI?
>

Sounds good.

[snip]

Regards,
Bin

[U-Boot] [PATCH 20/23] scsi: bootstage: Measure time taken to scan the bus

[Bin Meng]

Hi Rob,

On Wed, Jan 28, 2015 at 1:38 AM, Rob Herring <robherring2@gmail.com> wrote:
> On Mon, Jan 26, 2015 at 7:23 PM, Simon Glass <sjg@chromium.org> wrote:
>> On some hardware this time can be significant. Add bootstage support for
>> measuring this. The result can be obtained using 'bootstage report' or
>> passed on to the Linux via the device tree.
>>
>> Signed-off-by: Simon Glass <sjg@chromium.org>
>> ---
>>
>>  common/cmd_scsi.c   | 2 ++
>>  include/bootstage.h | 1 +
>>  2 files changed, 3 insertions(+)
>>
>> diff --git a/common/cmd_scsi.c b/common/cmd_scsi.c
>> index cbc107e..a0a62eb 100644
>> --- a/common/cmd_scsi.c
>> +++ b/common/cmd_scsi.c
>> @@ -217,8 +217,10 @@ void scsi_init(void)
>>                        (busdevfunc >> 8) & 0x7);
>>         }
>>  #endif
>> +       bootstage_start(BOOTSTAGE_ID_ACCUM_SCSI, "ahci");
>>         scsi_low_level_init(busdevfunc);
>>         scsi_scan(1);
>> +       bootstage_accum(BOOTSTAGE_ID_ACCUM_SCSI);
>
> This does not cover the case if the platform calls scsi_scan at boot.
> The first time is the important one as that will include disk spin-up
> time.
>
> Perhaps they shouldn't be and "scsi scan" should always be in boot scripts.
>

scsi_init() is called in common/board_r.c, which already covers the
boot scan case.

Regards,
Bin

[U-Boot] [PATCH 20/23] scsi: bootstage: Measure time taken to scan the bus

[Simon Glass]

Hi,

On 27 January 2015 at 18:20, Bin Meng <bmeng.cn@gmail.com> wrote:
> Hi Rob,
>
> On Wed, Jan 28, 2015 at 1:38 AM, Rob Herring <robherring2@gmail.com> wrote:
>> On Mon, Jan 26, 2015 at 7:23 PM, Simon Glass <sjg@chromium.org> wrote:
>>> On some hardware this time can be significant. Add bootstage support for
>>> measuring this. The result can be obtained using 'bootstage report' or
>>> passed on to the Linux via the device tree.
>>>
>>> Signed-off-by: Simon Glass <sjg@chromium.org>
>>> ---
>>>
>>>  common/cmd_scsi.c   | 2 ++
>>>  include/bootstage.h | 1 +
>>>  2 files changed, 3 insertions(+)
>>>
>>> diff --git a/common/cmd_scsi.c b/common/cmd_scsi.c
>>> index cbc107e..a0a62eb 100644
>>> --- a/common/cmd_scsi.c
>>> +++ b/common/cmd_scsi.c
>>> @@ -217,8 +217,10 @@ void scsi_init(void)
>>>                        (busdevfunc >> 8) & 0x7);
>>>         }
>>>  #endif
>>> +       bootstage_start(BOOTSTAGE_ID_ACCUM_SCSI, "ahci");
>>>         scsi_low_level_init(busdevfunc);
>>>         scsi_scan(1);
>>> +       bootstage_accum(BOOTSTAGE_ID_ACCUM_SCSI);
>>
>> This does not cover the case if the platform calls scsi_scan at boot.
>> The first time is the important one as that will include disk spin-up
>> time.
>>
>> Perhaps they shouldn't be and "scsi scan" should always be in boot scripts.
>>
>
> scsi_init() is called in common/board_r.c, which already covers the
> boot scan case.

I think platform data is missing. Rob if you are able to test this I
could send an updated patch?

Regards,
Simon

[U-Boot] [PATCH 19/23] x86: spi: Support ValleyView in ICH SPI driver

[Simon Glass]

Hi Bin,

On 27 January 2015 at 07:00, Bin Meng <bmeng.cn@gmail.com> wrote:
> Hi Simon,
>
> On Tue, Jan 27, 2015 at 9:23 AM, Simon Glass <sjg@chromium.org> wrote:
>> The base address is found in a different way and the protection bit is also
>> in a different place. Otherwise it is very similar.
>>
>> Signed-off-by: Simon Glass <sjg@chromium.org>
>> ---
>>
>>  drivers/spi/ich.c | 56 ++++++++++++++++++++++++++++++++++++++++---------------
>>  drivers/spi/ich.h | 11 ++++++-----
>>  2 files changed, 47 insertions(+), 20 deletions(-)

Just a note on this one...for v2 I have done nothing. I think we
should move it to device tree as you say but it needs some more
thought, as we have register offsets and device types to think about.
I will try a few things and test on link also. Once I have this I will
send a v3. So this patch will have to sit here until that is done,
hopefully only a few days.

Thanks for the quick reviews!

Regards,
Simon

[U-Boot] [PATCH 19/23] x86: spi: Support ValleyView in ICH SPI driver

[Bin Meng]

Hi Simon,

On Wed, Jan 28, 2015 at 1:17 PM, Simon Glass <sjg@chromium.org> wrote:
> Hi Bin,
>
> On 27 January 2015 at 07:00, Bin Meng <bmeng.cn@gmail.com> wrote:
>> Hi Simon,
>>
>> On Tue, Jan 27, 2015 at 9:23 AM, Simon Glass <sjg@chromium.org> wrote:
>>> The base address is found in a different way and the protection bit is also
>>> in a different place. Otherwise it is very similar.
>>>
>>> Signed-off-by: Simon Glass <sjg@chromium.org>
>>> ---
>>>
>>>  drivers/spi/ich.c | 56 ++++++++++++++++++++++++++++++++++++++++---------------
>>>  drivers/spi/ich.h | 11 ++++++-----
>>>  2 files changed, 47 insertions(+), 20 deletions(-)
>
> Just a note on this one...for v2 I have done nothing. I think we
> should move it to device tree as you say but it needs some more
> thought, as we have register offsets and device types to think about.
> I will try a few things and test on link also. Once I have this I will
> send a v3. So this patch will have to sit here until that is done,
> hopefully only a few days.
>

OK, I think we can just apply this patch for now along with other
patches in this series. We can revisit this driver when adding DT and
DM support.

> Thanks for the quick reviews!
>

You are welcome!

Regards,
Bin

[U-Boot] [PATCH 19/23] x86: spi: Support ValleyView in ICH SPI driver

[Simon Glass]

Hi Bin,

On 27 January 2015 at 23:02, Bin Meng <bmeng.cn@gmail.com> wrote:
> Hi Simon,
>
> On Wed, Jan 28, 2015 at 1:17 PM, Simon Glass <sjg@chromium.org> wrote:
>> Hi Bin,
>>
>> On 27 January 2015 at 07:00, Bin Meng <bmeng.cn@gmail.com> wrote:
>>> Hi Simon,
>>>
>>> On Tue, Jan 27, 2015 at 9:23 AM, Simon Glass <sjg@chromium.org> wrote:
>>>> The base address is found in a different way and the protection bit is also
>>>> in a different place. Otherwise it is very similar.
>>>>
>>>> Signed-off-by: Simon Glass <sjg@chromium.org>
>>>> ---
>>>>
>>>>  drivers/spi/ich.c | 56 ++++++++++++++++++++++++++++++++++++++++---------------
>>>>  drivers/spi/ich.h | 11 ++++++-----
>>>>  2 files changed, 47 insertions(+), 20 deletions(-)
>>
>> Just a note on this one...for v2 I have done nothing. I think we
>> should move it to device tree as you say but it needs some more
>> thought, as we have register offsets and device types to think about.
>> I will try a few things and test on link also. Once I have this I will
>> send a v3. So this patch will have to sit here until that is done,
>> hopefully only a few days.
>>
>
> OK, I think we can just apply this patch for now along with other
> patches in this series. We can revisit this driver when adding DT and
> DM support.

Oh OK we can do it that way. I actually have some partial work to
convert the ICH driver to DM, so I'll go back to that soon.

Applied to u-boot-x86.

Regards,
Simon