From mboxrd@z Thu Jan 1 00:00:00 1970 From: Mike Turquette Subject: Re: [PATCH] clk: ti: Fix FAPLL parent enable bit handling Date: Wed, 25 Feb 2015 12:07:52 -0800 Message-ID: <20150225200752.421.26748@quantum> References: <20150128170048.GO28663@atomide.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <20150128170048.GO28663@atomide.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=m.gmane.org@lists.infradead.org To: Tony Lindgren Cc: linux-omap@vger.kernel.org, Dan Carpenter , linux-arm-kernel@lists.infradead.org, Brian Hutchinson List-Id: linux-omap@vger.kernel.org Quoting Tony Lindgren (2015-01-28 09:00:49) > Commit 163152cbbe32 ("clk: ti: Add support for FAPLL on dm816x") > added basic support for the FAPLL on dm818x, but has a bug for the > parent PLL enable bit. The FAPLL_MAIN_PLLEN is defined as BIT(3) > but the code is doing a shift on it. > > This means the parent PLL won't get disabled even if all it's child > synthesizers are disabled. > > Reported-by: Dan Carpenter > Cc: Brian Hutchinson > Signed-off-by: Tony Lindgren Missed this one for 3.20. Applied to clk-fixes. Regards, Mike > > --- a/drivers/clk/ti/fapll.c > +++ b/drivers/clk/ti/fapll.c > @@ -84,7 +84,7 @@ static int ti_fapll_enable(struct clk_hw *hw) > struct fapll_data *fd = to_fapll(hw); > u32 v = readl_relaxed(fd->base); > > - v |= (1 << FAPLL_MAIN_PLLEN); > + v |= FAPLL_MAIN_PLLEN; > writel_relaxed(v, fd->base); > > return 0; > @@ -95,7 +95,7 @@ static void ti_fapll_disable(struct clk_hw *hw) > struct fapll_data *fd = to_fapll(hw); > u32 v = readl_relaxed(fd->base); > > - v &= ~(1 << FAPLL_MAIN_PLLEN); > + v &= ~FAPLL_MAIN_PLLEN; > writel_relaxed(v, fd->base); > } > > @@ -104,7 +104,7 @@ static int ti_fapll_is_enabled(struct clk_hw *hw) > struct fapll_data *fd = to_fapll(hw); > u32 v = readl_relaxed(fd->base); > > - return v & (1 << FAPLL_MAIN_PLLEN); > + return v & FAPLL_MAIN_PLLEN; > } > > static unsigned long ti_fapll_recalc_rate(struct clk_hw *hw, From mboxrd@z Thu Jan 1 00:00:00 1970 From: mturquette@linaro.org (Mike Turquette) Date: Wed, 25 Feb 2015 12:07:52 -0800 Subject: [PATCH] clk: ti: Fix FAPLL parent enable bit handling In-Reply-To: <20150128170048.GO28663@atomide.com> References: <20150128170048.GO28663@atomide.com> Message-ID: <20150225200752.421.26748@quantum> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org Quoting Tony Lindgren (2015-01-28 09:00:49) > Commit 163152cbbe32 ("clk: ti: Add support for FAPLL on dm816x") > added basic support for the FAPLL on dm818x, but has a bug for the > parent PLL enable bit. The FAPLL_MAIN_PLLEN is defined as BIT(3) > but the code is doing a shift on it. > > This means the parent PLL won't get disabled even if all it's child > synthesizers are disabled. > > Reported-by: Dan Carpenter > Cc: Brian Hutchinson > Signed-off-by: Tony Lindgren Missed this one for 3.20. Applied to clk-fixes. Regards, Mike > > --- a/drivers/clk/ti/fapll.c > +++ b/drivers/clk/ti/fapll.c > @@ -84,7 +84,7 @@ static int ti_fapll_enable(struct clk_hw *hw) > struct fapll_data *fd = to_fapll(hw); > u32 v = readl_relaxed(fd->base); > > - v |= (1 << FAPLL_MAIN_PLLEN); > + v |= FAPLL_MAIN_PLLEN; > writel_relaxed(v, fd->base); > > return 0; > @@ -95,7 +95,7 @@ static void ti_fapll_disable(struct clk_hw *hw) > struct fapll_data *fd = to_fapll(hw); > u32 v = readl_relaxed(fd->base); > > - v &= ~(1 << FAPLL_MAIN_PLLEN); > + v &= ~FAPLL_MAIN_PLLEN; > writel_relaxed(v, fd->base); > } > > @@ -104,7 +104,7 @@ static int ti_fapll_is_enabled(struct clk_hw *hw) > struct fapll_data *fd = to_fapll(hw); > u32 v = readl_relaxed(fd->base); > > - return v & (1 << FAPLL_MAIN_PLLEN); > + return v & FAPLL_MAIN_PLLEN; > } > > static unsigned long ti_fapll_recalc_rate(struct clk_hw *hw,