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From: Damien Lespiau <damien.lespiau@intel.com>
To: Michel Thierry <michel.thierry@intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 00/12] PPGTT with 48b addressing
Date: Tue, 3 Mar 2015 13:52:09 +0000	[thread overview]
Message-ID: <20150303135209.GB12982@strange.icx.intel.com> (raw)
In-Reply-To: <1424454366-19006-1-git-send-email-michel.thierry@intel.com>

On Fri, Feb 20, 2015 at 05:45:54PM +0000, Michel Thierry wrote:
> These patches rely on "PPGTT dynamic page allocations", currently under review,
> to provide GEN8 dynamic page table support with 64b addresses. As the review
> progresses, these patches may be combined.
> 
> In order expand the GPU address space, a 4th level translation is added, the
> Page Map Level 4 (PML4). This PML4 has 256 PML4 Entries (PML4E), PML4[0-255],
> each pointing to a PDP.
> 
> For now, this feature will only be available in BDW, in LRC submission mode
> (execlists) and when i915.enable_ppgtt=3 is set.
> Also note that this expanded address space is only available for full PPGTT,
> aliasing PPGTT remains 32b.

FWIW, I don't think it sounds like a good idea to enable 48bits address
spaces without having implemented Wa32bitGeneralStateOffset and
Wa32bitInstructionBaseOffset.

-- 
Damien
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      parent reply	other threads:[~2015-03-03 13:52 UTC|newest]

Thread overview: 32+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-02-20 17:45 [PATCH 00/12] PPGTT with 48b addressing Michel Thierry
2015-02-20 17:45 ` [PATCH 01/12] drm/i915/bdw: Make pdp allocation more dynamic Michel Thierry
2015-03-03 11:48   ` akash goel
2015-03-18 10:15     ` Michel Thierry
2015-02-20 17:45 ` [PATCH 02/12] drm/i915/bdw: Abstract PDP usage Michel Thierry
2015-03-03 12:16   ` akash goel
2015-03-18 10:16     ` Michel Thierry
2015-03-04  3:07   ` akash goel
2015-02-20 17:45 ` [PATCH 03/12] drm/i915/bdw: Add dynamic page trace events Michel Thierry
2015-02-24 10:56   ` Daniel Vetter
2015-02-24 10:59   ` Daniel Vetter
2015-02-20 17:45 ` [PATCH 04/12] drm/i915/bdw: Add ppgtt info for dynamic pages Michel Thierry
2015-03-03 12:23   ` akash goel
2015-03-18 10:17     ` Michel Thierry
2015-02-20 17:45 ` [PATCH 05/12] drm/i915/bdw: implement alloc/free for 4lvl Michel Thierry
2015-03-03 12:55   ` akash goel
2015-03-04 13:00     ` Daniel Vetter
2015-03-04  2:48   ` akash goel
2015-02-20 17:46 ` [PATCH 06/12] drm/i915/bdw: Add 4 level switching infrastructure Michel Thierry
2015-03-03 13:01   ` akash goel
2015-03-04 13:08     ` Daniel Vetter
2015-02-20 17:46 ` [PATCH 07/12] drm/i915/bdw: Support 64 bit PPGTT in lrc mode Michel Thierry
2015-03-03 13:08   ` akash goel
2015-02-20 17:46 ` [PATCH 08/12] drm/i915/bdw: Generalize PTE writing for GEN8 PPGTT Michel Thierry
2015-02-20 17:46 ` [PATCH 09/12] drm/i915: Plumb sg_iter through va allocation ->maps Michel Thierry
2015-02-20 17:46 ` [PATCH 10/12] drm/i915/bdw: Add 4 level support in insert_entries and clear_range Michel Thierry
2015-03-03 16:39   ` akash goel
2015-02-20 17:46 ` [PATCH 11/12] drm/i915: Expand error state's address width to 64b Michel Thierry
2015-03-03 16:42   ` akash goel
2015-02-20 17:46 ` [PATCH 12/12] drm/i915/bdw: Flip the 48b switch Michel Thierry
2015-02-24 10:54 ` [PATCH 00/12] PPGTT with 48b addressing Daniel Vetter
2015-03-03 13:52 ` Damien Lespiau [this message]

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