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From: "Edgar E. Iglesias" <edgar.iglesias@gmail.com>
To: Julien Grall <julien.grall@linaro.org>
Cc: tim@xen.org, stefano.stabellini@citrix.com,
	ian.campbell@citrix.com, xen-devel@lists.xen.org
Subject: Re: [PATCH v3 0/2] Add support for Xilinx ZynqMP SoC
Date: Wed, 11 Mar 2015 09:59:42 +1000	[thread overview]
Message-ID: <20150310235942.GA16866@toto> (raw)
In-Reply-To: <54FED5C2.50903@linaro.org>

On Tue, Mar 10, 2015 at 11:30:10AM +0000, Julien Grall wrote:
> Hello Edgar,
> 
> Thank you for adding support of the ZynqMP.
> 
> On 10/03/15 02:49, Edgar E. Iglesias wrote:
> > From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
> > 
> > Adds support for the Cadence UART in Xilinx ZynqMP. The
> > rest of the ZynqMP platform is discovered via device-tree.
> 
> Did you make sure that the default grant table range (0xb0000000 -
> 0xb0020000) don't overlap with an hardware region?

No I didn't, thanks for pointing that out. I need to move these to
another address.

So now I'm back to needing platform specific code. Long term,
Maybe it would make sense making the grant table range somehow
configurable via DT?

Anyway, I'll send a v4 with the platform code to move the gnt
into a reserved area in the memory map.

Thanks,
Edgar


> 
> Regards,
> 
> -- 
> Julien Grall

  reply	other threads:[~2015-03-10 23:59 UTC|newest]

Thread overview: 8+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-03-10  2:49 [PATCH v3 0/2] Add support for Xilinx ZynqMP SoC Edgar E. Iglesias
2015-03-10  2:49 ` [PATCH v3 1/2] xen/arm: Add Cadence UART driver Edgar E. Iglesias
2015-03-10 11:31   ` Julien Grall
2015-03-10  2:49 ` [PATCH v3 2/2] xen/arm: Add Xilinx ZynqMP early printk support Edgar E. Iglesias
2015-03-10 11:30 ` [PATCH v3 0/2] Add support for Xilinx ZynqMP SoC Julien Grall
2015-03-10 23:59   ` Edgar E. Iglesias [this message]
2015-03-11  9:46     ` Ian Campbell
2015-03-11 10:09       ` Edgar E. Iglesias

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