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From: Marek Vasut <marex@denx.de>
To: u-boot@lists.denx.de
Subject: [U-Boot] [RFC PATCH] usb: dwc2: handle bcm2835 phys->virt address translations
Date: Fri, 13 Mar 2015 15:30:20 +0100	[thread overview]
Message-ID: <201503131530.20684.marex@denx.de> (raw)
In-Reply-To: <1426227189-30488-1-git-send-email-swarren@wwwdotorg.org>

On Friday, March 13, 2015 at 07:13:09 AM, Stephen Warren wrote:
> BCM2835 bus addresses use the top 2 bits to determine whether peripherals
> use or bypass the GPU L1 and L2 cache. BCM2835-ARM-Peripherals.pdf states
> that:
> 
> 0: L1 & L2 cached
> 4: L2 cache coherent (non allocaing)
> 8: L2 cached only
> c: Direct uncached.

Caches aren't working on BCM2xxx or what's the reason for this hack ?
Or are these different (not on-CPU) caches we're talking about (yes,
I did notice the GPU Lx cache stuff)?

Best regards,
Marek Vasut

  reply	other threads:[~2015-03-13 14:30 UTC|newest]

Thread overview: 15+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-03-13  6:13 [U-Boot] [RFC PATCH] usb: dwc2: handle bcm2835 phys->virt address translations Stephen Warren
2015-03-13 14:30 ` Marek Vasut [this message]
2015-03-13 16:35   ` Stephen Warren
2015-03-13 18:13     ` Marek Vasut
2015-03-13 18:39       ` Stephen Warren
2015-03-13 18:49         ` Marek Vasut
2015-03-13 17:02 ` Eric Anholt
2015-03-15 16:04 ` Stephen Warren
2015-03-15 18:20   ` Marek Vasut
2015-03-17  3:04     ` Stephen Warren
2015-03-17 14:57       ` popcorn mix
2015-03-17 17:29         ` Stephen Warren
2015-03-17 17:53           ` popcorn mix
2015-03-15 16:51 ` Stephen Warren
2015-03-15 18:20   ` Marek Vasut

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