From mboxrd@z Thu Jan 1 00:00:00 1970 From: Chao Peng Subject: Re: [PATCH 3/6] X86: improve psr scheduling code Date: Tue, 17 Mar 2015 17:12:14 +0800 Message-ID: <20150317091214.GE5371@pengc-linux.bj.intel.com> References: <1426241605-4114-1-git-send-email-chao.p.peng@linux.intel.com> <1426241605-4114-4-git-send-email-chao.p.peng@linux.intel.com> <5507189F020000780006A6B8@mail.emea.novell.com> Reply-To: Chao Peng Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Content-Disposition: inline In-Reply-To: <5507189F020000780006A6B8@mail.emea.novell.com> List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org To: Jan Beulich Cc: wei.liu2@citrix.com, Ian.Campbell@citrix.com, stefano.stabellini@eu.citrix.com, andrew.cooper3@citrix.com, Ian.Jackson@eu.citrix.com, xen-devel@lists.xen.org, will.auld@intel.com, keir@xen.org, dgdegra@tycho.nsa.gov List-Id: xen-devel@lists.xenproject.org On Mon, Mar 16, 2015 at 04:53:35PM +0000, Jan Beulich wrote: > >>> On 13.03.15 at 11:13, wrote: > > @@ -1473,11 +1471,10 @@ static void __context_switch(void) > > } > > vcpu_restore_fpu_eager(n); > > n->arch.ctxt_switch_to(n); > > - > > - if ( psr_cmt_enabled() && n->domain->arch.psr_rmid > 0 ) > > - psr_assoc_rmid(n->domain->arch.psr_rmid); > > } > > > > + psr_ctxt_switch_to(n->domain); > > But you now potentially do the MSR write despite it already being > the needed value (e.g. when switching between an idle vCPU and > another one also having RMID zero). Not really. The MSR is already updated lazily in psr_assoc_rmid(). Chao