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From: Andi Kleen <ak@linux.intel.com>
To: kan.liang@intel.com
Cc: a.p.zijlstra@chello.nl, linux-kernel@vger.kernel.org
Subject: Re: [PATCH 1/1] perf/x86/intel: Broadwell support LBR callstack
Date: Thu, 2 Apr 2015 12:45:55 -0700	[thread overview]
Message-ID: <20150402194555.GD15335@tassilo.jf.intel.com> (raw)
In-Reply-To: <1427962377-40955-1-git-send-email-kan.liang@intel.com>

On Thu, Apr 02, 2015 at 04:12:57AM -0400, kan.liang@intel.com wrote:
> From: Kan Liang <kan.liang@intel.com>
> 
> Same as Haswell, Broadwell also support LBR callstack.
> 
> Signed-off-by: Kan Liang <kan.liang@intel.com>

Thanks looks good.

Acked-by: Andi Kleen <ak@linux.intel.com>

-Andi


> ---
>  arch/x86/kernel/cpu/perf_event_intel.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/arch/x86/kernel/cpu/perf_event_intel.c b/arch/x86/kernel/cpu/perf_event_intel.c
> index fc6dbc4..4b61fe9 100644
> --- a/arch/x86/kernel/cpu/perf_event_intel.c
> +++ b/arch/x86/kernel/cpu/perf_event_intel.c
> @@ -2787,7 +2787,7 @@ __init int intel_pmu_init(void)
>  		hw_cache_extra_regs[C(NODE)][C(OP_WRITE)][C(RESULT_ACCESS)] = HSW_DEMAND_WRITE|
>  									      BDW_L3_MISS_LOCAL|HSW_SNOOP_DRAM;
>  
> -		intel_pmu_lbr_init_snb();
> +		intel_pmu_lbr_init_hsw();
>  
>  		x86_pmu.event_constraints = intel_bdw_event_constraints;
>  		x86_pmu.pebs_constraints = intel_hsw_pebs_event_constraints;
> -- 
> 1.8.3.1
> 

-- 
ak@linux.intel.com -- Speaking for myself only

  reply	other threads:[~2015-04-02 19:46 UTC|newest]

Thread overview: 3+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-04-02  8:12 [PATCH 1/1] perf/x86/intel: Broadwell support LBR callstack kan.liang
2015-04-02 19:45 ` Andi Kleen [this message]
2015-04-18 10:14 ` [tip:perf/urgent] perf/x86/intel: Add Broadwell support for the " tip-bot for Kan Liang

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