From mboxrd@z Thu Jan 1 00:00:00 1970 From: Tony Lindgren Subject: Re: ARM errata 430973 on multi platform kernels Date: Mon, 6 Apr 2015 10:42:45 -0700 Message-ID: <20150406174245.GJ18048@atomide.com> References: <551F186B.90608@gmail.com> <20150403225212.GY10805@atomide.com> <5520E2EE.4080302@gmail.com> <5521A438.1070008@gmail.com> <20150406151939.GG18048@atomide.com> <20150406154037.GI18048@atomide.com> <5522BEEF.2000405@gmail.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Return-path: Received: from muru.com ([72.249.23.125]:42397 "EHLO muru.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752784AbbDFRqc (ORCPT ); Mon, 6 Apr 2015 13:46:32 -0400 Content-Disposition: inline In-Reply-To: <5522BEEF.2000405@gmail.com> Sender: linux-omap-owner@vger.kernel.org List-Id: linux-omap@vger.kernel.org To: Ivaylo Dimitrov Cc: Matthijs van Duin , Sebastian Reichel , "linux-arm-kernel@lists.infradead.org" , "linux-omap@vger.kernel.org" , Pavel Machek * Ivaylo Dimitrov [150406 10:15]: > On 6.04.2015 18:40, Tony Lindgren wrote: > > > >Oops sorry, wrong numbers for errata above.. s/458693/430973/, here's > >a better version: > > > >1. For cortex-a8 revisions affected by 430973, we can do a custom > > cpu_v7_switch_mm function that always does flush BTAC/BTB. > > > > Why custom function, if IBE bit is zero, BTB invalidate instruction is a > NOP. Do you think that "mcr p15, 0, r2, c7, c5, 6" executed as a NOP will > put so much overhead, that it deserves a custom function? Hmm but it still seems to do something also on cortex-a8 r3p2 that is supposedly not affected by 430973.. Based on my tests so far, at least armhf running cpuburn-a8 in the background and doing apt-get update segfaults constantly without flush BTAC/BTB. This seems to be the case no matter how the aux ctrl reg bits are set.. This should be reproducable on any pandboard xm BTW. > >2. For HS cortex-a8 processors other than n900 affected by 430973, > > we need to implement functions similar to rx51_secure_update_aux_cr, > > the bootrom on n900 is different from TI HS omaps so the SMC call > > numbering may be different. > > > >3. For later cortex-a8 processors not affected by 430973, we need > > to clear IBE bit to avoid erratum 687067. > > > > Maybe it should be implemented something like: > > 1. if Cortex-A8, always execute invalidate BTB instruction in > cpu_v7_switch_mm This part still seems to need more investigating for why it's still needed also r3p2 as I describe above. Otherwise we may be hiding some other bug. > 2. For Cortex-A8 revisions affected by 430973, set IBE bit to 1, set it > to 0 for all others. That should happen as soon as possible, > otherwise kernel may crash on affected revisions if thumb- > compiled. Yes this makes sense. Regards, Tony From mboxrd@z Thu Jan 1 00:00:00 1970 From: tony@atomide.com (Tony Lindgren) Date: Mon, 6 Apr 2015 10:42:45 -0700 Subject: ARM errata 430973 on multi platform kernels In-Reply-To: <5522BEEF.2000405@gmail.com> References: <551F186B.90608@gmail.com> <20150403225212.GY10805@atomide.com> <5520E2EE.4080302@gmail.com> <5521A438.1070008@gmail.com> <20150406151939.GG18048@atomide.com> <20150406154037.GI18048@atomide.com> <5522BEEF.2000405@gmail.com> Message-ID: <20150406174245.GJ18048@atomide.com> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org * Ivaylo Dimitrov [150406 10:15]: > On 6.04.2015 18:40, Tony Lindgren wrote: > > > >Oops sorry, wrong numbers for errata above.. s/458693/430973/, here's > >a better version: > > > >1. For cortex-a8 revisions affected by 430973, we can do a custom > > cpu_v7_switch_mm function that always does flush BTAC/BTB. > > > > Why custom function, if IBE bit is zero, BTB invalidate instruction is a > NOP. Do you think that "mcr p15, 0, r2, c7, c5, 6" executed as a NOP will > put so much overhead, that it deserves a custom function? Hmm but it still seems to do something also on cortex-a8 r3p2 that is supposedly not affected by 430973.. Based on my tests so far, at least armhf running cpuburn-a8 in the background and doing apt-get update segfaults constantly without flush BTAC/BTB. This seems to be the case no matter how the aux ctrl reg bits are set.. This should be reproducable on any pandboard xm BTW. > >2. For HS cortex-a8 processors other than n900 affected by 430973, > > we need to implement functions similar to rx51_secure_update_aux_cr, > > the bootrom on n900 is different from TI HS omaps so the SMC call > > numbering may be different. > > > >3. For later cortex-a8 processors not affected by 430973, we need > > to clear IBE bit to avoid erratum 687067. > > > > Maybe it should be implemented something like: > > 1. if Cortex-A8, always execute invalidate BTB instruction in > cpu_v7_switch_mm This part still seems to need more investigating for why it's still needed also r3p2 as I describe above. Otherwise we may be hiding some other bug. > 2. For Cortex-A8 revisions affected by 430973, set IBE bit to 1, set it > to 0 for all others. That should happen as soon as possible, > otherwise kernel may crash on affected revisions if thumb- > compiled. Yes this makes sense. Regards, Tony