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* [PATCH] drm/i915/bdw: WaProgramL3SqcReg1Default
@ 2015-03-31 23:03 Rodrigo Vivi
  2015-04-01  5:52 ` shuang.he
                   ` (3 more replies)
  0 siblings, 4 replies; 9+ messages in thread
From: Rodrigo Vivi @ 2015-03-31 23:03 UTC (permalink / raw)
  To: intel-gfx; +Cc: Mika Kuoppala, Rodrigo Vivi

Program the default initial value of the L3SqcReg1 on BDW for performance

v2: Default confirmed and using intel_ring_emit_wa as Mika pointed out.

v3: Spec shows now a different value. It tells us to set to 0x784000
    instead the 0x610000 that is there already.
    Also rebased after a long time so using WA_WRITE now.

Cc: Mika Kuoppala <mika.kuoppala@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h         | 3 +++
 drivers/gpu/drm/i915/intel_ringbuffer.c | 3 +++
 2 files changed, 6 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 7e1a0fd9..7f8b69a 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5325,6 +5325,9 @@ enum skl_disp_power_wells {
 #define GEN7_L3SQCREG1				0xB010
 #define  VLV_B0_WA_L3SQCREG1_VALUE		0x00D30000
 
+#define GEN8_L3SQCREG1				0xB100
+#define  BDW_WA_L3SQCREG1_DEFAULT		0x784000
+
 #define GEN7_L3CNTLREG1				0xB01C
 #define  GEN7_WA_FOR_GEN7_L3_CONTROL			0x3C47FF8C
 #define  GEN7_L3AGDIS				(1<<19)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index abe062a..c02fccc 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -853,6 +853,9 @@ static int bdw_init_workarounds(struct intel_engine_cs *ring)
 			    GEN6_WIZ_HASHING_MASK,
 			    GEN6_WIZ_HASHING_16x4);
 
+	/* WaProgramL3SqcReg1Default:bdw */
+	WA_WRITE(GEN8_L3SQCREG1, BDW_WA_L3SQCREG1_DEFAULT);
+
 	return 0;
 }
 
-- 
2.1.0

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 9+ messages in thread
* Re: [PATCH] drm/i915/bdw: WaProgramL3SqcReg1Default
  2015-03-31 23:03 [PATCH] drm/i915/bdw: WaProgramL3SqcReg1Default Rodrigo Vivi
@ 2015-04-01  5:52 ` shuang.he
  2015-04-01  7:49 ` Jani Nikula
                   ` (2 subsequent siblings)
  3 siblings, 0 replies; 9+ messages in thread
From: shuang.he @ 2015-04-01  5:52 UTC (permalink / raw)
  To: shuang.he, ethan.gao, intel-gfx, rodrigo.vivi

Tested-By: PRC QA PRTS (Patch Regression Test System Contact: shuang.he@intel.com)
Task id: 6107
-------------------------------------Summary-------------------------------------
Platform          Delta          drm-intel-nightly          Series Applied
PNV                 -2              272/272              270/272
ILK                 -1              302/302              301/302
SNB                                  303/303              303/303
IVB                 -1              338/338              337/338
BYT                                  287/287              287/287
HSW                                  361/361              361/361
BDW                                  308/308              308/308
-------------------------------------Detailed-------------------------------------
Platform  Test                                drm-intel-nightly          Series Applied
 PNV  igt@gem_userptr_blits@coherency-sync      CRASH(2)PASS(3)      CRASH(1)PASS(1)
 PNV  igt@gem_tiled_pread_pwrite      FAIL(3)PASS(2)      FAIL(1)PASS(1)
*ILK  igt@gem_unfence_active_buffers      PASS(2)      DMESG_WARN(1)PASS(1)
(dmesg patch applied)drm:i915_hangcheck_elapsed[i915]]*ERROR*Hangcheck_timer_elapsed...bsd_ring_idle@Hangcheck timer elapsed... bsd ring idle
 IVB  igt@gem_storedw_batches_loop@normal      DMESG_WARN(1)PASS(1)      DMESG_WARN(1)PASS(1)
(dmesg patch applied)drm:i915_hangcheck_elapsed[i915]]*ERROR*Hangcheck_timer_elapsed...blitter_ring_idle@Hangcheck timer elapsed... blitter ring idle
Note: You need to pay more attention to line start with '*'
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 9+ messages in thread
* Re: [PATCH] drm/i915/bdw: WaProgramL3SqcReg1Default
  2015-03-31 23:03 [PATCH] drm/i915/bdw: WaProgramL3SqcReg1Default Rodrigo Vivi
  2015-04-01  5:52 ` shuang.he
@ 2015-04-01  7:49 ` Jani Nikula
  2015-04-01  8:31 ` Ville Syrjälä
  2015-04-01 15:41 ` Ville Syrjälä
  3 siblings, 0 replies; 9+ messages in thread
From: Jani Nikula @ 2015-04-01  7:49 UTC (permalink / raw)
  To: intel-gfx; +Cc: Rodrigo Vivi, Mika Kuoppala

On Wed, 01 Apr 2015, Rodrigo Vivi <rodrigo.vivi@intel.com> wrote:
> Program the default initial value of the L3SqcReg1 on BDW for performance
>
> v2: Default confirmed and using intel_ring_emit_wa as Mika pointed out.
>
> v3: Spec shows now a different value. It tells us to set to 0x784000
>     instead the 0x610000 that is there already.
>     Also rebased after a long time so using WA_WRITE now.
>
> Cc: Mika Kuoppala <mika.kuoppala@intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

Cc: stable?

BR,
Jani.


> ---
>  drivers/gpu/drm/i915/i915_reg.h         | 3 +++
>  drivers/gpu/drm/i915/intel_ringbuffer.c | 3 +++
>  2 files changed, 6 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 7e1a0fd9..7f8b69a 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -5325,6 +5325,9 @@ enum skl_disp_power_wells {
>  #define GEN7_L3SQCREG1				0xB010
>  #define  VLV_B0_WA_L3SQCREG1_VALUE		0x00D30000
>  
> +#define GEN8_L3SQCREG1				0xB100
> +#define  BDW_WA_L3SQCREG1_DEFAULT		0x784000
> +
>  #define GEN7_L3CNTLREG1				0xB01C
>  #define  GEN7_WA_FOR_GEN7_L3_CONTROL			0x3C47FF8C
>  #define  GEN7_L3AGDIS				(1<<19)
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index abe062a..c02fccc 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -853,6 +853,9 @@ static int bdw_init_workarounds(struct intel_engine_cs *ring)
>  			    GEN6_WIZ_HASHING_MASK,
>  			    GEN6_WIZ_HASHING_16x4);
>  
> +	/* WaProgramL3SqcReg1Default:bdw */
> +	WA_WRITE(GEN8_L3SQCREG1, BDW_WA_L3SQCREG1_DEFAULT);
> +
>  	return 0;
>  }
>  
> -- 
> 2.1.0
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Jani Nikula, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 9+ messages in thread
* Re: [PATCH] drm/i915/bdw: WaProgramL3SqcReg1Default
  2015-03-31 23:03 [PATCH] drm/i915/bdw: WaProgramL3SqcReg1Default Rodrigo Vivi
  2015-04-01  5:52 ` shuang.he
  2015-04-01  7:49 ` Jani Nikula
@ 2015-04-01  8:31 ` Ville Syrjälä
  2015-04-01 14:49   ` Vivi, Rodrigo
  2015-04-01 15:41 ` Ville Syrjälä
  3 siblings, 1 reply; 9+ messages in thread
From: Ville Syrjälä @ 2015-04-01  8:31 UTC (permalink / raw)
  To: Rodrigo Vivi; +Cc: intel-gfx, Mika Kuoppala

On Tue, Mar 31, 2015 at 04:03:21PM -0700, Rodrigo Vivi wrote:
> Program the default initial value of the L3SqcReg1 on BDW for performance
> 
> v2: Default confirmed and using intel_ring_emit_wa as Mika pointed out.
> 
> v3: Spec shows now a different value. It tells us to set to 0x784000
>     instead the 0x610000 that is there already.
>     Also rebased after a long time so using WA_WRITE now.

Told you so ;)

http://lists.freedesktop.org/archives/intel-gfx/2014-September/052999.html

> 
> Cc: Mika Kuoppala <mika.kuoppala@intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h         | 3 +++
>  drivers/gpu/drm/i915/intel_ringbuffer.c | 3 +++
>  2 files changed, 6 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 7e1a0fd9..7f8b69a 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -5325,6 +5325,9 @@ enum skl_disp_power_wells {
>  #define GEN7_L3SQCREG1				0xB010
>  #define  VLV_B0_WA_L3SQCREG1_VALUE		0x00D30000
>  
> +#define GEN8_L3SQCREG1				0xB100
> +#define  BDW_WA_L3SQCREG1_DEFAULT		0x784000
> +
>  #define GEN7_L3CNTLREG1				0xB01C
>  #define  GEN7_WA_FOR_GEN7_L3_CONTROL			0x3C47FF8C
>  #define  GEN7_L3AGDIS				(1<<19)
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index abe062a..c02fccc 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -853,6 +853,9 @@ static int bdw_init_workarounds(struct intel_engine_cs *ring)
>  			    GEN6_WIZ_HASHING_MASK,
>  			    GEN6_WIZ_HASHING_16x4);
>  
> +	/* WaProgramL3SqcReg1Default:bdw */
> +	WA_WRITE(GEN8_L3SQCREG1, BDW_WA_L3SQCREG1_DEFAULT);
> +
>  	return 0;
>  }
>  
> -- 
> 2.1.0
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Ville Syrjälä
Intel OTC
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 9+ messages in thread
* Re: [PATCH] drm/i915/bdw: WaProgramL3SqcReg1Default
  2015-04-01  8:31 ` Ville Syrjälä
@ 2015-04-01 14:49   ` Vivi, Rodrigo
  0 siblings, 0 replies; 9+ messages in thread
From: Vivi, Rodrigo @ 2015-04-01 14:49 UTC (permalink / raw)
  To: ville.syrjala; +Cc: intel-gfx, Kuoppala, Mika

On Wed, 2015-04-01 at 11:31 +0300, Ville Syrjälä wrote:
> On Tue, Mar 31, 2015 at 04:03:21PM -0700, Rodrigo Vivi wrote:
> > Program the default initial value of the L3SqcReg1 on BDW for performance
> > 
> > v2: Default confirmed and using intel_ring_emit_wa as Mika pointed out.
> > 
> > v3: Spec shows now a different value. It tells us to set to 0x784000
> >     instead the 0x610000 that is there already.
> >     Also rebased after a long time so using WA_WRITE now.
> 
> Told you so ;)
> 
> http://lists.freedesktop.org/archives/intel-gfx/2014-September/052999.html

ops, sorry! but now BSpec is updated at least...

So rv-b? :)
> 
> > 
> > Cc: Mika Kuoppala <mika.kuoppala@intel.com>
> > Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > ---
> >  drivers/gpu/drm/i915/i915_reg.h         | 3 +++
> >  drivers/gpu/drm/i915/intel_ringbuffer.c | 3 +++
> >  2 files changed, 6 insertions(+)
> > 
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index 7e1a0fd9..7f8b69a 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -5325,6 +5325,9 @@ enum skl_disp_power_wells {
> >  #define GEN7_L3SQCREG1				0xB010
> >  #define  VLV_B0_WA_L3SQCREG1_VALUE		0x00D30000
> >  
> > +#define GEN8_L3SQCREG1				0xB100
> > +#define  BDW_WA_L3SQCREG1_DEFAULT		0x784000
> > +
> >  #define GEN7_L3CNTLREG1				0xB01C
> >  #define  GEN7_WA_FOR_GEN7_L3_CONTROL			0x3C47FF8C
> >  #define  GEN7_L3AGDIS				(1<<19)
> > diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> > index abe062a..c02fccc 100644
> > --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> > +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> > @@ -853,6 +853,9 @@ static int bdw_init_workarounds(struct intel_engine_cs *ring)
> >  			    GEN6_WIZ_HASHING_MASK,
> >  			    GEN6_WIZ_HASHING_16x4);
> >  
> > +	/* WaProgramL3SqcReg1Default:bdw */
> > +	WA_WRITE(GEN8_L3SQCREG1, BDW_WA_L3SQCREG1_DEFAULT);
> > +
> >  	return 0;
> >  }
> >  
> > -- 
> > 2.1.0
> > 
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 9+ messages in thread
* Re: [PATCH] drm/i915/bdw: WaProgramL3SqcReg1Default
  2015-03-31 23:03 [PATCH] drm/i915/bdw: WaProgramL3SqcReg1Default Rodrigo Vivi
                   ` (2 preceding siblings ...)
  2015-04-01  8:31 ` Ville Syrjälä
@ 2015-04-01 15:41 ` Ville Syrjälä
  2015-04-07  8:26   ` Daniel Vetter
  3 siblings, 1 reply; 9+ messages in thread
From: Ville Syrjälä @ 2015-04-01 15:41 UTC (permalink / raw)
  To: Rodrigo Vivi; +Cc: intel-gfx, Mika Kuoppala

On Tue, Mar 31, 2015 at 04:03:21PM -0700, Rodrigo Vivi wrote:
> Program the default initial value of the L3SqcReg1 on BDW for performance
> 
> v2: Default confirmed and using intel_ring_emit_wa as Mika pointed out.
> 
> v3: Spec shows now a different value. It tells us to set to 0x784000
>     instead the 0x610000 that is there already.
>     Also rebased after a long time so using WA_WRITE now.
> 
> Cc: Mika Kuoppala <mika.kuoppala@intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

> ---
>  drivers/gpu/drm/i915/i915_reg.h         | 3 +++
>  drivers/gpu/drm/i915/intel_ringbuffer.c | 3 +++
>  2 files changed, 6 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 7e1a0fd9..7f8b69a 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -5325,6 +5325,9 @@ enum skl_disp_power_wells {
>  #define GEN7_L3SQCREG1				0xB010
>  #define  VLV_B0_WA_L3SQCREG1_VALUE		0x00D30000
>  
> +#define GEN8_L3SQCREG1				0xB100
> +#define  BDW_WA_L3SQCREG1_DEFAULT		0x784000
> +
>  #define GEN7_L3CNTLREG1				0xB01C
>  #define  GEN7_WA_FOR_GEN7_L3_CONTROL			0x3C47FF8C
>  #define  GEN7_L3AGDIS				(1<<19)
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index abe062a..c02fccc 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -853,6 +853,9 @@ static int bdw_init_workarounds(struct intel_engine_cs *ring)
>  			    GEN6_WIZ_HASHING_MASK,
>  			    GEN6_WIZ_HASHING_16x4);
>  
> +	/* WaProgramL3SqcReg1Default:bdw */
> +	WA_WRITE(GEN8_L3SQCREG1, BDW_WA_L3SQCREG1_DEFAULT);
> +
>  	return 0;
>  }
>  
> -- 
> 2.1.0
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Ville Syrjälä
Intel OTC
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 9+ messages in thread
* Re: [PATCH] drm/i915/bdw: WaProgramL3SqcReg1Default
  2015-04-01 15:41 ` Ville Syrjälä
@ 2015-04-07  8:26   ` Daniel Vetter
  0 siblings, 0 replies; 9+ messages in thread
From: Daniel Vetter @ 2015-04-07  8:26 UTC (permalink / raw)
  To: Ville Syrjälä; +Cc: intel-gfx, Mika Kuoppala, Rodrigo Vivi

On Wed, Apr 01, 2015 at 06:41:32PM +0300, Ville Syrjälä wrote:
> On Tue, Mar 31, 2015 at 04:03:21PM -0700, Rodrigo Vivi wrote:
> > Program the default initial value of the L3SqcReg1 on BDW for performance
> > 
> > v2: Default confirmed and using intel_ring_emit_wa as Mika pointed out.
> > 
> > v3: Spec shows now a different value. It tells us to set to 0x784000
> >     instead the 0x610000 that is there already.
> >     Also rebased after a long time so using WA_WRITE now.
> > 
> > Cc: Mika Kuoppala <mika.kuoppala@intel.com>
> > Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> 
> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Queued for -next, thanks for the patch.
-Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 9+ messages in thread
* Re: [PATCH] drm/i915/bdw: WaProgramL3SqcReg1Default
  2014-09-30 15:11 ` [PATCH] " Rodrigo Vivi
@ 2014-10-01 13:46   ` Mika Kuoppala
  0 siblings, 0 replies; 9+ messages in thread
From: Mika Kuoppala @ 2014-10-01 13:46 UTC (permalink / raw)
  To: intel-gfx; +Cc: Rodrigo Vivi

Rodrigo Vivi <rodrigo.vivi@intel.com> writes:

> Program the default initial value of the L3SqcReg1 on BDW for performance
>
> v2: Default confirmed and using intel_ring_emit_wa as Mika pointed out.
>
> Cc: Mika Kuoppala <mika.kuoppala@intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h         | 3 +++
>  drivers/gpu/drm/i915/intel_ringbuffer.c | 5 ++++-
>  2 files changed, 7 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 36a847a..33143cc 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -4972,6 +4972,9 @@ enum punit_power_well {
>  #define GEN7_L3SQCREG1				0xB010
>  #define  VLV_B0_WA_L3SQCREG1_VALUE		0x00D30000
>  
> +#define GEN8_L3SQCREG1				0xB100
> +#define  BDW_WA_L3SQCREG1_DEFAULT		0x00610000
> +

This is the default value after reset. I have experimented with other
values and nothing improves above noise level. Further, my suggestion to
using 0x00810000 will cause a gpu hang...so there is dragons here.

As you are writing the same default value that is already in register,
and there is no indication that we should refresh anything, I would
say this patch is not needed until someone comes along and shows
something better than what the default is.

Thanks,
-Mika

>  #define GEN7_L3CNTLREG1				0xB01C
>  #define  GEN7_WA_FOR_GEN7_L3_CONTROL			0x3C47FF8C
>  #define  GEN7_L3AGDIS				(1<<19)
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index 816a692..a37675d 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -707,7 +707,7 @@ static int bdw_init_workarounds(struct intel_engine_cs *ring)
>  	 * update the number of dwords required based on the
>  	 * actual number of workarounds applied
>  	 */
> -	ret = intel_ring_begin(ring, 18);
> +	ret = intel_ring_begin(ring, 21);
>  	if (ret)
>  		return ret;
>  
> @@ -751,6 +751,9 @@ static int bdw_init_workarounds(struct intel_engine_cs *ring)
>  	intel_ring_emit_wa(ring, GEN7_GT_MODE,
>  			   GEN6_WIZ_HASHING_MASK | GEN6_WIZ_HASHING_16x4);
>  
> +	/* WaProgramL3SqcReg1Default:bdw */
> +	intel_ring_emit_wa(ring, GEN8_L3SQCREG1, BDW_WA_L3SQCREG1_DEFAULT);
> +
>  	intel_ring_advance(ring);
>  
>  	DRM_DEBUG_DRIVER("Number of Workarounds applied: %d\n",
> -- 
> 1.9.3
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 9+ messages in thread
* [PATCH] drm/i915/bdw: WaProgramL3SqcReg1Default
  2014-09-26 19:06 [PATCH 3/5] " Ville Syrjälä
@ 2014-09-30 15:11 ` Rodrigo Vivi
  2014-10-01 13:46   ` Mika Kuoppala
  0 siblings, 1 reply; 9+ messages in thread
From: Rodrigo Vivi @ 2014-09-30 15:11 UTC (permalink / raw)
  To: intel-gfx; +Cc: Mika Kuoppala, Rodrigo Vivi

Program the default initial value of the L3SqcReg1 on BDW for performance

v2: Default confirmed and using intel_ring_emit_wa as Mika pointed out.

Cc: Mika Kuoppala <mika.kuoppala@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h         | 3 +++
 drivers/gpu/drm/i915/intel_ringbuffer.c | 5 ++++-
 2 files changed, 7 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 36a847a..33143cc 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4972,6 +4972,9 @@ enum punit_power_well {
 #define GEN7_L3SQCREG1				0xB010
 #define  VLV_B0_WA_L3SQCREG1_VALUE		0x00D30000
 
+#define GEN8_L3SQCREG1				0xB100
+#define  BDW_WA_L3SQCREG1_DEFAULT		0x00610000
+
 #define GEN7_L3CNTLREG1				0xB01C
 #define  GEN7_WA_FOR_GEN7_L3_CONTROL			0x3C47FF8C
 #define  GEN7_L3AGDIS				(1<<19)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 816a692..a37675d 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -707,7 +707,7 @@ static int bdw_init_workarounds(struct intel_engine_cs *ring)
 	 * update the number of dwords required based on the
 	 * actual number of workarounds applied
 	 */
-	ret = intel_ring_begin(ring, 18);
+	ret = intel_ring_begin(ring, 21);
 	if (ret)
 		return ret;
 
@@ -751,6 +751,9 @@ static int bdw_init_workarounds(struct intel_engine_cs *ring)
 	intel_ring_emit_wa(ring, GEN7_GT_MODE,
 			   GEN6_WIZ_HASHING_MASK | GEN6_WIZ_HASHING_16x4);
 
+	/* WaProgramL3SqcReg1Default:bdw */
+	intel_ring_emit_wa(ring, GEN8_L3SQCREG1, BDW_WA_L3SQCREG1_DEFAULT);
+
 	intel_ring_advance(ring);
 
 	DRM_DEBUG_DRIVER("Number of Workarounds applied: %d\n",
-- 
1.9.3

^ permalink raw reply related	[flat|nested] 9+ messages in thread
end of thread, other threads:[~2015-04-07  8:24 UTC | newest]

Thread overview: 9+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2015-03-31 23:03 [PATCH] drm/i915/bdw: WaProgramL3SqcReg1Default Rodrigo Vivi
2015-04-01  5:52 ` shuang.he
2015-04-01  7:49 ` Jani Nikula
2015-04-01  8:31 ` Ville Syrjälä
2015-04-01 14:49   ` Vivi, Rodrigo
2015-04-01 15:41 ` Ville Syrjälä
2015-04-07  8:26   ` Daniel Vetter
  -- strict thread matches above, loose matches on Subject: below --
2014-09-26 19:06 [PATCH 3/5] " Ville Syrjälä
2014-09-30 15:11 ` [PATCH] " Rodrigo Vivi
2014-10-01 13:46   ` Mika Kuoppala

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