* [PATCH 1/2] drm/i915: Naming constants to be written to GEN9_PG_ENABLE
@ 2015-04-10 8:41 sagar.a.kamble
2015-04-10 8:41 ` [PATCH 2/2] drm/i915: Disable Render power gating sagar.a.kamble
2015-04-10 8:57 ` [PATCH 1/2] drm/i915: Naming constants to be written to GEN9_PG_ENABLE Damien Lespiau
0 siblings, 2 replies; 9+ messages in thread
From: sagar.a.kamble @ 2015-04-10 8:41 UTC (permalink / raw)
To: intel-gfx; +Cc: Sagar Kamble
From: Sagar Kamble <sagar.a.kamble@intel.com>
Change-Id: I4253459c075c50d9b6f034b4ed4ad2f54cd7d1d7
Signed-off-by: Sagar Kamble <sagar.a.kamble@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 2 ++
drivers/gpu/drm/i915/intel_pm.c | 4 +++-
2 files changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index c6adf2d..f593900 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6199,6 +6199,8 @@ enum skl_disp_power_wells {
#define GEN9_MEDIA_PG_IDLE_HYSTERESIS 0xA0C4
#define GEN9_RENDER_PG_IDLE_HYSTERESIS 0xA0C8
#define GEN9_PG_ENABLE 0xA210
+#define GEN9_RENDER_PG_ENABLE (1<<0)
+#define GEN9_MEDIA_PG_ENABLE (1<<1)
#define VLV_CHICKEN_3 (VLV_DISPLAY_BASE + 0x7040C)
#define PIXEL_OVERLAP_CNT_MASK (3 << 30)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index cafdb29..9975401 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4351,7 +4351,9 @@ static void gen9_enable_rc6(struct drm_device *dev)
rc6_mask);
/* 3b: Enable Coarse Power Gating only when RC6 is enabled */
- I915_WRITE(GEN9_PG_ENABLE, (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ? 3 : 0);
+ I915_WRITE(GEN9_PG_ENABLE, (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ?
+ (GEN9_RENDER_PG_ENABLE | GEN9_MEDIA_PG_ENABLE) : 0);
+
intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
--
1.8.5
_______________________________________________
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Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH 2/2] drm/i915: Disable Render power gating
2015-04-10 8:41 [PATCH 1/2] drm/i915: Naming constants to be written to GEN9_PG_ENABLE sagar.a.kamble
@ 2015-04-10 8:41 ` sagar.a.kamble
2015-04-10 8:50 ` Damien Lespiau
2015-04-10 11:11 ` Damien Lespiau
2015-04-10 8:57 ` [PATCH 1/2] drm/i915: Naming constants to be written to GEN9_PG_ENABLE Damien Lespiau
1 sibling, 2 replies; 9+ messages in thread
From: sagar.a.kamble @ 2015-04-10 8:41 UTC (permalink / raw)
To: intel-gfx; +Cc: Sagar Kamble
From: Sagar Kamble <sagar.a.kamble@intel.com>
When RC6 along with Render power gating is enabled, GPU hang
happens due to lack of synchronization between GTI and Render reset.
Change-Id: If1614206341eb52a21eadae8c5ebb2655029b50c
Signed-off-by: Sagar Kamble <sagar.a.kamble@intel.com>
Conflicts:
drivers/gpu/drm/i915/intel_pm.c
---
drivers/gpu/drm/i915/intel_pm.c | 7 +++++--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 9975401..f080710 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4350,9 +4350,12 @@ static void gen9_enable_rc6(struct drm_device *dev)
GEN6_RC_CTL_EI_MODE(1) |
rc6_mask);
- /* 3b: Enable Coarse Power Gating only when RC6 is enabled */
+ /*
+ * 3b: Enable Coarse Power Gating only when RC6 is enabled.
+ * WaDisableRenderPowerGating - Render PG need to be disabled with RC6.
+ */
I915_WRITE(GEN9_PG_ENABLE, (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ?
- (GEN9_RENDER_PG_ENABLE | GEN9_MEDIA_PG_ENABLE) : 0);
+ GEN9_MEDIA_PG_ENABLE : 0);
intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
--
1.8.5
_______________________________________________
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Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 9+ messages in thread
* Re: [PATCH 2/2] drm/i915: Disable Render power gating
2015-04-10 8:41 ` [PATCH 2/2] drm/i915: Disable Render power gating sagar.a.kamble
@ 2015-04-10 8:50 ` Damien Lespiau
2015-04-10 11:11 ` Damien Lespiau
1 sibling, 0 replies; 9+ messages in thread
From: Damien Lespiau @ 2015-04-10 8:50 UTC (permalink / raw)
To: sagar.a.kamble; +Cc: intel-gfx
On Fri, Apr 10, 2015 at 02:11:30PM +0530, sagar.a.kamble@intel.com wrote:
> From: Sagar Kamble <sagar.a.kamble@intel.com>
>
> When RC6 along with Render power gating is enabled, GPU hang
> happens due to lack of synchronization between GTI and Render reset.
>
> Change-Id: If1614206341eb52a21eadae8c5ebb2655029b50c
> Signed-off-by: Sagar Kamble <sagar.a.kamble@intel.com>
>
> Conflicts:
> drivers/gpu/drm/i915/intel_pm.c
So, is this a hang that occurs at reset? Do you know if we can do better
by disabling/enabling it around reset?
> ---
> drivers/gpu/drm/i915/intel_pm.c | 7 +++++--
> 1 file changed, 5 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 9975401..f080710 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -4350,9 +4350,12 @@ static void gen9_enable_rc6(struct drm_device *dev)
> GEN6_RC_CTL_EI_MODE(1) |
> rc6_mask);
>
> - /* 3b: Enable Coarse Power Gating only when RC6 is enabled */
> + /*
> + * 3b: Enable Coarse Power Gating only when RC6 is enabled.
> + * WaDisableRenderPowerGating - Render PG need to be disabled with RC6.
> + */
I don't see any WaDisableRenderPowerGating name in the wa databse, where
does that name come from?
> I915_WRITE(GEN9_PG_ENABLE, (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ?
> - (GEN9_RENDER_PG_ENABLE | GEN9_MEDIA_PG_ENABLE) : 0);
> + GEN9_MEDIA_PG_ENABLE : 0);
>
>
> intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
> --
> 1.8.5
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH 1/2] drm/i915: Naming constants to be written to GEN9_PG_ENABLE
2015-04-10 8:41 [PATCH 1/2] drm/i915: Naming constants to be written to GEN9_PG_ENABLE sagar.a.kamble
2015-04-10 8:41 ` [PATCH 2/2] drm/i915: Disable Render power gating sagar.a.kamble
@ 2015-04-10 8:57 ` Damien Lespiau
1 sibling, 0 replies; 9+ messages in thread
From: Damien Lespiau @ 2015-04-10 8:57 UTC (permalink / raw)
To: sagar.a.kamble; +Cc: intel-gfx
On Fri, Apr 10, 2015 at 02:11:29PM +0530, sagar.a.kamble@intel.com wrote:
> From: Sagar Kamble <sagar.a.kamble@intel.com>
>
> Change-Id: I4253459c075c50d9b6f034b4ed4ad2f54cd7d1d7
> Signed-off-by: Sagar Kamble <sagar.a.kamble@intel.com>
Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 2 ++
> drivers/gpu/drm/i915/intel_pm.c | 4 +++-
> 2 files changed, 5 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index c6adf2d..f593900 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -6199,6 +6199,8 @@ enum skl_disp_power_wells {
> #define GEN9_MEDIA_PG_IDLE_HYSTERESIS 0xA0C4
> #define GEN9_RENDER_PG_IDLE_HYSTERESIS 0xA0C8
> #define GEN9_PG_ENABLE 0xA210
> +#define GEN9_RENDER_PG_ENABLE (1<<0)
> +#define GEN9_MEDIA_PG_ENABLE (1<<1)
>
> #define VLV_CHICKEN_3 (VLV_DISPLAY_BASE + 0x7040C)
> #define PIXEL_OVERLAP_CNT_MASK (3 << 30)
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index cafdb29..9975401 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -4351,7 +4351,9 @@ static void gen9_enable_rc6(struct drm_device *dev)
> rc6_mask);
>
> /* 3b: Enable Coarse Power Gating only when RC6 is enabled */
> - I915_WRITE(GEN9_PG_ENABLE, (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ? 3 : 0);
> + I915_WRITE(GEN9_PG_ENABLE, (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ?
> + (GEN9_RENDER_PG_ENABLE | GEN9_MEDIA_PG_ENABLE) : 0);
> +
>
> intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
>
> --
> 1.8.5
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH 2/2] drm/i915: Disable Render power gating
2015-04-10 8:41 ` [PATCH 2/2] drm/i915: Disable Render power gating sagar.a.kamble
2015-04-10 8:50 ` Damien Lespiau
@ 2015-04-10 11:11 ` Damien Lespiau
2015-04-10 12:02 ` [PATCH 1/1] " sagar.a.kamble
1 sibling, 1 reply; 9+ messages in thread
From: Damien Lespiau @ 2015-04-10 11:11 UTC (permalink / raw)
To: sagar.a.kamble; +Cc: intel-gfx
On Fri, Apr 10, 2015 at 02:11:30PM +0530, sagar.a.kamble@intel.com wrote:
> From: Sagar Kamble <sagar.a.kamble@intel.com>
>
> When RC6 along with Render power gating is enabled, GPU hang
> happens due to lack of synchronization between GTI and Render reset.
Maybe, instead of reset here, say render being power gated?
> Change-Id: If1614206341eb52a21eadae8c5ebb2655029b50c
> Signed-off-by: Sagar Kamble <sagar.a.kamble@intel.com>
>
> Conflicts:
> drivers/gpu/drm/i915/intel_pm.c
I have limited info about this, but it seems to fix something that has
been characterized recently. There may be more dubious interactions to
fix around this coarse power gating, RC6 entry and forcewake, but that's
another story. So with the skl,bxt mention added:
Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
> ---
> drivers/gpu/drm/i915/intel_pm.c | 7 +++++--
> 1 file changed, 5 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 9975401..f080710 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -4350,9 +4350,12 @@ static void gen9_enable_rc6(struct drm_device *dev)
> GEN6_RC_CTL_EI_MODE(1) |
> rc6_mask);
>
> - /* 3b: Enable Coarse Power Gating only when RC6 is enabled */
> + /*
> + * 3b: Enable Coarse Power Gating only when RC6 is enabled.
> + * WaDisableRenderPowerGating - Render PG need to be disabled with RC6.
> + */
WaDisableRenderPowerGating:skl,bxt
> I915_WRITE(GEN9_PG_ENABLE, (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ?
> - (GEN9_RENDER_PG_ENABLE | GEN9_MEDIA_PG_ENABLE) : 0);
> + GEN9_MEDIA_PG_ENABLE : 0);
>
>
> intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
> --
> 1.8.5
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH 1/1] drm/i915: Disable Render power gating
2015-04-10 11:11 ` Damien Lespiau
@ 2015-04-10 12:02 ` sagar.a.kamble
2015-04-10 14:16 ` Daniel Vetter
0 siblings, 1 reply; 9+ messages in thread
From: sagar.a.kamble @ 2015-04-10 12:02 UTC (permalink / raw)
To: intel-gfx; +Cc: Sagar Kamble
From: Sagar Kamble <sagar.a.kamble@intel.com>
When RC6 along with Render power gating is enabled, GPU hang
happens due to lack of synchronization between GTI and Render
power gating.
Change-Id: If1614206341eb52a21eadae8c5ebb2655029b50c
Signed-off-by: Sagar Kamble <sagar.a.kamble@intel.com>
---
drivers/gpu/drm/i915/intel_pm.c | 7 +++++--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 9975401..4dd8b41 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4350,9 +4350,12 @@ static void gen9_enable_rc6(struct drm_device *dev)
GEN6_RC_CTL_EI_MODE(1) |
rc6_mask);
- /* 3b: Enable Coarse Power Gating only when RC6 is enabled */
+ /*
+ * 3b: Enable Coarse Power Gating only when RC6 is enabled.
+ * WaDisableRenderPowerGating:skl,bxt - Render PG need to be disabled with RC6.
+ */
I915_WRITE(GEN9_PG_ENABLE, (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ?
- (GEN9_RENDER_PG_ENABLE | GEN9_MEDIA_PG_ENABLE) : 0);
+ GEN9_MEDIA_PG_ENABLE : 0);
intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
--
1.8.5
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 9+ messages in thread
* Re: [PATCH 1/1] drm/i915: Disable Render power gating
2015-04-10 12:02 ` [PATCH 1/1] " sagar.a.kamble
@ 2015-04-10 14:16 ` Daniel Vetter
2015-04-12 5:58 ` [PATCH v2 " sagar.a.kamble
0 siblings, 1 reply; 9+ messages in thread
From: Daniel Vetter @ 2015-04-10 14:16 UTC (permalink / raw)
To: sagar.a.kamble; +Cc: intel-gfx
On Fri, Apr 10, 2015 at 05:32:34PM +0530, sagar.a.kamble@intel.com wrote:
> From: Sagar Kamble <sagar.a.kamble@intel.com>
>
> When RC6 along with Render power gating is enabled, GPU hang
> happens due to lack of synchronization between GTI and Render
> power gating.
>
When resending patches please have a per-patch changelog here. And if the
patch is reviewed please also add all these tags when resending. Otherwise
the patch gets lost easily.
Merged the first one meanwhile, thanks.
-Daniel
> Change-Id: If1614206341eb52a21eadae8c5ebb2655029b50c
> Signed-off-by: Sagar Kamble <sagar.a.kamble@intel.com>
> ---
> drivers/gpu/drm/i915/intel_pm.c | 7 +++++--
> 1 file changed, 5 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 9975401..4dd8b41 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -4350,9 +4350,12 @@ static void gen9_enable_rc6(struct drm_device *dev)
> GEN6_RC_CTL_EI_MODE(1) |
> rc6_mask);
>
> - /* 3b: Enable Coarse Power Gating only when RC6 is enabled */
> + /*
> + * 3b: Enable Coarse Power Gating only when RC6 is enabled.
> + * WaDisableRenderPowerGating:skl,bxt - Render PG need to be disabled with RC6.
> + */
> I915_WRITE(GEN9_PG_ENABLE, (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ?
> - (GEN9_RENDER_PG_ENABLE | GEN9_MEDIA_PG_ENABLE) : 0);
> + GEN9_MEDIA_PG_ENABLE : 0);
>
>
> intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
> --
> 1.8.5
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH v2 1/1] drm/i915: Disable Render power gating
2015-04-10 14:16 ` Daniel Vetter
@ 2015-04-12 5:58 ` sagar.a.kamble
2015-04-13 9:24 ` Daniel Vetter
0 siblings, 1 reply; 9+ messages in thread
From: sagar.a.kamble @ 2015-04-12 5:58 UTC (permalink / raw)
To: intel-gfx; +Cc: Sagar Kamble
From: Sagar Kamble <sagar.a.kamble@intel.com>
When RC6 along with Render power gating is enabled, GPU hang
happens due to lack of synchronization between GTI and Render
power gating.
v2: Updated commit message and WA name (Damien)
Change-Id: If1614206341eb52a21eadae8c5ebb2655029b50c
Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Sagar Kamble <sagar.a.kamble@intel.com>
---
drivers/gpu/drm/i915/intel_pm.c | 7 +++++--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 9975401..4dd8b41 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4350,9 +4350,12 @@ static void gen9_enable_rc6(struct drm_device *dev)
GEN6_RC_CTL_EI_MODE(1) |
rc6_mask);
- /* 3b: Enable Coarse Power Gating only when RC6 is enabled */
+ /*
+ * 3b: Enable Coarse Power Gating only when RC6 is enabled.
+ * WaDisableRenderPowerGating:skl,bxt - Render PG need to be disabled with RC6.
+ */
I915_WRITE(GEN9_PG_ENABLE, (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ?
- (GEN9_RENDER_PG_ENABLE | GEN9_MEDIA_PG_ENABLE) : 0);
+ GEN9_MEDIA_PG_ENABLE : 0);
intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
--
1.8.5
_______________________________________________
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Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 9+ messages in thread
* Re: [PATCH v2 1/1] drm/i915: Disable Render power gating
2015-04-12 5:58 ` [PATCH v2 " sagar.a.kamble
@ 2015-04-13 9:24 ` Daniel Vetter
0 siblings, 0 replies; 9+ messages in thread
From: Daniel Vetter @ 2015-04-13 9:24 UTC (permalink / raw)
To: sagar.a.kamble; +Cc: intel-gfx
On Sun, Apr 12, 2015 at 11:28:14AM +0530, sagar.a.kamble@intel.com wrote:
> From: Sagar Kamble <sagar.a.kamble@intel.com>
>
> When RC6 along with Render power gating is enabled, GPU hang
> happens due to lack of synchronization between GTI and Render
> power gating.
>
> v2: Updated commit message and WA name (Damien)
>
> Change-Id: If1614206341eb52a21eadae8c5ebb2655029b50c
> Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
> Signed-off-by: Sagar Kamble <sagar.a.kamble@intel.com>
Queued for -next, thanks for the patch.
-Daniel
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 9+ messages in thread
end of thread, other threads:[~2015-04-13 9:22 UTC | newest]
Thread overview: 9+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2015-04-10 8:41 [PATCH 1/2] drm/i915: Naming constants to be written to GEN9_PG_ENABLE sagar.a.kamble
2015-04-10 8:41 ` [PATCH 2/2] drm/i915: Disable Render power gating sagar.a.kamble
2015-04-10 8:50 ` Damien Lespiau
2015-04-10 11:11 ` Damien Lespiau
2015-04-10 12:02 ` [PATCH 1/1] " sagar.a.kamble
2015-04-10 14:16 ` Daniel Vetter
2015-04-12 5:58 ` [PATCH v2 " sagar.a.kamble
2015-04-13 9:24 ` Daniel Vetter
2015-04-10 8:57 ` [PATCH 1/2] drm/i915: Naming constants to be written to GEN9_PG_ENABLE Damien Lespiau
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