From mboxrd@z Thu Jan 1 00:00:00 1970 From: Catalin Marinas Subject: Re: [RFC PATCH 5/5] arm64: qcom: add cpu operations Date: Wed, 15 Apr 2015 15:53:51 +0100 Message-ID: <20150415145350.GB22741@localhost> References: <1428601031-5366-1-git-send-email-galak@codeaurora.org> <1428601031-5366-6-git-send-email-galak@codeaurora.org> <20150414162953.GL28709@leverpostej> <552D9A37.6070107@redhat.com> <20150415090425.GA2866@leverpostej> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Return-path: Content-Disposition: inline In-Reply-To: <20150415090425.GA2866@leverpostej> Sender: devicetree-owner-u79uwXL29TY76Z2rM5mHXA@public.gmane.org To: Mark Rutland Cc: Al Stone , "devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org" , "linux-arm-msm-u79uwXL29TY76Z2rM5mHXA@public.gmane.org" , Kumar Gala , Will Deacon , "linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org" , "arm-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org" , Abhimanyu Kapur , "linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org" List-Id: linux-arm-msm@vger.kernel.org On Wed, Apr 15, 2015 at 10:04:25AM +0100, Mark Rutland wrote: > On Tue, Apr 14, 2015 at 11:52:39PM +0100, Al Stone wrote: > > On 04/14/2015 10:29 AM, Mark Rutland wrote: > > >> diff --git a/Documentation/devicetree/bindings/arm/cpus.txt b/Documentation/devicetree/bindings/arm/cpus.txt > > >> index 8b9e0a9..35cabe5 100644 > > >> --- a/Documentation/devicetree/bindings/arm/cpus.txt > > >> +++ b/Documentation/devicetree/bindings/arm/cpus.txt > > >> @@ -185,6 +185,8 @@ nodes to be present and contain the properties described below. > > >> be one of: > > >> "psci" > > >> "spin-table" > > > > > > In the case of these two, there's documentation on what the OS, FW, and > > > HW are expected to do. There's a PSCI spec, and spin-table is documented > > > in booting.txt (which is admittedly not fantastic). > > > [snip...] > > > > Perhaps a side topic, but I thought spin-table was being actively discouraged > > for arm64. Forgive me if I missed the memo, but is that not correct? > > We prefer that people implement PSCI, and if they must use spin-table, > each CPU has its own release address. > > However, we don't want implementation-specific mechanisms, and > spin-table is preferable to these. An important aspect is that with spin-table you don't get CPU off or suspend and some kernel functionality will be missing (kexec being one of them). -- Catalin -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932434AbbDOOyH (ORCPT ); Wed, 15 Apr 2015 10:54:07 -0400 Received: from foss.arm.com ([217.140.101.70]:36177 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932254AbbDOOyA (ORCPT ); Wed, 15 Apr 2015 10:54:00 -0400 Date: Wed, 15 Apr 2015 15:53:51 +0100 From: Catalin Marinas To: Mark Rutland Cc: Al Stone , "devicetree@vger.kernel.org" , "linux-arm-msm@vger.kernel.org" , Kumar Gala , Will Deacon , "linux-kernel@vger.kernel.org" , "arm@kernel.org" , Abhimanyu Kapur , "linux-arm-kernel@lists.infradead.org" Subject: Re: [RFC PATCH 5/5] arm64: qcom: add cpu operations Message-ID: <20150415145350.GB22741@localhost> References: <1428601031-5366-1-git-send-email-galak@codeaurora.org> <1428601031-5366-6-git-send-email-galak@codeaurora.org> <20150414162953.GL28709@leverpostej> <552D9A37.6070107@redhat.com> <20150415090425.GA2866@leverpostej> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20150415090425.GA2866@leverpostej> User-Agent: Mutt/1.5.21 (2010-09-15) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, Apr 15, 2015 at 10:04:25AM +0100, Mark Rutland wrote: > On Tue, Apr 14, 2015 at 11:52:39PM +0100, Al Stone wrote: > > On 04/14/2015 10:29 AM, Mark Rutland wrote: > > >> diff --git a/Documentation/devicetree/bindings/arm/cpus.txt b/Documentation/devicetree/bindings/arm/cpus.txt > > >> index 8b9e0a9..35cabe5 100644 > > >> --- a/Documentation/devicetree/bindings/arm/cpus.txt > > >> +++ b/Documentation/devicetree/bindings/arm/cpus.txt > > >> @@ -185,6 +185,8 @@ nodes to be present and contain the properties described below. > > >> be one of: > > >> "psci" > > >> "spin-table" > > > > > > In the case of these two, there's documentation on what the OS, FW, and > > > HW are expected to do. There's a PSCI spec, and spin-table is documented > > > in booting.txt (which is admittedly not fantastic). > > > [snip...] > > > > Perhaps a side topic, but I thought spin-table was being actively discouraged > > for arm64. Forgive me if I missed the memo, but is that not correct? > > We prefer that people implement PSCI, and if they must use spin-table, > each CPU has its own release address. > > However, we don't want implementation-specific mechanisms, and > spin-table is preferable to these. An important aspect is that with spin-table you don't get CPU off or suspend and some kernel functionality will be missing (kexec being one of them). -- Catalin From mboxrd@z Thu Jan 1 00:00:00 1970 From: catalin.marinas@arm.com (Catalin Marinas) Date: Wed, 15 Apr 2015 15:53:51 +0100 Subject: [RFC PATCH 5/5] arm64: qcom: add cpu operations In-Reply-To: <20150415090425.GA2866@leverpostej> References: <1428601031-5366-1-git-send-email-galak@codeaurora.org> <1428601031-5366-6-git-send-email-galak@codeaurora.org> <20150414162953.GL28709@leverpostej> <552D9A37.6070107@redhat.com> <20150415090425.GA2866@leverpostej> Message-ID: <20150415145350.GB22741@localhost> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On Wed, Apr 15, 2015 at 10:04:25AM +0100, Mark Rutland wrote: > On Tue, Apr 14, 2015 at 11:52:39PM +0100, Al Stone wrote: > > On 04/14/2015 10:29 AM, Mark Rutland wrote: > > >> diff --git a/Documentation/devicetree/bindings/arm/cpus.txt b/Documentation/devicetree/bindings/arm/cpus.txt > > >> index 8b9e0a9..35cabe5 100644 > > >> --- a/Documentation/devicetree/bindings/arm/cpus.txt > > >> +++ b/Documentation/devicetree/bindings/arm/cpus.txt > > >> @@ -185,6 +185,8 @@ nodes to be present and contain the properties described below. > > >> be one of: > > >> "psci" > > >> "spin-table" > > > > > > In the case of these two, there's documentation on what the OS, FW, and > > > HW are expected to do. There's a PSCI spec, and spin-table is documented > > > in booting.txt (which is admittedly not fantastic). > > > [snip...] > > > > Perhaps a side topic, but I thought spin-table was being actively discouraged > > for arm64. Forgive me if I missed the memo, but is that not correct? > > We prefer that people implement PSCI, and if they must use spin-table, > each CPU has its own release address. > > However, we don't want implementation-specific mechanisms, and > spin-table is preferable to these. An important aspect is that with spin-table you don't get CPU off or suspend and some kernel functionality will be missing (kexec being one of them). -- Catalin