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From: Bruce Richardson <bruce.richardson-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org>
To: "Kavanagh,
	Mark B" <mark.b.kavanagh-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org>
Cc: "dev-VfR2kkLFssw@public.gmane.org" <dev-VfR2kkLFssw@public.gmane.org>
Subject: Re: Minimum Supported x86 microarchitecture
Date: Wed, 15 Apr 2015 17:05:27 +0100	[thread overview]
Message-ID: <20150415160527.GA9836@bricha3-MOBL3> (raw)
In-Reply-To: <DC5AD7FA266D86499789B1BCAEC715F846DA64E3-pww93C2UFcwu0RiL9chJVbfspsVTdybXVpNB7YpNyf8@public.gmane.org>

On Wed, Apr 15, 2015 at 03:09:39PM +0000, Kavanagh, Mark B wrote:
> Hi,
> 
> The recent reimplementation of rte_memcpy in DPDK v2.0.0 seems to have a placed an implicit floor on the microarchitecture/Instruction set supported by DPDK.
> 
> For example, I can't compile head of OVS against DPDK 2.0 with gcc without passing the 'msse3' flag; this points to an implicit minimum  supported CPU of 'core2'. More discussion on same is available here: http://openvswitch.org/pipermail/dev/2015-April/053523.html
> 
> Can anyone confirm or deny this, and is/should it be documented?
> 
> Thanks in advance,
> Mark

SSE3 is the minimum necessary. However, I believe all x86_64 cpus have at least
SSE3 support, so this should only be a problem with 32-bit builds. Is this the
case for you?

/Bruce

  parent reply	other threads:[~2015-04-15 16:05 UTC|newest]

Thread overview: 3+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-04-15 15:09 Minimum Supported x86 microarchitecture Kavanagh, Mark B
     [not found] ` <DC5AD7FA266D86499789B1BCAEC715F846DA64E3-pww93C2UFcwu0RiL9chJVbfspsVTdybXVpNB7YpNyf8@public.gmane.org>
2015-04-15 16:05   ` Bruce Richardson [this message]
2015-04-15 16:09     ` Kavanagh, Mark B

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