From mboxrd@z Thu Jan  1 00:00:00 1970
From: Mark Brown <broonie@kernel.org>
Subject: Re: [RFC 6/7] ASoC: hda: Add support for SSP register
	settings
Date: Fri, 24 Apr 2015 18:55:32 +0100
Message-ID: <20150424175532.GD22845@sirena.org.uk>
References: <1429390653-8194-1-git-send-email-vinod.koul@intel.com>
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To: Vinod Koul <vinod.koul@intel.com>
Cc: alsa-devel@alsa-project.org, tiwai@suse.de, Hardik T Shah <hardik.t.shah@intel.com>, liam.r.girdwood@linux.intel.com, patches.audio@intel.com, Jeeja KP <jeeja.kp@intel.com>
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On Sun, Apr 19, 2015 at 02:27:32AM +0530, Vinod Koul wrote:

> +	req_bclk = fs * slots * s_fmt;

We have a helper for this.

> +	dummy = 0;
> +	/* Find the lowest bit clock possible for particular configuration */
> +	do {
> +		req_bclk = ((s_fmt * fs * slots) + (fs * dummy));
> +		mod = HDA_SSP_MAX_FREQ_192 % req_bclk;
> +		divisor = HDA_SSP_MAX_FREQ_192 / req_bclk;
> +		if (!mod) {
> +			found = 1;
> +			break;
> +		}
> +		/* Dont add odd number of dummy bits, since I2S requires
> +		 * dummy bit after each slot/channel
> +		 */

It does?

> +		dummy += 2;
> +		if (dummy > (HDA_SSPSP2_FEP_MASK >> HDA_SSPSP2_FEP_SHIFT)) {
> +			dev_err(ctx->dev, "Dummy bit greater than what SSP can support\n");
> +			return -EINVAL;
> +		}
> +
> +	} while (divisor > 0);

Aside from the limits this all looks like it could be generic?

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