From mboxrd@z Thu Jan 1 00:00:00 1970 From: Konrad Rzeszutek Wilk Subject: Re: [PATCH v3 10/10] x86/MSI-X: provide hypercall interface for mask-all control Date: Fri, 12 Jun 2015 09:21:40 -0400 Message-ID: <20150612132140.GA15651@l.oracle.com> References: <55719F9D0200007800081425@mail.emea.novell.com> <5571A3F202000078000814CA@mail.emea.novell.com> <557964870200007800083706@mail.emea.novell.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mail6.bemta14.messagelabs.com ([193.109.254.103]) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1Z3Ou9-0003WN-Oa for xen-devel@lists.xenproject.org; Fri, 12 Jun 2015 13:21:53 +0000 Content-Disposition: inline In-Reply-To: <557964870200007800083706@mail.emea.novell.com> List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org To: Jan Beulich Cc: Wei Liu , Stefano Stabellini , Andrew Cooper , Ian Jackson , Ian Campbell , xen-devel , dgdegra@tycho.nsa.gov, Keir Fraser , Roger Pau Monne List-Id: xen-devel@lists.xenproject.org On Thu, Jun 11, 2015 at 09:35:51AM +0100, Jan Beulich wrote: > >>> On 05.06.15 at 13:28, wrote: > > Qemu shouldn't be fiddling with this bit directly, as the hypervisor > > may (and now does) use it for its own purposes. Provide it with a > > replacement interface, allowing the hypervisor to track host and guest > > masking intentions independently (clearing the bit only when both want > > it clear). > > Originally I merely meant to ping the tools side changes here > (considering that the original issue has been pending for months, > delayed by various security issues as well as slow turnaround on > understanding the nature and validity of that original issue, I'd > _really_ like to see this go in now), but thinking about it once > again over night I realized that what we do here to allow qemu > to be fixed would then also be made use of by the kernels > running pciback: While Dom0 fiddling with the MSI-X mask-all bit > for its own purposes is at least not a security problem, it doing > so on behalf of (and directed by) a guest would be as soon as > the hypervisor side patches making use of that bit went in. It is hard to comment on this since I don't know exactly what those patches would do. But the 'pci_msi_ignore_mask' from 38737d82f9f0168955f9944c3f8bd3bb262c7e88, "PCI/MSI: Add pci_msi_ignore_mask to prevent writes to MSI/MSI-X Mask Bits"" should have prevented that. That said said patches could change the pci_msi_ignore_mask of course. > > While I continue to be of the opinion that all direct writes to > interrupt masking bits (MSI-X mask-all, MSI-X per-entry mask, > MSI per entry mask) outside of the hypervisor are wrong and > should be eliminated, the scope of the problem now clearly > going beyond qemu made me reconsider whether we shouldn't, > as advocated by Stefano, follow the trap-and-emulate route > instead. This would not only mean adding code to x86's existing > port CF8/CFC intercepts, but also write-protecting the MMCFG > pages for all PCI devices being MSI or MSI-X capable, emulating > writes with inspection / modification of writes to any of the mask > bits located in PCI config space. (A subsequent optimization to > this may then be a hypercall to do config space writes, > eliminating the emulation overhead, accompanied by a bitmap > indicating which devices' CFG space can be written directly.) > > For a (from now on) timely resolution of the original problem I'd > really appreciate opinions (or alternative suggestions). Weeding out the direct writes is nice, but the process of eliminating those is going to take time. I like your idea as it provides a nice mechanism to track which component is at fault writting to those areas and can help in fixing that. But on the flip side - it also might delay patches for the offending code as we would have already an 'firewall' in place. > > Jan >