From mboxrd@z Thu Jan  1 00:00:00 1970
Return-Path: <linux-kernel-owner@vger.kernel.org>
Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand
	id S1755702AbbFOO0V (ORCPT <rfc822;w@1wt.eu>);
	Mon, 15 Jun 2015 10:26:21 -0400
Received: from cantor2.suse.de ([195.135.220.15]:56311 "EHLO mx2.suse.de"
	rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP
	id S1755304AbbFOO0H (ORCPT <rfc822;linux-kernel@vger.kernel.org>);
	Mon, 15 Jun 2015 10:26:07 -0400
Date: Mon, 15 Jun 2015 16:25:59 +0200
From: Borislav Petkov <bp@suse.de>
To: Huang Rui <ray.huang@amd.com>
Cc: Peter Zijlstra <peterz@infradead.org>,
        Andy Lutomirski <luto@amacapital.net>,
        Thomas Gleixner <tglx@linutronix.de>, Ingo Molnar <mingo@kernel.org>,
        "Rafael J. Wysocki" <rjw@rjwysocki.net>, Len Brown <lenb@kernel.org>,
        John Stultz <john.stultz@linaro.org>,
        =?utf-8?B?RnLDqWTDqXJpYw==?= Weisbecker <fweisbec@gmail.com>,
        linux-kernel@vger.kernel.org, x86@kernel.org,
        Fengguang Wu <fengguang.wu@intel.com>, Aaron Lu <aaron.lu@intel.com>,
        Suravee Suthikulanit <suravee.suthikulpanit@amd.com>,
        Tony Li <tony.li@amd.com>, Ken Xue <ken.xue@amd.com>
Subject: Re: [PATCH v5 2/2] x86, mwaitt: introduce mwaix delay with a
 configurable timer
Message-ID: <20150615142559.GC4481@pd.tnic>
References: <1434365284-1495-1-git-send-email-ray.huang@amd.com>
 <1434365284-1495-3-git-send-email-ray.huang@amd.com>
 <20150615105718.GW3644@twins.programming.kicks-ass.net>
 <20150615111526.GB4481@pd.tnic>
 <20150615140418.GB28310@hr-slim.amd.com>
MIME-Version: 1.0
Content-Type: text/plain; charset=utf-8
Content-Disposition: inline
In-Reply-To: <20150615140418.GB28310@hr-slim.amd.com>
User-Agent: Mutt/1.5.23 (2014-03-12)
Sender: linux-kernel-owner@vger.kernel.org
List-ID: <linux-kernel.vger.kernel.org>
X-Mailing-List: linux-kernel@vger.kernel.org

On Mon, Jun 15, 2015 at 10:04:19PM +0800, Huang Rui wrote:
> Hmm, the current processor cannot enter C1 with MWAITX, so I don't
> confirm if it would have higher wakeup latency on C1 in future.

I remember you saying MWAITX enters currently something between C1 and
C0. How does that behave wrt latency and power savings?

-- 
Regards/Gruss,
    Boris.

ECO tip #101: Trim your mails when you reply.
--