From: Tom Rini <trini@konsulko.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH] ARM: DRA7: Change configuration to prevent DDR reset control from EMIF
Date: Tue, 16 Jun 2015 11:43:37 -0400 [thread overview]
Message-ID: <20150616154337.GJ1728@bill-the-cat> (raw)
In-Reply-To: <1434461341-21565-1-git-send-email-nm@ti.com>
On Tue, Jun 16, 2015 at 08:29:01AM -0500, Nishanth Menon wrote:
> DRA7/AM57xx devices can be operated in many different configurations.
> When the SoC is supposed to support a configuration where low power mode
> state may involve the SoC completely powered off and DDR is in self
> refresh, SoC EMIF controller should not be the master of the reset
> signal and an external entity might be in control of things.
>
> The default configuration of Linux on TI evms involve not powering off
> the voltage rails (due to various reasons including reliability concerns)
> and must not allow DDR reset to be controlled by EMIF. On platforms
> where external entity might control the reset signal, this configuration
> will be a "dont care".
>
> Fixes: 536d87470869 ("ARM: DRA7: Update DDR IO registers")
> Tested-by: Keerthy <j-keerthy@ti.com>
> Acked-by: Brad Griffis <bgriffis@ti.com>
> Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
--
Tom
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next prev parent reply other threads:[~2015-06-16 15:43 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-06-16 13:29 [U-Boot] [PATCH] ARM: DRA7: Change configuration to prevent DDR reset control from EMIF Nishanth Menon
2015-06-16 15:43 ` Tom Rini [this message]
2015-06-19 20:25 ` [U-Boot] " Tom Rini
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