From: Damien Lespiau <damien.lespiau@intel.com>
To: Chris Wilson <chris@chris-wilson.co.uk>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [RFC] drm/i915: Introduce documentation for register subfields
Date: Fri, 19 Jun 2015 11:44:25 +0100 [thread overview]
Message-ID: <20150619104425.GI24323@strange.ger.corp.intel.com> (raw)
In-Reply-To: <1434707535-13014-1-git-send-email-chris@chris-wilson.co.uk>
On Fri, Jun 19, 2015 at 10:52:15AM +0100, Chris Wilson wrote:
> An interesting point was raised in some recent patches to document the
> various widths of the register subfields. I disagreed with that patch in
> that it transformed illegal values into some random potentially harmful
> valid value (and not transforming an invalid value would end up writing
> bits in other subfields, so equally bad). Most of our register usage is
> with static values so unlikely to be of concern, but for those we can
> document the register subfields and provide compile time checking.
I've thought about things like this in the past as well, we can even
automatically generate all of that from the specs!
I had other per-register metadata in mind, like:
- is the register is a masked one or not (and then warn if we're
trying to write it wihtout the _MASKED_*() macros)
- is the register part of the render context (and then warn if we try
to write it with a MMIO write).
#define FOO 0x1234
#define FOO_IS_MASKED 1
#define FOO_IS_IN_RENDER_CTX 1
should be enough for the compile-time warns like you do here.
--
Damien
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next prev parent reply other threads:[~2015-06-19 10:44 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-06-19 9:52 [RFC] drm/i915: Introduce documentation for register subfields Chris Wilson
2015-06-19 10:44 ` Damien Lespiau [this message]
2015-06-22 14:05 ` Daniel Vetter
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