From mboxrd@z Thu Jan  1 00:00:00 1970
From: Albert ARIBAUD <albert.u.boot@aribaud.net>
Date: Thu, 2 Jul 2015 23:06:02 +0200
Subject: [U-Boot] [PATCH 3/6] armv8/mmu: Clean up TCR programming
In-Reply-To: <550C6346.4010009@arm.com>
References: <1426852073-10299-1-git-send-email-thierry.reding@gmail.com>
 <1426852073-10299-3-git-send-email-thierry.reding@gmail.com>
 <550C6346.4010009@arm.com>
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To: u-boot@lists.denx.de

Hello Marc,

On Fri, 20 Mar 2015 18:13:26 +0000, Marc Zyngier <marc.zyngier@arm.com>
wrote:
> On 20/03/15 11:47, Thierry Reding wrote:
> > From: Thierry Reding <treding@nvidia.com>
> > 
> > Use the inner shareable attribute for memory, which makes more sense
> > considering that this code is called when caches are being enabled.
> > 
> > While at it, fix the values for the shareability attribute field to
> > match the documentation.
> > 
> > Cc: Albert Aribaud <albert.u.boot@aribaud.net>
> > Cc: Marc Zyngier <marc.zyngier@arm.com>
> > Signed-off-by: Thierry Reding <treding@nvidia.com>
> > ---
> >  arch/arm/include/asm/armv8/mmu.h | 8 ++++----
> >  1 file changed, 4 insertions(+), 4 deletions(-)
> > 
> > diff --git a/arch/arm/include/asm/armv8/mmu.h b/arch/arm/include/asm/armv8/mmu.h
> > index 4b9cb5296572..6d42f5533a74 100644
> > --- a/arch/arm/include/asm/armv8/mmu.h
> > +++ b/arch/arm/include/asm/armv8/mmu.h
> > @@ -93,8 +93,8 @@
> >  #define TCR_ORGN_WBNWA		(3 << 10)
> >  #define TCR_ORGN_MASK		(3 << 10)
> >  #define TCR_SHARED_NON		(0 << 12)
> > -#define TCR_SHARED_OUTER	(1 << 12)
> > -#define TCR_SHARED_INNER	(2 << 12)
> > +#define TCR_SHARED_OUTER	(2 << 12)
> > +#define TCR_SHARED_INNER	(3 << 12)
> >  #define TCR_TG0_4K		(0 << 14)
> >  #define TCR_TG0_64K		(1 << 14)
> >  #define TCR_TG0_16K		(2 << 14)
> > @@ -102,9 +102,9 @@
> >  #define TCR_EL2_IPS_BITS	(3 << 16)	/* 42 bits physical address */
> >  #define TCR_EL3_IPS_BITS	(3 << 16)	/* 42 bits physical address */
> >  
> > -/* PTWs cacheable, inner/outer WBWA and non-shareable */
> > +/* PTWs cacheable, inner/outer WBWA and inner shareable */
> >  #define TCR_FLAGS		(TCR_TG0_64K |		\
> > -				TCR_SHARED_NON |	\
> > +				TCR_SHARED_INNER |	\
> >  				TCR_ORGN_WBWA |		\
> >  				TCR_IRGN_WBWA |		\
> >  				TCR_T0SZ(VA_BITS))
> > 
> 
> Acked-by: Marc Zyngier <marc.zyngier@arm.com>
> 
> One thing though: the architecture doesn't mandate 64k pages to be
> implemented by the HW. Actually, it doesn't mandate any particular page
> size, you just have to implement at least one (4k, 16k or 64k).
> 
> It would be good to test if 64k pages are implemented (by testing
> ID_AA64MMFR0_EL1) and not try to enable caches if not, possibly
> displaying a warning for the unsuspecting u-boot hacker.

So Marc, is this a request for a change, or is the patch applicable as
it is?

Amicalement,
-- 
Albert.