From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:36837) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZPq29-0000KA-Ce for qemu-devel@nongnu.org; Thu, 13 Aug 2015 06:46:54 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ZPq20-0006m7-Vc for qemu-devel@nongnu.org; Thu, 13 Aug 2015 06:46:53 -0400 Received: from mail-lb0-x22f.google.com ([2a00:1450:4010:c04::22f]:33453) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZPpvl-0002EO-95 for qemu-devel@nongnu.org; Thu, 13 Aug 2015 06:40:17 -0400 Received: by lbbsx3 with SMTP id sx3so24622447lbb.0 for ; Thu, 13 Aug 2015 03:40:16 -0700 (PDT) Date: Thu, 13 Aug 2015 12:40:14 +0200 From: "Edgar E. Iglesias" Message-ID: <20150813104014.GB27827@toto> References: <1438950810-28618-1-git-send-email-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1438950810-28618-1-git-send-email-peter.maydell@linaro.org> Subject: Re: [Qemu-devel] [PATCH 0/6] flush TLBs for one MMUidx only, missing AArch64 TLB ops List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Peter Maydell Cc: Paolo Bonzini , Alex =?iso-8859-1?Q?Benn=E9e?= , qemu-devel@nongnu.org, patches@linaro.org On Fri, Aug 07, 2015 at 01:33:24PM +0100, Peter Maydell wrote: > This series does three things: Hi, Looks good to me! Reviewed-by: Edgar E. Iglesias Cheers, Edgar > > (1) implement the "flush the TLB only for a specified MMU index" > functionality that we talked about when we added all the new > MMU index values for ARM for EL2 and EL3 > > (2) use that to restrict the AArch64 TLB maintenance operations > to only the MMU indexes they need to touch > > (3) add all the missing EL2 and EL3 related TLB operations for > AArch64 > > I did a quick performance test by running hackbench. Measuring > suggests that performance is improved by between half and one > percent, which isn't fantastic but then I don't know how much > of hackbench's runtime is bottlenecked by TLB flushes. I would > expect that a workload that actually used EL2 and EL3 will > benefit by not having the EL2 and EL3 flushes taking out the > EL1&0 TLB too. > > Disclaimer: the EL2 and EL3 parts of this code are untested > because we haven't completely implemented those for AArch64 yet. > > > Peter Maydell (6): > cputlb: Add functions for flushing TLB for a single MMU index > target-arm: Move TLBI ALLE1/ALLE1IS definitions into numeric order > target-arm: Restrict AArch64 TLB flushes to the MMU indexes they must > touch > target-arm: Implement missing EL2 TLBI operations > target-arm: Implement missing EL3 TLB invalidate operations > target-arm: Implement AArch64 TLBI operations on IPAs > > cputlb.c | 81 ++++++++++++ > include/exec/exec-all.h | 47 +++++++ > target-arm/helper.c | 329 +++++++++++++++++++++++++++++++++++++++++------- > 3 files changed, 412 insertions(+), 45 deletions(-) > > -- > 1.9.1 >