> I meant without polling. Does the hardware design prevent from using I2C in 
> interrupt mode in a race-free way ?

Yes, when we get a NACK after address phase. HW automatically creates a
STOP condition after a NACK. After this STOP, if we haven't been fast
enough to clear the ESG bit (which started the address phase), then it
will be still set and a new message will be created.