From mboxrd@z Thu Jan  1 00:00:00 1970
From: Marek Vasut <marex@denx.de>
Date: Fri, 23 Oct 2015 20:17:06 +0200
Subject: [U-Boot] [PATCH v4 18/24] spi: cadence_qspi_apb: Use GENMASK
In-Reply-To: <CAD6G_RRt4zSkd+Ng5NLbxR=Esu8zWe1Tg--zx_T9Xtsmi+HkCA@mail.gmail.com>
References: <1445547024-7774-1-git-send-email-jteki@openedev.com>
 <20151022212523.GM23893@bill-the-cat>
 <CAD6G_RRt4zSkd+Ng5NLbxR=Esu8zWe1Tg--zx_T9Xtsmi+HkCA@mail.gmail.com>
Message-ID: <201510232017.06640.marex@denx.de>
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On Friday, October 23, 2015 at 07:17:28 PM, Jagan Teki wrote:
> On 23 October 2015 at 02:55, Tom Rini <trini@konsulko.com> wrote:
> > On Thu, Oct 22, 2015 at 07:10:17PM -0200, Fabio Estevam wrote:
> >> On Thu, Oct 22, 2015 at 6:50 PM, Jagan Teki <jteki@openedev.com> wrote:
> >> >         reg &= ~(CQSPI_REG_CONFIG_CHIPSELECT_MASK
> >> > 
> >> > @@ -719,7 +719,7 @@ int cadence_qspi_apb_indirect_read_setup(struct
> >> > cadence_spi_platdata *plat,
> >> > 
> >> >  #if defined(CONFIG_SPL_SPI_XIP) && defined(CONFIG_SPL_BUILD)
> >> >  
> >> >                 writel(0x0, plat->regbase + CQSPI_REG_MODE_BIT);
> >> >  
> >> >  #else
> >> > 
> >> > -               writel(0xFF, plat->regbase + CQSPI_REG_MODE_BIT);
> >> > +               writel(GENMASK(7, 0), plat->regbase +
> >> > CQSPI_REG_MODE_BIT);
> >> 
> >> Is the 0xFF really a mask here? It seems it is just writing 0xFF to
> >> the register directly without any masking operation.
> 
> As register got initialized to all 1's like masking all to set may be
> we can add a macro like MODE_BIT_MASK and then will assign GENMASK to
> that.

Please keep the 0xff value, I agree with Fabio.

Best regards,
Marek Vasut