From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756173AbbJ1TJy (ORCPT ); Wed, 28 Oct 2015 15:09:54 -0400 Received: from foss.arm.com ([217.140.101.70]:35991 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752375AbbJ1TJx (ORCPT ); Wed, 28 Oct 2015 15:09:53 -0400 Date: Wed, 28 Oct 2015 19:09:49 +0000 From: Catalin Marinas To: Robert Richter Cc: Will Deacon , Robert Richter , Tirumalesh Chalamarla , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: Re: [PATCH] arm64: Increase the max granular size Message-ID: <20151028190948.GJ8899@e104818-lin.cambridge.arm.com> References: <1442944788-17254-1-git-send-email-rric@kernel.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1442944788-17254-1-git-send-email-rric@kernel.org> User-Agent: Mutt/1.5.23 (2014-03-12) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, Sep 22, 2015 at 07:59:48PM +0200, Robert Richter wrote: > From: Tirumalesh Chalamarla > > Increase the standard cacheline size to avoid having locks in the same > cacheline. > > Cavium's ThunderX core implements cache lines of 128 byte size. With > current granulare size of 64 bytes (L1_CACHE_SHIFT=6) two locks could > share the same cache line leading a performance degradation. > Increasing the size fixes that. > > Increasing the size has no negative impact to cache invalidation on > systems with a smaller cache line. There is an impact on memory usage, > but that's not too important for arm64 use cases. > > Signed-off-by: Tirumalesh Chalamarla > Signed-off-by: Robert Richter Applied. Thanks. -- Catalin From mboxrd@z Thu Jan 1 00:00:00 1970 From: catalin.marinas@arm.com (Catalin Marinas) Date: Wed, 28 Oct 2015 19:09:49 +0000 Subject: [PATCH] arm64: Increase the max granular size In-Reply-To: <1442944788-17254-1-git-send-email-rric@kernel.org> References: <1442944788-17254-1-git-send-email-rric@kernel.org> Message-ID: <20151028190948.GJ8899@e104818-lin.cambridge.arm.com> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On Tue, Sep 22, 2015 at 07:59:48PM +0200, Robert Richter wrote: > From: Tirumalesh Chalamarla > > Increase the standard cacheline size to avoid having locks in the same > cacheline. > > Cavium's ThunderX core implements cache lines of 128 byte size. With > current granulare size of 64 bytes (L1_CACHE_SHIFT=6) two locks could > share the same cache line leading a performance degradation. > Increasing the size fixes that. > > Increasing the size has no negative impact to cache invalidation on > systems with a smaller cache line. There is an impact on memory usage, > but that's not too important for arm64 use cases. > > Signed-off-by: Tirumalesh Chalamarla > Signed-off-by: Robert Richter Applied. Thanks. -- Catalin