From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:50818) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZwJsl-00048u-W0 for qemu-devel@nongnu.org; Tue, 10 Nov 2015 20:07:29 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ZwJsk-0005xm-G9 for qemu-devel@nongnu.org; Tue, 10 Nov 2015 20:07:27 -0500 Date: Wed, 11 Nov 2015 11:46:50 +1100 From: David Gibson Message-ID: <20151111004650.GA5852@voom.redhat.com> References: <1446795779-28086-1-git-send-email-bharata@linux.vnet.ibm.com> <1446844375.14282.34.camel@kernel.crashing.org> <564144CE.2000603@ozlabs.ru> <20151110052945.GF14232@in.ibm.com> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha1; protocol="application/pgp-signature"; boundary="nFreZHaLTZJo0R7j" Content-Disposition: inline In-Reply-To: <20151110052945.GF14232@in.ibm.com> Subject: Re: [Qemu-devel] [PATCH] ppc: Add/Re-introduce MMU model definitions needed by PR KVM List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Bharata B Rao Cc: Alexey Kardashevskiy , qemu-ppc@nongnu.org, qemu-devel@nongnu.org, aneesh.kumar@linux.vnet.ibm.com --nFreZHaLTZJo0R7j Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Tue, Nov 10, 2015 at 10:59:45AM +0530, Bharata B Rao wrote: > On Tue, Nov 10, 2015 at 12:13:50PM +1100, Alexey Kardashevskiy wrote: > > On 11/07/2015 08:12 AM, Benjamin Herrenschmidt wrote: > > >On Fri, 2015-11-06 at 13:12 +0530, Bharata B Rao wrote: > > >>Commit aa4bb5875231 (ppc: Add mmu_model defines for arch 2.03 and > > >>2.07) > > >>removed the mmu_model definition POWERPC_MMU_2_06a which is needed by > > >>PR KVM. Reintroduce it and also add POWERPC_MMU_2_07a. > > >> > > >>This fixes QEMU crash (qemu: fatal: Unknown MMU model) during booting > > >>of PR KVM guest. > > > > > >Hrm, I see... we clear the 1TSEG bit and that causes the switch/cases > > >to no long work. Argh.... > > > > > >We should clean up that junk. We are mixing up bit masks and an actual > > >model "number" in the same field. We should make that cleaner, using > > >a mask to extract the actual version and switch/case on *that*... > >=20 > >=20 > > I like this and I wonder if Bharata is going to do this, if not, I will= , I > > just noticed this this patch made it to the dwg/spapr-next tree so we n= eed > > to hurry... > >=20 > > Bharata, got some time for this? Thanks. >=20 > I can only get to this tomorrow, so if it is urgent please feel free > to work on this. >=20 > Meanwhile I have gotten till this point, very lightly tested though > and patch description needs update. This looks like a good start on a cleanup, but I'm disinclined to merge it now, right before the hard freeze. The mixing of model IDs and feature bits is ugly, but it's been there for a long while - we can cope with it for a bit longer. >=20 > Regards, > Bharata. >=20 > ppc: Add/Re-introduce MMU model definitions needed by PR KVM >=20 > From: Bharata B Rao >=20 > Commit aa4bb5875231 (ppc: Add mmu_model defines for arch 2.03 and 2.07) > removed the mmu_model definition POWERPC_MMU_2_06a which is needed by > PR KVM. Reintroduce it and also add POWERPC_MMU_2_07a. >=20 > This fixes QEMU crash (qemu: fatal: Unknown MMU model) during booting > of PR KVM guest. >=20 > Signed-off-by: Bharata B Rao > Cc: Benjamin Herrenschmidt > --- > target-ppc/cpu.h | 25 +++++++++++++++---------- > target-ppc/mmu_helper.c | 8 ++++---- > target-ppc/translate_init.c | 11 +++++++---- > 3 files changed, 26 insertions(+), 18 deletions(-) >=20 > diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h > index b34aed6..2c4a10a 100644 > --- a/target-ppc/cpu.h > +++ b/target-ppc/cpu.h > @@ -88,6 +88,17 @@ > =20 > /***********************************************************************= ******/ > /* MMU model = */ > + > +#if defined(TARGET_PPC64) > +#define POWERPC_MMU_64 0x00010000 > +#define POWERPC_MMU_1TSEG 0x00020000 > +#define POWERPC_MMU_AMR 0x00040000 > +#define POWERPC_MMU_MASK ~(POWERPC_MMU_64 | POWERPC_MMU_1TSEG | \ > + POWERPC_MMU_AMR) > +#else > +#define POWERPC_MMU_MASK ~0 > +#endif > + > typedef enum powerpc_mmu_t powerpc_mmu_t; > enum powerpc_mmu_t { > POWERPC_MMU_UNKNOWN =3D 0x00000000, > @@ -112,19 +123,13 @@ enum powerpc_mmu_t { > /* PowerPC 601 MMU model (specific BATs format) */ > POWERPC_MMU_601 =3D 0x0000000A, > #if defined(TARGET_PPC64) > -#define POWERPC_MMU_64 0x00010000 > -#define POWERPC_MMU_1TSEG 0x00020000 > -#define POWERPC_MMU_AMR 0x00040000 > /* 64 bits PowerPC MMU */ > - POWERPC_MMU_64B =3D POWERPC_MMU_64 | 0x00000001, > - /* Architecture 2.03 and later (has LPCR) */ > - POWERPC_MMU_2_03 =3D POWERPC_MMU_64 | 0x00000002, > + POWERPC_MMU_64B =3D 0x0000000B, > + POWERPC_MMU_2_03 =3D 0x0000000C, > /* Architecture 2.06 variant */ > - POWERPC_MMU_2_06 =3D POWERPC_MMU_64 | POWERPC_MMU_1TSEG > - | POWERPC_MMU_AMR | 0x00000003, > + POWERPC_MMU_2_06 =3D 0x0000000D, > /* Architecture 2.07 variant */ > - POWERPC_MMU_2_07 =3D POWERPC_MMU_64 | POWERPC_MMU_1TSEG > - | POWERPC_MMU_AMR | 0x00000004, > + POWERPC_MMU_2_07 =3D 0x0000000E, > #endif /* defined(TARGET_PPC64) */ > }; > =20 > diff --git a/target-ppc/mmu_helper.c b/target-ppc/mmu_helper.c > index e52d0e5..9dead4b 100644 > --- a/target-ppc/mmu_helper.c > +++ b/target-ppc/mmu_helper.c > @@ -1280,7 +1280,7 @@ static void mmu6xx_dump_mmu(FILE *f, fprintf_functi= on cpu_fprintf, > =20 > void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUPPCState *env) > { > - switch (env->mmu_model) { > + switch (env->mmu_model & POWERPC_MMU_MASK) { > case POWERPC_MMU_BOOKE: > mmubooke_dump_mmu(f, cpu_fprintf, env); > break; > @@ -1430,7 +1430,7 @@ hwaddr ppc_cpu_get_phys_page_debug(CPUState *cs, va= ddr addr) > CPUPPCState *env =3D &cpu->env; > mmu_ctx_t ctx; > =20 > - switch (env->mmu_model) { > + switch (env->mmu_model & POWERPC_MMU_MASK) { > #if defined(TARGET_PPC64) > case POWERPC_MMU_64B: > case POWERPC_MMU_2_03: > @@ -1911,7 +1911,7 @@ void ppc_tlb_invalidate_all(CPUPPCState *env) > { > PowerPCCPU *cpu =3D ppc_env_get_cpu(env); > =20 > - switch (env->mmu_model) { > + switch (env->mmu_model & POWERPC_MMU_MASK) { > case POWERPC_MMU_SOFT_6xx: > case POWERPC_MMU_SOFT_74xx: > ppc6xx_tlb_invalidate_all(env); > @@ -1957,7 +1957,7 @@ void ppc_tlb_invalidate_one(CPUPPCState *env, targe= t_ulong addr) > CPUState *cs; > =20 > addr &=3D TARGET_PAGE_MASK; > - switch (env->mmu_model) { > + switch (env->mmu_model & POWERPC_MMU_MASK) { > case POWERPC_MMU_SOFT_6xx: > case POWERPC_MMU_SOFT_74xx: > ppc6xx_tlb_invalidate_virt(env, addr, 0); > diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c > index 4934c80..a19aa32 100644 > --- a/target-ppc/translate_init.c > +++ b/target-ppc/translate_init.c > @@ -7967,7 +7967,7 @@ POWERPC_FAMILY(970)(ObjectClass *oc, void *data) > (1ull << MSR_DR) | > (1ull << MSR_PMM) | > (1ull << MSR_RI); > - pcc->mmu_model =3D POWERPC_MMU_64B; > + pcc->mmu_model =3D POWERPC_MMU_64B | POWERPC_MMU_64; > #if defined(CONFIG_SOFTMMU) > pcc->handle_mmu_fault =3D ppc_hash64_handle_mmu_fault; > #endif > @@ -8020,7 +8020,8 @@ POWERPC_FAMILY(POWER5P)(ObjectClass *oc, void *data) > (1ull << MSR_DR) | > (1ull << MSR_PMM) | > (1ull << MSR_RI); > - pcc->mmu_model =3D POWERPC_MMU_2_03; > + /* Architecture 2.03 and later (has LPCR) */ > + pcc->mmu_model =3D POWERPC_MMU_2_03 | POWERPC_MMU_64; > #if defined(CONFIG_SOFTMMU) > pcc->handle_mmu_fault =3D ppc_hash64_handle_mmu_fault; > #endif > @@ -8164,7 +8165,8 @@ POWERPC_FAMILY(POWER7)(ObjectClass *oc, void *data) > (1ull << MSR_PMM) | > (1ull << MSR_RI) | > (1ull << MSR_LE); > - pcc->mmu_model =3D POWERPC_MMU_2_06; > + pcc->mmu_model =3D POWERPC_MMU_2_06 | POWERPC_MMU_64 | POWERPC_MMU_1= TSEG | > + POWERPC_MMU_AMR; > #if defined(CONFIG_SOFTMMU) > pcc->handle_mmu_fault =3D ppc_hash64_handle_mmu_fault; > #endif > @@ -8244,7 +8246,8 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data) > (1ull << MSR_PMM) | > (1ull << MSR_RI) | > (1ull << MSR_LE); > - pcc->mmu_model =3D POWERPC_MMU_2_07; > + pcc->mmu_model =3D POWERPC_MMU_2_07 | POWERPC_MMU_64 | POWERPC_MMU_1= TSEG | > + POWERPC_MMU_AMR; > #if defined(CONFIG_SOFTMMU) > pcc->handle_mmu_fault =3D ppc_hash64_handle_mmu_fault; > #endif >=20 --=20 David Gibson | I'll have my music baroque, and my code david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_ | _way_ _around_! http://www.ozlabs.org/~dgibson --nFreZHaLTZJo0R7j Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAEBAgAGBQJWQo/6AAoJEGw4ysog2bOSla4P/jOGA9w1b8L7X/bdGaPQCQ7m m2G03vVTDOYsJ+0R4/VoNSRx/ewM3R4c/zz09jYNYIEFXcxln7c9IVY66dKWLYRo DxJbhWKxVKXLj535sP88S5Kk4KmUmJp2fUXPyZfTk2olYruieQx7yasVcY6F7KmI ifjvxqnxngI6YP3vfwYtaB/4IWzewHsyB2TP+oLZyfeWwTRL3WXzMNR+KvoeIsTI hXo3jIn5hUWfvqpae7P9vLNZ1JghS7sA9xrnTRMqLVWOVYDupx1mIhBuiYd7YUy8 W6Vg2GpQeOsHApZYieFbgVPg+/j7tvdsm5gqe6GO9Ew+RJuoBprzF4KWYeajDcdt iw7VQHtJy1srwqZRLc5sfc+MvldDB8Bd0YL0CZ04iuFGqrFP8cxFokMYtMIL9pNk 7hCY9vV5hPHz09Fcx3903f0QWPk9exiZpxD7gi3pmieGo9t/JkLJNDsZ1Un2Zo2e 2w2UBvpB0Azd6PHpnySNegRExmbleogc8/dEFitnn2ZF7ZURqfwI0AfR5tBu5MDd ZM6mpLMutwr02nfctd8QXRYTGKs3P1fV/BlvOgOVy7TB88q5wSxmY8oYOnh2goQT cGwFipRWoTO5JOR4HfOXxhKCeqlLAZGuQc8olUkqCVE9IzgEx/qg7CRYp1WGQaYv 1cC8zdNtoYwAwCn2AP8I =OHKW -----END PGP SIGNATURE----- --nFreZHaLTZJo0R7j--