On Wed, Nov 11, 2015 at 11:27:25AM +1100, Benjamin Herrenschmidt wrote:
> We use an env. flag which is set to the initial value of MSR_HVB in
> the msr_mask. We also adjust the POWER8 mask to set SHV.
> 
> Also use this to adjust ctx.hv so that it is *set* when the processor
> doesn't have an HV mode (970 with Apple mode for example), thus enabling
> hypervisor instructions/SPRs.
> 
> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>

Reviewed-by: David Gibson <david@gibson.dropbear.id.au>

> ---
>  target-ppc/cpu.h            |  4 ++++
>  target-ppc/translate.c      |  4 +++-
>  target-ppc/translate_init.c | 21 ++++++++++++++++-----
>  3 files changed, 23 insertions(+), 6 deletions(-)
> 
> diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
> index 357b6e7..062644e 100644
> --- a/target-ppc/cpu.h
> +++ b/target-ppc/cpu.h
> @@ -1113,6 +1113,10 @@ struct CPUPPCState {
>      hwaddr mpic_iack;
>      /* true when the external proxy facility mode is enabled */
>      bool mpic_proxy;
> +    /* set when the processor has an HV mode, thus HV priv
> +     * instructions and SPRs are diallowed if MSR:HV is 0
> +     */
> +    bool has_hv_mode;
>  #endif
>  
>      /* Those resources are used only during code translation */
> diff --git a/target-ppc/translate.c b/target-ppc/translate.c
> index a2fe1b5..10eb9e3 100644
> --- a/target-ppc/translate.c
> +++ b/target-ppc/translate.c
> @@ -11465,8 +11465,10 @@ void gen_intermediate_code(CPUPPCState *env, struct TranslationBlock *tb)
>      ctx.exception = POWERPC_EXCP_NONE;
>      ctx.spr_cb = env->spr_cb;
>      ctx.pr = msr_pr;
> -    ctx.hv = !msr_pr && msr_hv;
>      ctx.mem_idx = env->dmmu_idx;
> +#if !defined(CONFIG_USER_ONLY)
> +    ctx.hv = !msr_pr && (msr_hv || !env->has_hv_mode);
> +#endif
>      ctx.insns_flags = env->insns_flags;
>      ctx.insns_flags2 = env->insns_flags2;
>      ctx.access_type = -1;
> diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
> index 7bcfbc0..76f20ea 100644
> --- a/target-ppc/translate_init.c
> +++ b/target-ppc/translate_init.c
> @@ -8391,7 +8391,8 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data)
>                          PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 |
>                          PPC2_TM;
>      pcc->msr_mask = (1ull << MSR_SF) |
> -                    (1ull << MSR_TM) |
> +                    (1ull << MSR_SHV) |
> +		    (1ull << MSR_TM) |
>                      (1ull << MSR_VR) |
>                      (1ull << MSR_VSX) |
>                      (1ull << MSR_EE) |
> @@ -9748,10 +9749,7 @@ static void ppc_cpu_reset(CPUState *s)
>      pcc->parent_reset(s);
>  
>      msr = (target_ulong)0;
> -    if (0) {
> -        /* XXX: find a suitable condition to enable the hypervisor mode */
> -        msr |= (target_ulong)MSR_HVB;
> -    }
> +    msr |= (target_ulong)MSR_HVB;
>      msr |= (target_ulong)0 << MSR_AP; /* TO BE CHECKED */
>      msr |= (target_ulong)0 << MSR_SA; /* TO BE CHECKED */
>      msr |= (target_ulong)1 << MSR_EP;
> @@ -9852,6 +9850,19 @@ static void ppc_cpu_initfn(Object *obj)
>      env->bfd_mach = pcc->bfd_mach;
>      env->check_pow = pcc->check_pow;
>  
> +    /* Mark HV mode as supported if the CPU has an MSR_HV bit
> +     * in the msr_mask. The mask can later be cleared by PAPR
> +     * mode but the hv mode support will remain, thus enforcing
> +     * that we cannot use priv. instructions in guest in PAPR
> +     * mode. For 970 we currently simply don't set HV in msr_mask
> +     * thus simulating an "Apple mode" 970. If we ever want to
> +     * support 970 HV mode, we'll have to add a processor attribute
> +     * of some sort.
> +     */
> +#if !defined(CONFIG_USER_ONLY)
> +    env->has_hv_mode = !!(env->msr_mask & MSR_HVB);
> +#endif
> +
>  #if defined(TARGET_PPC64)
>      if (pcc->sps) {
>          env->sps = *pcc->sps;

-- 
David Gibson			| I'll have my music baroque, and my code
david AT gibson.dropbear.id.au	| minimalist, thank you.  NOT _the_ _other_
				| _way_ _around_!
http://www.ozlabs.org/~dgibson