From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:42097) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1a3d3F-0001eH-10 for qemu-devel@nongnu.org; Tue, 01 Dec 2015 00:00:31 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1a3d3B-00055H-UT for qemu-devel@nongnu.org; Tue, 01 Dec 2015 00:00:28 -0500 Date: Tue, 1 Dec 2015 15:30:53 +1100 From: David Gibson Message-ID: <20151201043053.GP31343@voom.redhat.com> References: <1447201710-10229-1-git-send-email-benh@kernel.crashing.org> <1447201710-10229-34-git-send-email-benh@kernel.crashing.org> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha1; protocol="application/pgp-signature"; boundary="24/piotZLKF/SXqU" Content-Disposition: inline In-Reply-To: <1447201710-10229-34-git-send-email-benh@kernel.crashing.org> Subject: Re: [Qemu-devel] [Qemu-ppc] [PATCH 33/77] ppc/xics: Make the ICSState a list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Benjamin Herrenschmidt Cc: qemu-ppc@nongnu.org, qemu-devel@nongnu.org --24/piotZLKF/SXqU Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Wed, Nov 11, 2015 at 11:27:46AM +1100, Benjamin Herrenschmidt wrote: > Instead of an array of fixed sized blocks, use a list, as we will need > to have sources with variable number of interrupts. SPAPR only uses > a single entry. Native will create more. If performance becomes an > issue we can add some hashed lookup but for now this will do fine. >=20 > Signed-off-by: Benjamin Herrenschmidt > --- > hw/intc/xics.c | 86 +++++++++++++++++++++++++++++++--------------= ------ > hw/intc/xics_kvm.c | 28 +++++++++-------- > hw/intc/xics_spapr.c | 75 ++++++++++++++++++++++++-------------------- > hw/ppc/spapr_events.c | 2 +- > hw/ppc/spapr_pci.c | 4 +-- > hw/ppc/spapr_vio.c | 2 +- > include/hw/ppc/xics.h | 10 +++--- > 7 files changed, 118 insertions(+), 89 deletions(-) >=20 > diff --git a/hw/intc/xics.c b/hw/intc/xics.c > index d21471f..c4ac057 100644 > --- a/hw/intc/xics.c > +++ b/hw/intc/xics.c > @@ -79,13 +79,16 @@ void xics_cpu_setup(XICSState *xics, PowerPCCPU *cpu) > static void xics_common_reset(DeviceState *d) > { > XICSState *xics =3D XICS_COMMON(d); > + ICSState *ics; > int i; > =20 > for (i =3D 0; i < xics->nr_servers; i++) { > device_reset(DEVICE(&xics->ss[i])); > } > =20 > - device_reset(DEVICE(xics->ics)); > + QLIST_FOREACH(ics, &xics->ics, list) { > + device_reset(DEVICE(ics)); > + } > } > =20 > static void xics_prop_get_nr_irqs(Object *obj, Visitor *v, > @@ -117,7 +120,6 @@ static void xics_prop_set_nr_irqs(Object *obj, Visito= r *v, > } > =20 > assert(info->set_nr_irqs); > - assert(xics->ics); > info->set_nr_irqs(xics, value, errp); > } > =20 > @@ -195,33 +197,35 @@ static void ics_reject(ICSState *ics, int nr); > static void ics_resend(ICSState *ics); > static void ics_eoi(ICSState *ics, int nr); > =20 > -static void icp_check_ipi(XICSState *xics, int server) > +static void icp_check_ipi(ICPState *ss, int server) > { > - ICPState *ss =3D xics->ss + server; > - > if (XISR(ss) && (ss->pending_priority <=3D ss->mfrr)) { > return; > } > =20 > trace_xics_icp_check_ipi(server, ss->mfrr); > =20 > - if (XISR(ss)) { > - ics_reject(xics->ics, XISR(ss)); > + if (XISR(ss) && ss->xirr_owner) { > + ics_reject(ss->xirr_owner, XISR(ss)); > } > =20 > ss->xirr =3D (ss->xirr & ~XISR_MASK) | XICS_IPI; > ss->pending_priority =3D ss->mfrr; > + ss->xirr_owner =3D NULL; > qemu_irq_raise(ss->output); > } > =20 > static void icp_resend(XICSState *xics, int server) > { > ICPState *ss =3D xics->ss + server; > + ICSState *ics; > =20 > if (ss->mfrr < CPPR(ss)) { > - icp_check_ipi(xics, server); > + icp_check_ipi(ss, server); > + } > + QLIST_FOREACH(ics, &xics->ics, list) { > + ics_resend(ics); > } > - ics_resend(xics->ics); > } > =20 > void icp_set_cppr(XICSState *xics, int server, uint8_t cppr) > @@ -239,7 +243,10 @@ void icp_set_cppr(XICSState *xics, int server, uint8= _t cppr) > ss->xirr &=3D ~XISR_MASK; /* Clear XISR */ > ss->pending_priority =3D 0xff; > qemu_irq_lower(ss->output); > - ics_reject(xics->ics, old_xisr); > + if (ss->xirr_owner) { > + ics_reject(ss->xirr_owner, old_xisr); > + ss->xirr_owner =3D NULL; > + } To match the layour of the rest of things, this little fragment should probably go into an icp_reject() function. > } > } else { > if (!XISR(ss)) { > @@ -254,7 +261,7 @@ void icp_set_mfrr(XICSState *xics, int server, uint8_= t mfrr) > =20 > ss->mfrr =3D mfrr; > if (mfrr < CPPR(ss)) { > - icp_check_ipi(xics, server); > + icp_check_ipi(ss, server); > } > } > =20 > @@ -265,6 +272,7 @@ uint32_t icp_accept(ICPState *ss) > qemu_irq_lower(ss->output); > ss->xirr =3D ss->pending_priority << 24; > ss->pending_priority =3D 0xff; > + ss->xirr_owner =3D NULL; > =20 > trace_xics_icp_accept(xirr, ss->xirr); > =20 > @@ -282,30 +290,40 @@ uint32_t icp_ipoll(ICPState *ss, uint32_t *mfrr) > void icp_eoi(XICSState *xics, int server, uint32_t xirr) > { > ICPState *ss =3D xics->ss + server; > + ICSState *ics; > + uint32_t irq; > =20 > /* Send EOI -> ICS */ > ss->xirr =3D (ss->xirr & ~CPPR_MASK) | (xirr & CPPR_MASK); > trace_xics_icp_eoi(server, xirr, ss->xirr); > - ics_eoi(xics->ics, xirr & XISR_MASK); > + irq =3D xirr & XISR_MASK; > + QLIST_FOREACH(ics, &xics->ics, list) { > + if (ics_valid_irq(ics, irq)) { > + ics_eoi(ics, irq); > + } > + } > if (!XISR(ss)) { > icp_resend(xics, server); > } > } > =20 > -static void icp_irq(XICSState *xics, int server, int nr, uint8_t priorit= y) > +static void icp_irq(ICSState *ics, int server, int nr, uint8_t priority) > { > + XICSState *xics =3D ics->xics; > ICPState *ss =3D xics->ss + server; > =20 > trace_xics_icp_irq(server, nr, priority); > =20 > if ((priority >=3D CPPR(ss)) > || (XISR(ss) && (ss->pending_priority <=3D priority))) { > - ics_reject(xics->ics, nr); > + ics_reject(ics, nr); > } else { > - if (XISR(ss)) { > - ics_reject(xics->ics, XISR(ss)); > + if (XISR(ss) && ss->xirr_owner) { I'm guessing the only case where we should get XISR(ss) && !ss->xirr_owner will be an IPI, is that right? > + ics_reject(ss->xirr_owner, XISR(ss)); > + ss->xirr_owner =3D NULL; > } > ss->xirr =3D (ss->xirr & ~XISR_MASK) | (nr & XISR_MASK); > + ss->xirr_owner =3D ics; > ss->pending_priority =3D priority; > trace_xics_icp_raise(ss->xirr, ss->pending_priority); > qemu_irq_raise(ss->output); > @@ -388,8 +406,7 @@ static void resend_msi(ICSState *ics, int srcno) > if (irq->status & XICS_STATUS_REJECTED) { > irq->status &=3D ~XICS_STATUS_REJECTED; > if (irq->priority !=3D 0xff) { > - icp_irq(ics->xics, irq->server, srcno + ics->offset, > - irq->priority); > + icp_irq(ics, irq->server, srcno + ics->offset, irq->priority= ); > } > } > } > @@ -402,7 +419,7 @@ static void resend_lsi(ICSState *ics, int srcno) > && (irq->status & XICS_STATUS_ASSERTED) > && !(irq->status & XICS_STATUS_SENT)) { > irq->status |=3D XICS_STATUS_SENT; > - icp_irq(ics->xics, irq->server, srcno + ics->offset, irq->priori= ty); > + icp_irq(ics, irq->server, srcno + ics->offset, irq->priority); > } > } > =20 > @@ -417,7 +434,7 @@ static void set_irq_msi(ICSState *ics, int srcno, int= val) > irq->status |=3D XICS_STATUS_MASKED_PENDING; > trace_xics_masked_pending(); > } else { > - icp_irq(ics->xics, irq->server, srcno + ics->offset, irq->pr= iority); > + icp_irq(ics, irq->server, srcno + ics->offset, irq->priority= ); > } > } > } > @@ -456,7 +473,7 @@ static void write_xive_msi(ICSState *ics, int srcno) > } > =20 > irq->status &=3D ~XICS_STATUS_MASKED_PENDING; > - icp_irq(ics->xics, irq->server, srcno + ics->offset, irq->priority); > + icp_irq(ics, irq->server, srcno + ics->offset, irq->priority); > } > =20 > static void write_xive_lsi(ICSState *ics, int srcno) > @@ -642,28 +659,23 @@ static const TypeInfo ics_info =3D { > /* > * Exported functions > */ > -int xics_find_source(XICSState *xics, int irq) > +ICSState *xics_find_source(XICSState *xics, int irq) > { > - int sources =3D 1; > - int src; > + ICSState *ics; > =20 > - /* FIXME: implement multiple sources */ > - for (src =3D 0; src < sources; ++src) { > - ICSState *ics =3D &xics->ics[src]; > + QLIST_FOREACH(ics, &xics->ics, list) { > if (ics_valid_irq(ics, irq)) { > - return src; > + return ics; > } > } > - > - return -1; > + return NULL; > } > =20 > qemu_irq xics_get_qirq(XICSState *xics, int irq) > { > - int src =3D xics_find_source(xics, irq); > + ICSState *ics =3D xics_find_source(xics, irq); > =20 > - if (src >=3D 0) { > - ICSState *ics =3D &xics->ics[src]; > + if (ics) { > return ics->qirqs[irq - ics->offset]; > } > =20 > @@ -684,7 +696,13 @@ void ics_set_irq_type(ICSState *ics, int srcno, bool= lsi) > =20 > void xics_set_nr_irqs(XICSState *xics, uint32_t nr_irqs, Error **errp) > { > - xics->nr_irqs =3D xics->ics->nr_irqs =3D nr_irqs; > + ICSState *ics =3D QLIST_FIRST(&xics->ics); > + > + /* This needs to be deprecated ... */ Yeah.. I can't even remember what this was really for. We probably need to move it to a property on the ics objects, with a backwards compat shim for PAPR to copy the xics "master" object value to the single ics. > + xics->nr_irqs =3D nr_irqs; > + if (ics) { > + ics->nr_irqs =3D nr_irqs; > + } > } > =20 > void xics_set_nr_servers(XICSState *xics, uint32_t nr_servers, Error **e= rrp) > diff --git a/hw/intc/xics_kvm.c b/hw/intc/xics_kvm.c > index 7d86157..a478d25 100644 > --- a/hw/intc/xics_kvm.c > +++ b/hw/intc/xics_kvm.c > @@ -356,11 +356,6 @@ static void xics_kvm_cpu_setup(XICSState *xics, Powe= rPCCPU *cpu) > } > } > =20 > -static void xics_kvm_set_nr_irqs(XICSState *xics, uint32_t nr_irqs, Erro= r **errp) > -{ > - xics->nr_irqs =3D xics->ics->nr_irqs =3D nr_irqs; > -} > - > static void xics_kvm_set_nr_servers(XICSState *xics, uint32_t nr_servers, > Error **errp) > { > @@ -391,6 +386,7 @@ static void xics_kvm_realize(DeviceState *dev, Error = **errp) > { > KVMXICSState *xicskvm =3D KVM_XICS(dev); > XICSState *xics =3D XICS_COMMON(dev); > + ICSState *ics; > int i, rc; > Error *error =3D NULL; > struct kvm_create_device xics_create_device =3D { > @@ -442,10 +438,12 @@ static void xics_kvm_realize(DeviceState *dev, Erro= r **errp) > =20 > xicskvm->kernel_xics_fd =3D xics_create_device.fd; > =20 > - object_property_set_bool(OBJECT(xics->ics), true, "realized", &error= ); > - if (error) { > - error_propagate(errp, error); > - goto fail; > + QLIST_FOREACH(ics, &xics->ics, list) { > + object_property_set_bool(OBJECT(ics), true, "realized", &error); > + if (error) { > + error_propagate(errp, error); > + goto fail; > + } > } > =20 > assert(xics->nr_servers); > @@ -473,10 +471,14 @@ fail: > static void xics_kvm_initfn(Object *obj) > { > XICSState *xics =3D XICS_COMMON(obj); > + ICSState *ics; > + > + QLIST_INIT(&xics->ics); > =20 > - xics->ics =3D ICS(object_new(TYPE_KVM_ICS)); > - object_property_add_child(obj, "ics", OBJECT(xics->ics), NULL); > - xics->ics->xics =3D xics; > + ics =3D ICS(object_new(TYPE_KVM_ICS)); > + object_property_add_child(obj, "ics", OBJECT(ics), NULL); > + ics->xics =3D xics; > + QLIST_INSERT_HEAD(&xics->ics, ics, list); > } > =20 > static void xics_kvm_class_init(ObjectClass *oc, void *data) > @@ -486,7 +488,7 @@ static void xics_kvm_class_init(ObjectClass *oc, void= *data) > =20 > dc->realize =3D xics_kvm_realize; > xsc->cpu_setup =3D xics_kvm_cpu_setup; > - xsc->set_nr_irqs =3D xics_kvm_set_nr_irqs; > + xsc->set_nr_irqs =3D xics_set_nr_irqs; Wow.. why were xics_kvm_set_nr_irqs and xics_set_nr_irqs ever separate, I wonder. > xsc->set_nr_servers =3D xics_kvm_set_nr_servers; > } > =20 > diff --git a/hw/intc/xics_spapr.c b/hw/intc/xics_spapr.c > index fb508cd..d75fcf0 100644 > --- a/hw/intc/xics_spapr.c > +++ b/hw/intc/xics_spapr.c > @@ -111,10 +111,10 @@ static void rtas_set_xive(PowerPCCPU *cpu, sPAPRMac= hineState *spapr, > uint32_t nargs, target_ulong args, > uint32_t nret, target_ulong rets) > { > - ICSState *ics =3D spapr->xics->ics; > + ICSState *ics =3D QLIST_FIRST(&spapr->xics->ics); > uint32_t nr, server, priority; > =20 > - if ((nargs !=3D 3) || (nret !=3D 1)) { > + if ((nargs !=3D 3) || (nret !=3D 1) || !ics) { > rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); > return; > } !ics should probably be a HW_ERROR (or even an assert). > @@ -139,10 +139,10 @@ static void rtas_get_xive(PowerPCCPU *cpu, sPAPRMac= hineState *spapr, > uint32_t nargs, target_ulong args, > uint32_t nret, target_ulong rets) > { > - ICSState *ics =3D spapr->xics->ics; > + ICSState *ics =3D QLIST_FIRST(&spapr->xics->ics); > uint32_t nr; > =20 > - if ((nargs !=3D 1) || (nret !=3D 3)) { > + if ((nargs !=3D 1) || (nret !=3D 3) || !ics) { > rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); > return; > } > @@ -164,10 +164,10 @@ static void rtas_int_off(PowerPCCPU *cpu, sPAPRMach= ineState *spapr, > uint32_t nargs, target_ulong args, > uint32_t nret, target_ulong rets) > { > - ICSState *ics =3D spapr->xics->ics; > + ICSState *ics =3D QLIST_FIRST(&spapr->xics->ics); > uint32_t nr; > =20 > - if ((nargs !=3D 1) || (nret !=3D 1)) { > + if ((nargs !=3D 1) || (nret !=3D 1) || !ics) { > rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); > return; > } > @@ -190,10 +190,10 @@ static void rtas_int_on(PowerPCCPU *cpu, sPAPRMachi= neState *spapr, > uint32_t nargs, target_ulong args, > uint32_t nret, target_ulong rets) > { > - ICSState *ics =3D spapr->xics->ics; > + ICSState *ics =3D QLIST_FIRST(&spapr->xics->ics); > uint32_t nr; > =20 > - if ((nargs !=3D 1) || (nret !=3D 1)) { > + if ((nargs !=3D 1) || (nret !=3D 1) || !ics) { > rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); > return; > } > @@ -215,6 +215,7 @@ static void rtas_int_on(PowerPCCPU *cpu, sPAPRMachine= State *spapr, > static void xics_spapr_realize(DeviceState *dev, Error **errp) > { > XICSState *xics =3D XICS(dev); > + ICSState *ics; > Error *error =3D NULL; > int i; > =20 > @@ -236,10 +237,12 @@ static void xics_spapr_realize(DeviceState *dev, Er= ror **errp) > spapr_register_hypercall(H_EOI, h_eoi); > spapr_register_hypercall(H_IPOLL, h_ipoll); > =20 > - object_property_set_bool(OBJECT(xics->ics), true, "realized", &error= ); > - if (error) { > - error_propagate(errp, error); > - return; > + QLIST_FOREACH(ics, &xics->ics, list) { > + object_property_set_bool(OBJECT(ics), true, "realized", &error); > + if (error) { > + error_propagate(errp, error); > + return; > + } > } > =20 > for (i =3D 0; i < xics->nr_servers; i++) { > @@ -254,10 +257,14 @@ static void xics_spapr_realize(DeviceState *dev, Er= ror **errp) > static void xics_spapr_initfn(Object *obj) > { > XICSState *xics =3D XICS(obj); > + ICSState *ics; > + > + QLIST_INIT(&xics->ics); > =20 > - xics->ics =3D ICS(object_new(TYPE_ICS)); > - object_property_add_child(obj, "ics", OBJECT(xics->ics), NULL); > - xics->ics->xics =3D xics; > + ics =3D ICS(object_new(TYPE_ICS)); =20 > + object_property_add_child(obj, "ics", OBJECT(ics), NULL); > + ics->xics =3D xics; > + QLIST_INSERT_HEAD(&xics->ics, ics, list); > } > =20 > static void xics_spapr_class_init(ObjectClass *oc, void *data) > @@ -303,29 +310,31 @@ static int ics_find_free_block(ICSState *ics, int n= um, int alignnum) > return -1; > } > =20 > -int xics_spapr_alloc(XICSState *xics, int src, int irq_hint, bool lsi) > +int xics_spapr_alloc(XICSState *xics, int irq_hint, bool lsi) > { > - ICSState *ics =3D &xics->ics[src]; > + ICSState *ics =3D QLIST_FIRST(&xics->ics); > int irq; > =20 > + if (!ics) { > + return -1; > + } > if (irq_hint) { > - assert(src =3D=3D xics_find_source(xics, irq_hint)); > if (!ICS_IRQ_FREE(ics, irq_hint - ics->offset)) { > - trace_xics_alloc_failed_hint(src, irq_hint); > + trace_xics_alloc_failed_hint(0, irq_hint); > return -1; > } > irq =3D irq_hint; > } else { > irq =3D ics_find_free_block(ics, 1, 1); > if (irq < 0) { > - trace_xics_alloc_failed_no_left(src); > + trace_xics_alloc_failed_no_left(0); > return -1; > } > irq +=3D ics->offset; > } > =20 > ics_set_irq_type(ics, irq - ics->offset, lsi); > - trace_xics_alloc(src, irq); > + trace_xics_alloc(0, irq); Actually we should really deprecate xics_spapr_alloc(). I hadn't realised it at the time, but dynamically allocating resources like this is a PITA for migration and cross-version compatibility. So we should avoid it, instead having the caller explicitly assign numbers based on explicit parameters. > return irq; > } > @@ -334,12 +343,15 @@ int xics_spapr_alloc(XICSState *xics, int src, int = irq_hint, bool lsi) > * Allocate block of consecutive IRQs, and return the number of the firs= t IRQ in the block. > * If align=3D=3Dtrue, aligns the first IRQ number to num. > */ > -int xics_spapr_alloc_block(XICSState *xics, int src, int num, bool lsi, = bool align) > +int xics_spapr_alloc_block(XICSState *xics, int num, bool lsi, bool alig= n) > { > + ICSState *ics =3D QLIST_FIRST(&xics->ics); > int i, first =3D -1; > - ICSState *ics =3D &xics->ics[src]; > =20 > - assert(src =3D=3D 0); > + if (!ics) { > + return -1; > + } > + > /* > * MSIMesage::data is used for storing VIRQ so > * it has to be aligned to num to support multiple > @@ -362,7 +374,7 @@ int xics_spapr_alloc_block(XICSState *xics, int src, = int num, bool lsi, bool ali > } > first +=3D ics->offset; > =20 > - trace_xics_alloc_block(src, first, num, lsi, align); > + trace_xics_alloc_block(0, first, num, lsi, align); > =20 > return first; > } > @@ -373,7 +385,7 @@ static void ics_free(ICSState *ics, int srcno, int nu= m) > =20 > for (i =3D srcno; i < srcno + num; ++i) { > if (ICS_IRQ_FREE(ics, i)) { > - trace_xics_ics_free_warn(ics - ics->xics->ics, i + ics->offs= et); > + trace_xics_ics_free_warn(0, i + ics->offset); > } > memset(&ics->irqs[i], 0, sizeof(ICSIRQState)); > } > @@ -381,15 +393,10 @@ static void ics_free(ICSState *ics, int srcno, int = num) > =20 > void xics_spapr_free(XICSState *xics, int irq, int num) > { > - int src =3D xics_find_source(xics, irq); > - > - if (src >=3D 0) { > - ICSState *ics =3D &xics->ics[src]; > - > - /* FIXME: implement multiple sources */ > - assert(src =3D=3D 0); > + ICSState *ics =3D xics_find_source(xics, irq); > =20 > - trace_xics_ics_free(ics - xics->ics, irq, num); > + if (ics) { > + trace_xics_ics_free(0, irq, num); > ics_free(ics, irq - ics->offset, num); > } > } > diff --git a/hw/ppc/spapr_events.c b/hw/ppc/spapr_events.c > index c06deea..6335ead 100644 > --- a/hw/ppc/spapr_events.c > +++ b/hw/ppc/spapr_events.c > @@ -587,7 +587,7 @@ out_no_events: > void spapr_events_init(sPAPRMachineState *spapr) > { > QTAILQ_INIT(&spapr->pending_events); > - spapr->check_exception_irq =3D xics_spapr_alloc(spapr->xics, 0, 0, f= alse); > + spapr->check_exception_irq =3D xics_spapr_alloc(spapr->xics, 0, fals= e); > spapr->epow_notifier.notify =3D spapr_powerdown_req; > qemu_register_powerdown_notifier(&spapr->epow_notifier); > spapr_rtas_register(RTAS_CHECK_EXCEPTION, "check-exception", > diff --git a/hw/ppc/spapr_pci.c b/hw/ppc/spapr_pci.c > index cf3192e..9b13f85 100644 > --- a/hw/ppc/spapr_pci.c > +++ b/hw/ppc/spapr_pci.c > @@ -351,7 +351,7 @@ static void rtas_ibm_change_msi(PowerPCCPU *cpu, sPAP= RMachineState *spapr, > } > =20 > /* Allocate MSIs */ > - irq =3D xics_spapr_alloc_block(spapr->xics, 0, req_num, false, > + irq =3D xics_spapr_alloc_block(spapr->xics, req_num, false, > ret_intr_type =3D=3D RTAS_TYPE_MSI); > if (!irq) { > error_report("Cannot allocate MSIs for device %x", config_addr); > @@ -1360,7 +1360,7 @@ static void spapr_phb_realize(DeviceState *dev, Err= or **errp) > for (i =3D 0; i < PCI_NUM_PINS; i++) { > uint32_t irq; > =20 > - irq =3D xics_spapr_alloc_block(spapr->xics, 0, 1, true, false); > + irq =3D xics_spapr_alloc_block(spapr->xics, 1, true, false); > if (!irq) { > error_setg(errp, "spapr_allocate_lsi failed"); > return; > diff --git a/hw/ppc/spapr_vio.c b/hw/ppc/spapr_vio.c > index fc731eb..1a84815 100644 > --- a/hw/ppc/spapr_vio.c > +++ b/hw/ppc/spapr_vio.c > @@ -462,7 +462,7 @@ static void spapr_vio_busdev_realize(DeviceState *qde= v, Error **errp) > dev->qdev.id =3D id; > } > =20 > - dev->irq =3D xics_spapr_alloc(spapr->xics, 0, dev->irq, false); > + dev->irq =3D xics_spapr_alloc(spapr->xics, dev->irq, false); > if (!dev->irq) { > error_setg(errp, "can't allocate IRQ"); > return; > diff --git a/include/hw/ppc/xics.h b/include/hw/ppc/xics.h > index e670e89..12fc584 100644 > --- a/include/hw/ppc/xics.h > +++ b/include/hw/ppc/xics.h > @@ -79,7 +79,7 @@ struct XICSState { > uint32_t nr_servers; > uint32_t nr_irqs; > ICPState *ss; > - ICSState *ics; > + QLIST_HEAD(, ICSState) ics; > }; > =20 > #define TYPE_ICP "icp" > @@ -105,6 +105,7 @@ struct ICPState { > DeviceState parent_obj; > /*< public >*/ > CPUState *cs; > + ICSState *xirr_owner; Currently xirr_owner will be lost across migration, which will break things. Am I right in thinking that it's basically an optimization, and could be reconstructed from the XISR value and list of ICS ranges? If so we can do that easily enough in a post_load function. > uint32_t xirr; > uint8_t pending_priority; > uint8_t mfrr; > @@ -139,6 +140,7 @@ struct ICSState { > qemu_irq *qirqs; > ICSIRQState *irqs; > XICSState *xics; > + QLIST_ENTRY(ICSState) list; > }; > =20 > static inline bool ics_valid_irq(ICSState *ics, uint32_t nr) > @@ -167,8 +169,8 @@ struct ICSIRQState { > =20 > qemu_irq xics_get_qirq(XICSState *icp, int irq); > =20 > -int xics_spapr_alloc(XICSState *icp, int src, int irq_hint, bool lsi); > -int xics_spapr_alloc_block(XICSState *icp, int src, int num, bool lsi, b= ool align); > +int xics_spapr_alloc(XICSState *icp, int irq_hint, bool lsi); > +int xics_spapr_alloc_block(XICSState *icp, int num, bool lsi, bool align= ); > void xics_spapr_free(XICSState *icp, int irq, int num); > =20 > void xics_cpu_setup(XICSState *icp, PowerPCCPU *cpu); > @@ -189,6 +191,6 @@ void ics_set_irq_type(ICSState *ics, int srcno, bool = lsi); > =20 > void xics_set_nr_irqs(XICSState *icp, uint32_t nr_irqs, Error **errp); > void xics_set_nr_servers(XICSState *icp, uint32_t nr_servers, Error **er= rp); > -int xics_find_source(XICSState *icp, int irq); > +ICSState *xics_find_source(XICSState *icp, int irq); > =20 > #endif /* __XICS_H__ */ --=20 David Gibson | I'll have my music baroque, and my code david AT gibson.dropbear.id.au | minimalist, thank you. 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