From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1757303AbbLBAlo (ORCPT ); Tue, 1 Dec 2015 19:41:44 -0500 Received: from muru.com ([72.249.23.125]:49962 "EHLO muru.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751883AbbLBAln (ORCPT ); Tue, 1 Dec 2015 19:41:43 -0500 Date: Tue, 1 Dec 2015 16:41:36 -0800 From: Tony Lindgren To: Matthijs van Duin Cc: lkml , "linux-omap@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , Brian Hutchinson , Delio Brignoli , Neil Armstrong , Philipp Rosenberger , Paul Walmsley Subject: Re: [PATCH 05/10] ARM: OMAP2+: Disable GPIO softreset for dm81xx Message-ID: <20151202004136.GW23396@atomide.com> References: <1449013103-23238-1-git-send-email-tony@atomide.com> <1449013103-23238-6-git-send-email-tony@atomide.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.24 (2015-08-30) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org * Matthijs van Duin [151201 16:11]: > On 2 December 2015 at 00:38, Tony Lindgren wrote: > > Looks like GPIO softreset status bit on both dm8168 and dm8148 > > is broken and only goes high initially. After writing to sysc > > softreset bit, the resetdone bit never goes high again. > > The resetdone bit works fine, but it needs all clocks active to come > up. You're neglecting to enable the debounce clock to the GPIO module: > > > # mw.l 0x4818155c 0x2 > > That should write 0x102 instead. It seems to work only once based on what I've seen :) If you try it after it's powered it never works. Could be I'm doing something wrong of course.. > You can disable the debounce clock after resetting the module if you > don't need it, though I doubt there's any significant power savings > there. (More likely it exists as a separate bit to allow it to stay > enabled even if the module isn't, for wakeup on debounced inputs.) Hmm I tried setting HWMOD_CONTROL_OPT_CLKS_IN_RESET flag like we have for many SoCs to enable also sysclk18_ck but no luck. I can recheck that. Regards, Tony From mboxrd@z Thu Jan 1 00:00:00 1970 From: Tony Lindgren Subject: Re: [PATCH 05/10] ARM: OMAP2+: Disable GPIO softreset for dm81xx Date: Tue, 1 Dec 2015 16:41:36 -0800 Message-ID: <20151202004136.GW23396@atomide.com> References: <1449013103-23238-1-git-send-email-tony@atomide.com> <1449013103-23238-6-git-send-email-tony@atomide.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Return-path: Content-Disposition: inline In-Reply-To: Sender: linux-kernel-owner@vger.kernel.org To: Matthijs van Duin Cc: lkml , "linux-omap@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , Brian Hutchinson , Delio Brignoli , Neil Armstrong , Philipp Rosenberger , Paul Walmsley List-Id: linux-omap@vger.kernel.org * Matthijs van Duin [151201 16:11]: > On 2 December 2015 at 00:38, Tony Lindgren wrote: > > Looks like GPIO softreset status bit on both dm8168 and dm8148 > > is broken and only goes high initially. After writing to sysc > > softreset bit, the resetdone bit never goes high again. > > The resetdone bit works fine, but it needs all clocks active to come > up. You're neglecting to enable the debounce clock to the GPIO module: > > > # mw.l 0x4818155c 0x2 > > That should write 0x102 instead. It seems to work only once based on what I've seen :) If you try it after it's powered it never works. Could be I'm doing something wrong of course.. > You can disable the debounce clock after resetting the module if you > don't need it, though I doubt there's any significant power savings > there. (More likely it exists as a separate bit to allow it to stay > enabled even if the module isn't, for wakeup on debounced inputs.) Hmm I tried setting HWMOD_CONTROL_OPT_CLKS_IN_RESET flag like we have for many SoCs to enable also sysclk18_ck but no luck. I can recheck that. Regards, Tony From mboxrd@z Thu Jan 1 00:00:00 1970 From: tony@atomide.com (Tony Lindgren) Date: Tue, 1 Dec 2015 16:41:36 -0800 Subject: [PATCH 05/10] ARM: OMAP2+: Disable GPIO softreset for dm81xx In-Reply-To: References: <1449013103-23238-1-git-send-email-tony@atomide.com> <1449013103-23238-6-git-send-email-tony@atomide.com> Message-ID: <20151202004136.GW23396@atomide.com> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org * Matthijs van Duin [151201 16:11]: > On 2 December 2015 at 00:38, Tony Lindgren wrote: > > Looks like GPIO softreset status bit on both dm8168 and dm8148 > > is broken and only goes high initially. After writing to sysc > > softreset bit, the resetdone bit never goes high again. > > The resetdone bit works fine, but it needs all clocks active to come > up. You're neglecting to enable the debounce clock to the GPIO module: > > > # mw.l 0x4818155c 0x2 > > That should write 0x102 instead. It seems to work only once based on what I've seen :) If you try it after it's powered it never works. Could be I'm doing something wrong of course.. > You can disable the debounce clock after resetting the module if you > don't need it, though I doubt there's any significant power savings > there. (More likely it exists as a separate bit to allow it to stay > enabled even if the module isn't, for wakeup on debounced inputs.) Hmm I tried setting HWMOD_CONTROL_OPT_CLKS_IN_RESET flag like we have for many SoCs to enable also sysclk18_ck but no luck. I can recheck that. Regards, Tony