From mboxrd@z Thu Jan  1 00:00:00 1970
From: Marek Vasut <marex@denx.de>
Date: Fri, 11 Dec 2015 18:36:57 +0100
Subject: [U-Boot] [PATCH 3/6] arm: socfpga: de0-nano-soc: Enabling mtd
	partitioning layout
In-Reply-To: <566AEF17.5030305@kernel.org>
References: <1449825353-2568-1-git-send-email-clsee@altera.com>
 <201512111521.58098.marex@denx.de> <566AEF17.5030305@kernel.org>
Message-ID: <201512111836.57608.marex@denx.de>
List-Id: <u-boot.lists.denx.de>
MIME-Version: 1.0
Content-Type: text/plain; charset="us-ascii"
Content-Transfer-Encoding: 7bit
To: u-boot@lists.denx.de

On Friday, December 11, 2015 at 04:43:19 PM, Dinh Nguyen wrote:
> On 12/11/2015 08:21 AM, Marek Vasut wrote:
> > On Friday, December 11, 2015 at 10:15:50 AM, Chin Liang See wrote:
> >> Enabling mtd partitioning layout which indicate partition
> >> for various boot partition
> >> 
> >> Signed-off-by: Chin Liang See <clsee@altera.com>
> >> Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
> >> Cc: Dinh Nguyen <dinh.linux@gmail.com>
> >> Cc: Pavel Machek <pavel@denx.de>
> >> Cc: Marek Vasut <marex@denx.de>
> >> Cc: Stefan Roese <sr@denx.de>
> >> ---
> >> 
> >>  include/configs/socfpga_de0_nano_soc.h | 12 ++++++++++++
> >>  1 file changed, 12 insertions(+)
> >> 
> >> diff --git a/include/configs/socfpga_de0_nano_soc.h
> >> b/include/configs/socfpga_de0_nano_soc.h index 16e146c..c42175d 100644
> >> --- a/include/configs/socfpga_de0_nano_soc.h
> >> +++ b/include/configs/socfpga_de0_nano_soc.h
> >> @@ -86,4 +86,16 @@
> >> 
> >>  /* The rest of the configuration is shared */
> >>  #include <configs/socfpga_common.h>
> >> 
> >> +/* mtd partitioning for serial NOR flash */
> >> +#if defined(CONFIG_CMD_UBI) || defined(CONFIG_CMD_SF)
> >> +#define MTDPARTS_DEFAULT	"mtdparts=ff705000.spi:"\
> >> +				"256k(spl),"		\
> >> +				"64k(env),"		\
> >> +				"64k(dtb),"		\
> >> +				"256k(boot),"		\
> >> +				"16m(kernel),"		\
> >> +				"16m(rootfs),"		\
> >> +				"-(UBI)\0"
> >> +#endif
> > 
> > Does Atlas have a dedicated QSPI NOR ?
> 
> No, it does not.

Do you now understand why I have every single mainline SoCFPGA board in my
collection and why I am eagerly waiting for my first Arria 10 project ? :)

Best regards,
Marek Vasut