From: Herbert Xu <herbert@gondor.apana.org.au>
To: Haren Myneni <haren@linux.vnet.ibm.com>
Cc: segher@kernel.crashing.org, ddstreet@ieee.org,
davem@davemloft.net, pair@us.ibm.com, mpe@ellerman.id.au,
linux-crypto@vger.kernel.org, linuxppc-dev@lists.ozlabs.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH] crypto/nx842: Mask XERS0 bit in return value
Date: Thu, 17 Dec 2015 16:45:55 +0800 [thread overview]
Message-ID: <20151217084555.GA9239@gondor.apana.org.au> (raw)
In-Reply-To: <1450006242.19568.11.camel@hbabu-laptop>
On Sun, Dec 13, 2015 at 03:30:41AM -0800, Haren Myneni wrote:
>
> NX842 coprocessor sets 3rd bit in CR register with XER[S0] which is
> nothing to do with NX request. Since this bit can be set with other
> valuable return status, mast this bit.
>
> One of other bits (INITIATED, BUSY or REJECTED) will be returned for
> any given NX request.
>
> Signed-off-by: Haren Myneni <haren@us.ibm.com>
Patch applied. Thanks.
--
Email: Herbert Xu <herbert@gondor.apana.org.au>
Home Page: http://gondor.apana.org.au/~herbert/
PGP Key: http://gondor.apana.org.au/~herbert/pubkey.txt
prev parent reply other threads:[~2015-12-17 8:46 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-12-13 11:30 [PATCH] crypto/nx842: Mask XERS0 bit in return value Haren Myneni
2015-12-17 8:45 ` Herbert Xu [this message]
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