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* [PATCH] drm/dp/mst: constify drm_dp_mst_topology_cbs structures
@ 2015-12-30 21:20 ` Julia Lawall
  0 siblings, 0 replies; 90+ messages in thread
From: Julia Lawall @ 2015-12-30 21:20 UTC (permalink / raw)
  Cc: kernel-janitors, Alex Deucher, David Airlie, dri-devel,
	linux-kernel, Daniel Vetter, Jani Nikula, intel-gfx

The drm_dp_mst_topology_cbs structures are never modified, so declare them
as const.

Done with the help of Coccinelle.

Signed-off-by: Julia Lawall <Julia.Lawall@lip6.fr>

---
 drivers/gpu/drm/i915/intel_dp_mst.c    |    2 +-
 drivers/gpu/drm/radeon/radeon_dp_mst.c |    2 +-
 include/drm/drm_dp_mst_helper.h        |    2 +-
 3 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/include/drm/drm_dp_mst_helper.h b/include/drm/drm_dp_mst_helper.h
index 74b5888..b37b859 100644
--- a/include/drm/drm_dp_mst_helper.h
+++ b/include/drm/drm_dp_mst_helper.h
@@ -421,7 +421,7 @@ struct drm_dp_payload {
 struct drm_dp_mst_topology_mgr {
 
 	struct device *dev;
-	struct drm_dp_mst_topology_cbs *cbs;
+	const struct drm_dp_mst_topology_cbs *cbs;
 	int max_dpcd_transaction_bytes;
 	struct drm_dp_aux *aux; /* auxch for this topology mgr to use */
 	int max_payloads;
diff --git a/drivers/gpu/drm/radeon/radeon_dp_mst.c b/drivers/gpu/drm/radeon/radeon_dp_mst.c
index 94323f5..8a02225 100644
--- a/drivers/gpu/drm/radeon/radeon_dp_mst.c
+++ b/drivers/gpu/drm/radeon/radeon_dp_mst.c
@@ -329,7 +329,7 @@ static void radeon_dp_mst_hotplug(struct drm_dp_mst_topology_mgr *mgr)
 	drm_kms_helper_hotplug_event(dev);
 }
 
-struct drm_dp_mst_topology_cbs mst_cbs = {
+const struct drm_dp_mst_topology_cbs mst_cbs = {
 	.add_connector = radeon_dp_add_mst_connector,
 	.register_connector = radeon_dp_register_mst_connector,
 	.destroy_connector = radeon_dp_destroy_mst_connector,
diff --git a/drivers/gpu/drm/i915/intel_dp_mst.c b/drivers/gpu/drm/i915/intel_dp_mst.c
index e2f515d..fa0dabf 100644
--- a/drivers/gpu/drm/i915/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/intel_dp_mst.c
@@ -534,7 +534,7 @@ static void intel_dp_mst_hotplug(struct drm_dp_mst_topology_mgr *mgr)
 	drm_kms_helper_hotplug_event(dev);
 }
 
-static struct drm_dp_mst_topology_cbs mst_cbs = {
+static const struct drm_dp_mst_topology_cbs mst_cbs = {
 	.add_connector = intel_dp_add_mst_connector,
 	.register_connector = intel_dp_register_mst_connector,
 	.destroy_connector = intel_dp_destroy_mst_connector,


^ permalink raw reply related	[flat|nested] 90+ messages in thread
* [PATCH] drm/i915: Don't do pre plane update on disabled crtcs
@ 2016-01-14 16:32 Mika Kuoppala
  2016-01-14 17:20 ` ✗ warning: Fi.CI.BAT Patchwork
  0 siblings, 1 reply; 90+ messages in thread
From: Mika Kuoppala @ 2016-01-14 16:32 UTC (permalink / raw)
  To: intel-gfx

CI/Bat got following (shortened) trace on byt and also
on bsw:

------------[ cut here ]-----------
Unclaimed register detected before reading register 0x186500
Call Trace:
 __unclaimed_reg_debug+0x68/0x80 [i915]
vlv_read32+0x2de/0x370 [i915]
intel_set_memory_cxsr+0x87/0x1a0 [i915]
intel_pre_plane_update+0xb3/0xf0 [i915]
intel_atomic_commit+0x3b5/0x17c0 [i915]
...
---[ end trace 6387a0ad001bb39f ]---

Fix this by limiting pre plane update only to active crtcs.

References: https://bugs.freedesktop.org/show_bug.cgi?id=93698
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
---
 drivers/gpu/drm/i915/intel_display.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index aa24f79d85bf..a134a698d97d 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -13580,9 +13580,8 @@ static int intel_atomic_commit(struct drm_device *dev,
 		if (!needs_modeset(crtc->state))
 			continue;
 
-		intel_pre_plane_update(intel_crtc);
-
 		if (crtc_state->active) {
+			intel_pre_plane_update(intel_crtc);
 			intel_crtc_disable_planes(crtc, crtc_state->plane_mask);
 			dev_priv->display.crtc_disable(crtc);
 			intel_crtc->active = false;
-- 
2.5.0

_______________________________________________
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Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 90+ messages in thread
* [PATCH 0/7] Misc WM fixes and Arbitrated Display Bandwidth WA for SKL
@ 2016-01-14 12:02 Shobhit Kumar
  2016-01-14 13:20 ` ✗ warning: Fi.CI.BAT Patchwork
  0 siblings, 1 reply; 90+ messages in thread
From: Shobhit Kumar @ 2016-01-14 12:02 UTC (permalink / raw)
  To: intel-gfx

Hi,
This series add a set of updates to the WM calculation and also enables
arbitrated display bandwidth based WA. Some of these patches do overlap
with Matts work but we wanted to send them out as we have them in our
internal testing for early review. Most likley some of them can be
superceded by patches from Matt, or can be re-used if deemed necessary.

Especially "drm/i915/skl+: Use fb size for relative data rate calculation"
this already addresses some of Ville's comment on similar patch from Matt.

Regards
Shobhit

Kumar, Mahesh (6):
  drm/i915/skl+: Use proper bytes_per_pixel during WM calculation
  drm/i915/skl+: Use fb size for relative data rate calculation
  drm/i915/skl+: calculate ddb minimum allocation
  drm/i915/skl+: calculate plane pixel rate.
  drm/i915/skl+: Use scaling amount for plane data rate calculation
  drm/i915/skl: WA for watermark calculation based on Arbitrated Display
    BW

Shobhit Kumar (1):
  drm/i915: Add support to parse DMI table and get platform memory info

 drivers/gpu/drm/i915/i915_dma.c  |  19 +++
 drivers/gpu/drm/i915/i915_drv.h  |  15 ++
 drivers/gpu/drm/i915/intel_drv.h |   2 +
 drivers/gpu/drm/i915/intel_pm.c  | 294 +++++++++++++++++++++++++++++++++++++--
 4 files changed, 316 insertions(+), 14 deletions(-)

-- 
2.4.3

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Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 90+ messages in thread
* [PATCH 1/2] drm/i915/dsi: lose the loose 666 format name in favor of packed
@ 2016-01-14 10:28 Jani Nikula
  2016-01-14 11:49 ` ✗ warning: Fi.CI.BAT Patchwork
  0 siblings, 1 reply; 90+ messages in thread
From: Jani Nikula @ 2016-01-14 10:28 UTC (permalink / raw)
  To: intel-gfx; +Cc: jani.nikula

The enum mipi_dsi_pixel_format defines MIPI_DSI_FMT_RGB666 for the
"loose" 24 bpp format and MIPI_DSI_FMT_RGB666_PACKED for the 18 bpp
format. We have this the other way round, defining a loose version for
24 bpp.

Follow suit with what's in enum mipi_dsi_pixel_format to avoid future
confusion. Rename

VID_MODE_FORMAT_RGB666 -> VID_MODE_FORMAT_RGB666_PACKED
VID_MODE_FORMAT_RGB666_LOOSE -> VID_MODE_FORMAT_RGB666

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h            | 4 ++--
 drivers/gpu/drm/i915/intel_dsi_panel_vbt.c | 2 +-
 drivers/gpu/drm/i915/intel_dsi_pll.c       | 4 ++--
 3 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 0a988895165f..379c61677334 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7849,8 +7849,8 @@ enum skl_disp_power_wells {
 #define  VID_MODE_FORMAT_MASK				(0xf << 7)
 #define  VID_MODE_NOT_SUPPORTED				(0 << 7)
 #define  VID_MODE_FORMAT_RGB565				(1 << 7)
-#define  VID_MODE_FORMAT_RGB666				(2 << 7)
-#define  VID_MODE_FORMAT_RGB666_LOOSE			(3 << 7)
+#define  VID_MODE_FORMAT_RGB666_PACKED			(2 << 7)
+#define  VID_MODE_FORMAT_RGB666				(3 << 7)
 #define  VID_MODE_FORMAT_RGB888				(4 << 7)
 #define  CMD_MODE_CHANNEL_NUMBER_SHIFT			5
 #define  CMD_MODE_CHANNEL_NUMBER_MASK			(3 << 5)
diff --git a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
index 1d43e6f37fc1..3f4b9712bffd 100644
--- a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
+++ b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
@@ -420,7 +420,7 @@ struct drm_panel *vbt_panel_init(struct intel_dsi *intel_dsi, u16 panel_id)
 	intel_dsi->dual_link = mipi_config->dual_link;
 	intel_dsi->pixel_overlap = mipi_config->pixel_overlap;
 
-	if (intel_dsi->pixel_format == VID_MODE_FORMAT_RGB666)
+	if (intel_dsi->pixel_format == VID_MODE_FORMAT_RGB666_PACKED)
 		bits_per_pixel = 18;
 	else if (intel_dsi->pixel_format == VID_MODE_FORMAT_RGB565)
 		bits_per_pixel = 16;
diff --git a/drivers/gpu/drm/i915/intel_dsi_pll.c b/drivers/gpu/drm/i915/intel_dsi_pll.c
index bb5e95a1a453..f70df2b42b23 100644
--- a/drivers/gpu/drm/i915/intel_dsi_pll.c
+++ b/drivers/gpu/drm/i915/intel_dsi_pll.c
@@ -37,10 +37,10 @@ static int dsi_pixel_format_bpp(int pixel_format)
 	switch (pixel_format) {
 	default:
 	case VID_MODE_FORMAT_RGB888:
-	case VID_MODE_FORMAT_RGB666_LOOSE:
+	case VID_MODE_FORMAT_RGB666:
 		bpp = 24;
 		break;
-	case VID_MODE_FORMAT_RGB666:
+	case VID_MODE_FORMAT_RGB666_PACKED:
 		bpp = 18;
 		break;
 	case VID_MODE_FORMAT_RGB565:
-- 
2.1.4

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Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 90+ messages in thread
* [PATCH] drm/i915: Sink CRC: tune down error message at stop to debug_kms.
@ 2016-01-13 22:05 Rodrigo Vivi
  2016-01-14 10:20 ` ✗ warning: Fi.CI.BAT Patchwork
  0 siblings, 1 reply; 90+ messages in thread
From: Rodrigo Vivi @ 2016-01-13 22:05 UTC (permalink / raw)
  To: intel-gfx; +Cc: Daniel Vetter, Rodrigo Vivi

When we stop the sink CRC calculation we wait a while until the counter
is reset to zero and return -ETIMEDOUT. However the sink crc was
calculated already by this point so we just ignore this return at
the main function.

So, let's also ignore the message and put it as a debug message instead
of an error one. The message might still be useful when debuging
test failures so we could be able to know something was not going so
well with sink crc stop.

Reference: https://bugs.freedesktop.org/show_bug.cgi?id=93694
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/i915/intel_dp.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index c8f58ab..22f6887 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -4009,7 +4009,7 @@ static int intel_dp_sink_crc_stop(struct intel_dp *intel_dp)
 	} while (--attempts && count);
 
 	if (attempts == 0) {
-		DRM_ERROR("TIMEOUT: Sink CRC counter is not zeroed\n");
+		DRM_DEBUG_KMS("TIMEOUT: Sink CRC counter is not zeroed\n");
 		ret = -ETIMEDOUT;
 	}
 
-- 
2.4.3

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Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 90+ messages in thread
* [PATCH] drm/crtc-helper: Add caveat to disable_unused_functions doc
@ 2016-01-13 14:31 Daniel Vetter
  2016-01-13 14:57 ` ✗ warning: Fi.CI.BAT Patchwork
  0 siblings, 1 reply; 90+ messages in thread
From: Daniel Vetter @ 2016-01-13 14:31 UTC (permalink / raw)
  To: Intel Graphics Development
  Cc: Daniel Vetter, Maxime Ripard, Laurent Pinchart, DRI Development,
	Daniel Vetter

This shouldn't be used by atomic drivers any more, it confuses the
state tracking.

Cc: Maxime Ripard <maxime.ripard@free-electrons.com>
Cc: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Daniel Vetter <daniel.vetter@intel.com>
---
 drivers/gpu/drm/drm_crtc_helper.c | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/drivers/gpu/drm/drm_crtc_helper.c b/drivers/gpu/drm/drm_crtc_helper.c
index a02a7f9a6a9d..a278fbbe23e0 100644
--- a/drivers/gpu/drm/drm_crtc_helper.c
+++ b/drivers/gpu/drm/drm_crtc_helper.c
@@ -220,6 +220,15 @@ static void __drm_helper_disable_unused_functions(struct drm_device *dev)
  * disconnected connectors. Then it will disable all unused encoders and CRTCs
  * either by calling their disable callback if available or by calling their
  * dpms callback with DRM_MODE_DPMS_OFF.
+ *
+ * NOTE:
+ *
+ * This function is part of the legacy modeset helper library and will cause
+ * major confusion with atomic drivers. This is because atomic helpers guarantee
+ * to never call ->disable() hooks on a disabled function, or ->enable() hooks
+ * on an enabled functions. drm_helper_disable_unused_functions() on the other
+ * hand throws such guarantees into the wind and calls disable hooks
+ * unconditionally on unused functions.
  */
 void drm_helper_disable_unused_functions(struct drm_device *dev)
 {
-- 
2.7.0.rc3

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http://lists.freedesktop.org/mailman/listinfo/dri-devel

^ permalink raw reply related	[flat|nested] 90+ messages in thread
* [PATCH] drm/i915: Init power domains early in driver load
@ 2016-01-13 10:55 Daniel Vetter
  2016-01-13 12:13 ` ✗ warning: Fi.CI.BAT Patchwork
  0 siblings, 1 reply; 90+ messages in thread
From: Daniel Vetter @ 2016-01-13 10:55 UTC (permalink / raw)
  To: Intel Graphics Development
  Cc: Daniel Vetter, Ville Syrjälä,
	Patrik Jakobsson, Imre Deak, Jani Nikula, Meelis Roos,
	Chris Wilson, stable, Daniel Vetter

Since

commit ac9b8236551d1177fd07b56aef9b565d1864420d
Author: Ville Syrjälä <ville.syrjala@linux.intel.com>
Date:   Fri Nov 27 18:55:26 2015 +0200

    drm/i915: Introduce a gmbus power domain

gmbus also needs the power domain infrastructure right from the start,
since as soon as we register the i2c controllers someone can use them.

v2: Adjust cleanup paths too (Chris).

v3: Rebase onto -nightly (totally bogus tree I had lying around) and
also move dpio init head (Ville).

v4: Ville instead suggested to move gmbus setup later in the sequence,
since it's only needed by the modeset code.

v5: Move even close to the actual user, right next to the comment that
states where we really need gmbus (and interrupts!).

Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Patrik Jakobsson <patrik.jakobsson@linux.intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Meelis Roos <mroos@linux.ee>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Fixes: ac9b8236551d ("drm/i915: Introduce a gmbus power domain")
Cc: stable@vger.kernel.org
References: http://www.spinics.net/lists/intel-gfx/msg83075.html
Signed-off-by: Daniel Vetter <daniel.vetter@intel.com>
---

Resending since our CI seems to have missed it.
-Daniel

---
 drivers/gpu/drm/i915/i915_dma.c      | 6 +++---
 drivers/gpu/drm/i915/intel_display.c | 2 ++
 2 files changed, 5 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index 44a896ce32e6..a0f5659032fc 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -406,6 +406,8 @@ static int i915_load_modeset_init(struct drm_device *dev)
 	if (ret)
 		goto cleanup_gem_stolen;
 
+	intel_setup_gmbus(dev);
+
 	/* Important: The output setup functions called by modeset_init need
 	 * working irqs for e.g. gmbus and dp aux transfers. */
 	intel_modeset_init(dev);
@@ -455,6 +457,7 @@ cleanup_gem:
 cleanup_irq:
 	intel_guc_ucode_fini(dev);
 	drm_irq_uninstall(dev);
+	intel_teardown_gmbus(dev);
 cleanup_gem_stolen:
 	i915_gem_cleanup_stolen(dev);
 cleanup_vga_switcheroo:
@@ -1029,7 +1032,6 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
 
 	/* Try to make sure MCHBAR is enabled before poking at it */
 	intel_setup_mchbar(dev);
-	intel_setup_gmbus(dev);
 	intel_opregion_setup(dev);
 
 	i915_gem_load(dev);
@@ -1102,7 +1104,6 @@ out_gem_unload:
 	if (dev->pdev->msi_enabled)
 		pci_disable_msi(dev->pdev);
 
-	intel_teardown_gmbus(dev);
 	intel_teardown_mchbar(dev);
 	pm_qos_remove_request(&dev_priv->pm_qos);
 	destroy_workqueue(dev_priv->gpu_error.hangcheck_wq);
@@ -1204,7 +1205,6 @@ int i915_driver_unload(struct drm_device *dev)
 
 	intel_csr_ucode_fini(dev_priv);
 
-	intel_teardown_gmbus(dev);
 	intel_teardown_mchbar(dev);
 
 	destroy_workqueue(dev_priv->hotplug.dp_wq);
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 20a73d9e19d7..86fce41281fb 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -16125,6 +16125,8 @@ void intel_modeset_cleanup(struct drm_device *dev)
 	mutex_lock(&dev->struct_mutex);
 	intel_cleanup_gt_powersave(dev);
 	mutex_unlock(&dev->struct_mutex);
+
+	intel_teardown_gmbus(dev);
 }
 
 /*
-- 
2.7.0.rc3


^ permalink raw reply related	[flat|nested] 90+ messages in thread
* [PATCH v4] drm/i915: edp resume/On time optimization.
@ 2016-01-13  1:57 abhay.kumar
  2016-01-13 10:20 ` ✗ warning: Fi.CI.BAT Patchwork
  0 siblings, 1 reply; 90+ messages in thread
From: abhay.kumar @ 2016-01-13  1:57 UTC (permalink / raw)
  To: Intel-gfx, ville.syrjala

From: Abhay Kumar <abhay.kumar@intel.com>

Make resume/on codepath not to wait for panel_power_cycle_delay(t11_t12)
if this time is already spent in suspend/poweron time.

v2: Use CLOCK_BOOTTIME and remove jiffies for panel power cycle
    delay calculation(Ville).

v3: Addressed below comments
    1. Tracking time from where last powercycle is initiated.
    2. Used ktime_get_bootime() wrapper for boottime clock.
    3. Used ktime_ms_delta() to get time difference.

v4: Updated v3 change log in detail.

Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Abhay Kumar <abhay.kumar@intel.com>
---
 drivers/gpu/drm/i915/intel_dp.c  | 19 ++++++++++++++-----
 drivers/gpu/drm/i915/intel_drv.h |  2 +-
 2 files changed, 15 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 796e3d3..0042693 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1812,12 +1812,21 @@ static void wait_panel_off(struct intel_dp *intel_dp)
 
 static void wait_panel_power_cycle(struct intel_dp *intel_dp)
 {
+	static ktime_t panel_power_on_time;
+	s64 panel_power_off_duration;
+
 	DRM_DEBUG_KMS("Wait for panel power cycle\n");
 
+	/* take the difference of currrent time and panel power off time
+	 * and then make panel wait for t11_t12 if needed. */
+	panel_power_on_time = ktime_get_boottime();
+	panel_power_off_duration = ktime_ms_delta(panel_power_on_time, intel_dp->panel_power_off_time);
+
 	/* When we disable the VDD override bit last we have to do the manual
 	 * wait. */
-	wait_remaining_ms_from_jiffies(intel_dp->last_power_cycle,
-				       intel_dp->panel_power_cycle_delay);
+	if (panel_power_off_duration < (s64)intel_dp->panel_power_cycle_delay)
+		wait_remaining_ms_from_jiffies(jiffies,
+				       intel_dp->panel_power_cycle_delay - panel_power_off_duration);
 
 	wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
 }
@@ -1969,7 +1978,7 @@ static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
 	I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
 
 	if ((pp & POWER_TARGET_ON) == 0)
-		intel_dp->last_power_cycle = jiffies;
+		intel_dp->panel_power_off_time = ktime_get_boottime();
 
 	power_domain = intel_display_port_aux_power_domain(intel_encoder);
 	intel_display_power_put(dev_priv, power_domain);
@@ -2118,7 +2127,7 @@ static void edp_panel_off(struct intel_dp *intel_dp)
 	I915_WRITE(pp_ctrl_reg, pp);
 	POSTING_READ(pp_ctrl_reg);
 
-	intel_dp->last_power_cycle = jiffies;
+	intel_dp->panel_power_off_time = ktime_get_boottime();
 	wait_panel_off(intel_dp);
 
 	/* We got a reference when we enabled the VDD. */
@@ -5122,7 +5131,7 @@ intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connect
 
 static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
 {
-	intel_dp->last_power_cycle = jiffies;
+	intel_dp->panel_power_off_time = ktime_get_boottime();
 	intel_dp->last_power_on = jiffies;
 	intel_dp->last_backlight_off = jiffies;
 }
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index bdfe403..06b37b8 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -793,9 +793,9 @@ struct intel_dp {
 	int backlight_off_delay;
 	struct delayed_work panel_vdd_work;
 	bool want_panel_vdd;
-	unsigned long last_power_cycle;
 	unsigned long last_power_on;
 	unsigned long last_backlight_off;
+	ktime_t panel_power_off_time;
 
 	struct notifier_block edp_notifier;
 
-- 
1.9.1

_______________________________________________
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http://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 90+ messages in thread
* [PATCH 0/7] drm/i915: Reviewed fb offsets[] prep patches
@ 2016-01-12 19:08 ville.syrjala
  2016-01-13  8:24 ` ✗ warning: Fi.CI.BAT Patchwork
  0 siblings, 1 reply; 90+ messages in thread
From: ville.syrjala @ 2016-01-12 19:08 UTC (permalink / raw)
  To: intel-gfx

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Here's a repost of some already reviewed patches from my larger fb 
offsets[] series [1] from last year, for the sake of the CI system.

[1] http://lists.freedesktop.org/archives/intel-gfx/2015-October/078050.html

Ville Syrjälä (7):
  drm/i915: Pass modifier instead of tiling_mode to
    gen4_compute_page_offset()
  drm/i915: Factor out intel_tile_width()
  drm/i915: Redo intel_tile_height() as intel_tile_size() /
    intel_tile_width()
  drm/i915: change intel_fill_fb_ggtt_view() to use the real tile size
  drm/i915: Use intel_tile_{size,width,height}() in
    intel_gen4_compute_page_offset()
  drm/i915: s/intel_gen4_compute_page_offset/intel_compute_tile_offset/
  drm/i915: Refactor intel_surf_alignment()

 drivers/gpu/drm/i915/intel_display.c | 248 +++++++++++++++++------------------
 drivers/gpu/drm/i915/intel_drv.h     |  19 ++-
 drivers/gpu/drm/i915/intel_sprite.c  |  32 ++---
 3 files changed, 145 insertions(+), 154 deletions(-)

-- 
2.4.10

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http://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 90+ messages in thread
* [PATCH 1/2] drm/i915/gen8: Tidy display interrupt processing
@ 2016-01-12 16:04 Tvrtko Ursulin
  2016-01-13  7:49 ` ✗ warning: Fi.CI.BAT Patchwork
  0 siblings, 1 reply; 90+ messages in thread
From: Tvrtko Ursulin @ 2016-01-12 16:04 UTC (permalink / raw)
  To: Intel-gfx

From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

One bugfix and a few tidy-ups:

 * Pipe fault logging was broken on Gen9+.
 * Removed some unnecessary local variables.
 * Removed unnecessary initializers.
 * Decreased pipe iir block indentation level.
 * Grouped variable initialization close to use sites.

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
 drivers/gpu/drm/i915/i915_irq.c | 131 ++++++++++++++++++++--------------------
 1 file changed, 67 insertions(+), 64 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index f04d799153ca..7972ceee6096 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -2268,11 +2268,9 @@ static irqreturn_t gen8_irq_handler(int irq, void *arg)
 {
 	struct drm_device *dev = arg;
 	struct drm_i915_private *dev_priv = dev->dev_private;
-	u32 master_ctl;
+	u32 master_ctl, iir;
 	irqreturn_t ret = IRQ_NONE;
-	uint32_t tmp = 0;
 	enum pipe pipe;
-	u32 aux_mask = GEN8_AUX_CHANNEL_A;
 
 	if (!intel_irqs_enabled(dev_priv))
 		return IRQ_NONE;
@@ -2280,10 +2278,6 @@ static irqreturn_t gen8_irq_handler(int irq, void *arg)
 	/* IRQs are synced during runtime_suspend, we don't require a wakeref */
 	disable_rpm_wakeref_asserts(dev_priv);
 
-	if (INTEL_INFO(dev_priv)->gen >= 9)
-		aux_mask |=  GEN9_AUX_CHANNEL_B | GEN9_AUX_CHANNEL_C |
-			GEN9_AUX_CHANNEL_D;
-
 	master_ctl = I915_READ_FW(GEN8_MASTER_IRQ);
 	master_ctl &= ~GEN8_MASTER_IRQ_CONTROL;
 	if (!master_ctl)
@@ -2296,11 +2290,11 @@ static irqreturn_t gen8_irq_handler(int irq, void *arg)
 	ret = gen8_gt_irq_handler(dev_priv, master_ctl);
 
 	if (master_ctl & GEN8_DE_MISC_IRQ) {
-		tmp = I915_READ(GEN8_DE_MISC_IIR);
-		if (tmp) {
-			I915_WRITE(GEN8_DE_MISC_IIR, tmp);
+		iir = I915_READ(GEN8_DE_MISC_IIR);
+		if (iir) {
+			I915_WRITE(GEN8_DE_MISC_IIR, iir);
 			ret = IRQ_HANDLED;
-			if (tmp & GEN8_DE_MISC_GSE)
+			if (iir & GEN8_DE_MISC_GSE)
 				intel_opregion_asle_intr(dev);
 			else
 				DRM_ERROR("Unexpected DE Misc interrupt\n");
@@ -2310,33 +2304,40 @@ static irqreturn_t gen8_irq_handler(int irq, void *arg)
 	}
 
 	if (master_ctl & GEN8_DE_PORT_IRQ) {
-		tmp = I915_READ(GEN8_DE_PORT_IIR);
-		if (tmp) {
+		iir = I915_READ(GEN8_DE_PORT_IIR);
+		if (iir) {
+			u32 tmp_mask;
 			bool found = false;
-			u32 hotplug_trigger = 0;
-
-			if (IS_BROXTON(dev_priv))
-				hotplug_trigger = tmp & BXT_DE_PORT_HOTPLUG_MASK;
-			else if (IS_BROADWELL(dev_priv))
-				hotplug_trigger = tmp & GEN8_PORT_DP_A_HOTPLUG;
 
-			I915_WRITE(GEN8_DE_PORT_IIR, tmp);
+			I915_WRITE(GEN8_DE_PORT_IIR, iir);
 			ret = IRQ_HANDLED;
 
-			if (tmp & aux_mask) {
+			tmp_mask = GEN8_AUX_CHANNEL_A;
+			if (INTEL_INFO(dev_priv)->gen >= 9)
+				tmp_mask |= GEN9_AUX_CHANNEL_B |
+					    GEN9_AUX_CHANNEL_C |
+					    GEN9_AUX_CHANNEL_D;
+
+			if (iir & tmp_mask) {
 				dp_aux_irq_handler(dev);
 				found = true;
 			}
 
-			if (hotplug_trigger) {
-				if (IS_BROXTON(dev))
-					bxt_hpd_irq_handler(dev, hotplug_trigger, hpd_bxt);
-				else
-					ilk_hpd_irq_handler(dev, hotplug_trigger, hpd_bdw);
-				found = true;
+			if (IS_BROXTON(dev_priv)) {
+				tmp_mask = iir & BXT_DE_PORT_HOTPLUG_MASK;
+				if (tmp_mask) {
+					bxt_hpd_irq_handler(dev, tmp_mask, hpd_bxt);
+					found = true;
+				}
+			} else if (IS_BROADWELL(dev_priv)) {
+				tmp_mask = iir & GEN8_PORT_DP_A_HOTPLUG;
+				if (tmp_mask) {
+					ilk_hpd_irq_handler(dev, tmp_mask, hpd_bdw);
+					found = true;
+				}
 			}
 
-			if (IS_BROXTON(dev) && (tmp & BXT_DE_PORT_GMBUS)) {
+			if (IS_BROXTON(dev) && (iir & BXT_DE_PORT_GMBUS)) {
 				gmbus_irq_handler(dev);
 				found = true;
 			}
@@ -2349,49 +2350,51 @@ static irqreturn_t gen8_irq_handler(int irq, void *arg)
 	}
 
 	for_each_pipe(dev_priv, pipe) {
-		uint32_t pipe_iir, flip_done = 0, fault_errors = 0;
+		u32 flip_done, fault_errors;
 
 		if (!(master_ctl & GEN8_DE_PIPE_IRQ(pipe)))
 			continue;
 
-		pipe_iir = I915_READ(GEN8_DE_PIPE_IIR(pipe));
-		if (pipe_iir) {
-			ret = IRQ_HANDLED;
-			I915_WRITE(GEN8_DE_PIPE_IIR(pipe), pipe_iir);
+		iir = I915_READ(GEN8_DE_PIPE_IIR(pipe));
+		if (!iir) {
+			DRM_ERROR("The master control interrupt lied (DE PIPE)!\n");
+			continue;
+		}
 
-			if (pipe_iir & GEN8_PIPE_VBLANK &&
-			    intel_pipe_handle_vblank(dev, pipe))
-				intel_check_page_flip(dev, pipe);
+		ret = IRQ_HANDLED;
+		I915_WRITE(GEN8_DE_PIPE_IIR(pipe), iir);
 
-			if (INTEL_INFO(dev_priv)->gen >= 9)
-				flip_done = pipe_iir & GEN9_PIPE_PLANE1_FLIP_DONE;
-			else
-				flip_done = pipe_iir & GEN8_PIPE_PRIMARY_FLIP_DONE;
+		if (iir & GEN8_PIPE_VBLANK &&
+		    intel_pipe_handle_vblank(dev, pipe))
+			intel_check_page_flip(dev, pipe);
 
-			if (flip_done) {
-				intel_prepare_page_flip(dev, pipe);
-				intel_finish_page_flip_plane(dev, pipe);
-			}
+		flip_done = iir;
+		if (INTEL_INFO(dev_priv)->gen >= 9)
+			flip_done &= GEN9_PIPE_PLANE1_FLIP_DONE;
+		else
+			flip_done &= GEN8_PIPE_PRIMARY_FLIP_DONE;
 
-			if (pipe_iir & GEN8_PIPE_CDCLK_CRC_DONE)
-				hsw_pipe_crc_irq_handler(dev, pipe);
+		if (flip_done) {
+			intel_prepare_page_flip(dev, pipe);
+			intel_finish_page_flip_plane(dev, pipe);
+		}
 
-			if (pipe_iir & GEN8_PIPE_FIFO_UNDERRUN)
-				intel_cpu_fifo_underrun_irq_handler(dev_priv,
-								    pipe);
+		if (iir & GEN8_PIPE_CDCLK_CRC_DONE)
+			hsw_pipe_crc_irq_handler(dev, pipe);
 
+		if (iir & GEN8_PIPE_FIFO_UNDERRUN)
+			intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
 
-			if (INTEL_INFO(dev_priv)->gen >= 9)
-				fault_errors = pipe_iir & GEN9_DE_PIPE_IRQ_FAULT_ERRORS;
-			else
-				fault_errors = pipe_iir & GEN8_DE_PIPE_IRQ_FAULT_ERRORS;
+		fault_errors = iir;
+		if (INTEL_INFO(dev_priv)->gen >= 9)
+			fault_errors &= GEN9_DE_PIPE_IRQ_FAULT_ERRORS;
+		else
+			fault_errors &= GEN8_DE_PIPE_IRQ_FAULT_ERRORS;
 
-			if (fault_errors)
-				DRM_ERROR("Fault errors on pipe %c\n: 0x%08x",
-					  pipe_name(pipe),
-					  pipe_iir & GEN8_DE_PIPE_IRQ_FAULT_ERRORS);
-		} else
-			DRM_ERROR("The master control interrupt lied (DE PIPE)!\n");
+		if (fault_errors)
+			DRM_ERROR("Fault errors on pipe %c\n: 0x%08x",
+				  pipe_name(pipe),
+				  fault_errors);
 	}
 
 	if (HAS_PCH_SPLIT(dev) && !HAS_PCH_NOP(dev) &&
@@ -2401,15 +2404,15 @@ static irqreturn_t gen8_irq_handler(int irq, void *arg)
 		 * scheme also closed the SDE interrupt handling race we've seen
 		 * on older pch-split platforms. But this needs testing.
 		 */
-		u32 pch_iir = I915_READ(SDEIIR);
-		if (pch_iir) {
-			I915_WRITE(SDEIIR, pch_iir);
+		iir = I915_READ(SDEIIR);
+		if (iir) {
+			I915_WRITE(SDEIIR, iir);
 			ret = IRQ_HANDLED;
 
 			if (HAS_PCH_SPT(dev_priv))
-				spt_irq_handler(dev, pch_iir);
+				spt_irq_handler(dev, iir);
 			else
-				cpt_irq_handler(dev, pch_iir);
+				cpt_irq_handler(dev, iir);
 		} else {
 			/*
 			 * Like on previous PCH there seems to be something
-- 
1.9.1

_______________________________________________
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http://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 90+ messages in thread
* [PATCH 0/2] DPCD Backlight Control
@ 2016-01-12 15:59 Yetunde Adebisi
  2016-01-12 17:49 ` ✗ warning: Fi.CI.BAT Patchwork
  0 siblings, 1 reply; 90+ messages in thread
From: Yetunde Adebisi @ 2016-01-12 15:59 UTC (permalink / raw)
  To: intel-gfx; +Cc: Yetunde Adebisi

These patches add support for Backlight Control using DPCD registers on eDP
displays.

- Patch 1 adds macro for DPCD registers capability size to drm_dp_helper.h
A copy of this patch has also been sent to dri-devel list.

- Patch 2 Implements functionaly for DPCD Backlight Control 

Yetunde Adebisi (2):
  drm/dp: Add definition for Display Control DPCD Registers capability
    size
  drm/i915: Add Backlight Control using DPCD for eDP connectors (v5)

 drivers/gpu/drm/i915/Makefile                 |   1 +
 drivers/gpu/drm/i915/intel_dp.c               |  17 ++-
 drivers/gpu/drm/i915/intel_dp_aux_backlight.c | 169 ++++++++++++++++++++++++++
 drivers/gpu/drm/i915/intel_drv.h              |   6 +
 drivers/gpu/drm/i915/intel_panel.c            |   4 +
 include/drm/drm_dp_helper.h                   |   1 +
 6 files changed, 192 insertions(+), 6 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/intel_dp_aux_backlight.c

-- 
1.9.3

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http://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 90+ messages in thread
* [PATCH] drm/i915: edp resume/On time optimization.
@ 2016-01-11 22:55 abhay.kumar
  2016-01-12  9:49 ` ✗ warning: Fi.CI.BAT Patchwork
  0 siblings, 1 reply; 90+ messages in thread
From: abhay.kumar @ 2016-01-11 22:55 UTC (permalink / raw)
  To: Intel-gfx

From: Abhay Kumar <abhay.kumar@intel.com>

Make resume/on codepath not to wait for panel_power_cycle_delay(t11_t12)
if this time is already spent in suspend/poweron time.

v2: Use CLOCK_BOOTTIME and remove jiffies for panel power cycle
    delay calculation(Ville).

v3: Addressing Ville review comment.

Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Abhay Kumar <abhay.kumar@intel.com>
---
 drivers/gpu/drm/i915/intel_dp.c  | 19 ++++++++++++++-----
 drivers/gpu/drm/i915/intel_drv.h |  2 +-
 2 files changed, 15 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 796e3d3..d0885bc 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1812,12 +1812,21 @@ static void wait_panel_off(struct intel_dp *intel_dp)
 
 static void wait_panel_power_cycle(struct intel_dp *intel_dp)
 {
+	static ktime_t panel_power_on_time;
+	s64 panel_power_off_duration;
+
 	DRM_DEBUG_KMS("Wait for panel power cycle\n");
 
+	/* take the difference of currrent time and panel power off time
+	 * and then make panel wait for t11_t12 if needed. */
+	panel_power_on_time = ktime_get_boottime();
+	panel_power_off_duration = ktime_ms_delta(panel_power_on_time, intel_dp->panel_power_off_time);
+
 	/* When we disable the VDD override bit last we have to do the manual
 	 * wait. */
-	wait_remaining_ms_from_jiffies(intel_dp->last_power_cycle,
-				       intel_dp->panel_power_cycle_delay);
+	if (panel_power_off_duration < ((s64) intel_dp->panel_power_cycle_delay))
+		wait_remaining_ms_from_jiffies(jiffies,
+				       (intel_dp->panel_power_cycle_delay - panel_power_off_duration));
 
 	wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
 }
@@ -1969,7 +1978,7 @@ static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
 	I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
 
 	if ((pp & POWER_TARGET_ON) == 0)
-		intel_dp->last_power_cycle = jiffies;
+		intel_dp->panel_power_off_time = ktime_get_boottime();
 
 	power_domain = intel_display_port_aux_power_domain(intel_encoder);
 	intel_display_power_put(dev_priv, power_domain);
@@ -2118,7 +2127,7 @@ static void edp_panel_off(struct intel_dp *intel_dp)
 	I915_WRITE(pp_ctrl_reg, pp);
 	POSTING_READ(pp_ctrl_reg);
 
-	intel_dp->last_power_cycle = jiffies;
+	intel_dp->panel_power_off_time = ktime_get_boottime();
 	wait_panel_off(intel_dp);
 
 	/* We got a reference when we enabled the VDD. */
@@ -5122,7 +5131,7 @@ intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connect
 
 static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
 {
-	intel_dp->last_power_cycle = jiffies;
+	intel_dp->panel_power_off_time = ktime_get_boottime();
 	intel_dp->last_power_on = jiffies;
 	intel_dp->last_backlight_off = jiffies;
 }
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index bdfe403..06b37b8 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -793,9 +793,9 @@ struct intel_dp {
 	int backlight_off_delay;
 	struct delayed_work panel_vdd_work;
 	bool want_panel_vdd;
-	unsigned long last_power_cycle;
 	unsigned long last_power_on;
 	unsigned long last_backlight_off;
+	ktime_t panel_power_off_time;
 
 	struct notifier_block edp_notifier;
 
-- 
1.9.1

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http://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 90+ messages in thread
* [PATCH] drm/i915: reboot notifier delay for eDP panels
@ 2016-01-11 21:52 clinton.a.taylor
  2016-01-12  9:16 ` ✗ warning: Fi.CI.BAT Patchwork
  0 siblings, 1 reply; 90+ messages in thread
From: clinton.a.taylor @ 2016-01-11 21:52 UTC (permalink / raw)
  To: Intel-gfx

From: Clint Taylor <clinton.a.taylor@intel.com>

Add reboot notifier for all platforms. This guarantees T12 delay
compliance during reboot cycles when pre-os enables the panel within
500ms.

Signed-off-by: Clint Taylor <clinton.a.taylor@intel.com>
---
 drivers/gpu/drm/i915/intel_dp.c |   11 ++++++++---
 1 file changed, 8 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 796e3d3..dbbd27a 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -126,6 +126,7 @@ static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
 static void intel_dp_link_down(struct intel_dp *intel_dp);
 static bool edp_panel_vdd_on(struct intel_dp *intel_dp);
 static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
+static void edp_panel_off(struct intel_dp *intel_dp);
 static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp);
 static void vlv_steal_power_sequencer(struct drm_device *dev,
 				      enum pipe pipe);
@@ -596,6 +597,10 @@ static int edp_notify_handler(struct notifier_block *this, unsigned long code,
 		I915_WRITE(pp_ctrl_reg, PANEL_UNLOCK_REGS | PANEL_POWER_OFF);
 		msleep(intel_dp->panel_power_cycle_delay);
 	}
+	else
+	{
+		edp_panel_off(intel_dp);
+	}
 
 	pps_unlock(intel_dp);
 
@@ -5796,10 +5801,10 @@ static bool intel_edp_init_connector(struct intel_dp *intel_dp,
 	}
 	mutex_unlock(&dev->mode_config.mutex);
 
-	if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
-		intel_dp->edp_notifier.notifier_call = edp_notify_handler;
-		register_reboot_notifier(&intel_dp->edp_notifier);
+	intel_dp->edp_notifier.notifier_call = edp_notify_handler;
+	register_reboot_notifier(&intel_dp->edp_notifier);
 
+	if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
 		/*
 		 * Figure out the current pipe for the initial backlight setup.
 		 * If the current pipe isn't valid, try the PPS pipe, and if that
-- 
1.7.9.5

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^ permalink raw reply related	[flat|nested] 90+ messages in thread
* [PATCH] drm/i915: Handle error paths during watermark sanitization properly
@ 2016-01-11 16:16 Matt Roper
  2016-01-11 16:49 ` ✗ warning: Fi.CI.BAT Patchwork
                   ` (2 more replies)
  0 siblings, 3 replies; 90+ messages in thread
From: Matt Roper @ 2016-01-11 16:16 UTC (permalink / raw)
  To: intel-gfx

sanitize_watermarks() does not properly handle errors returned by
drm_atomic_helper_duplicate_state().  EDEADLK should trigger a modeset
backoff and retry; for other errors we need to drop locks before
returning.

Cc: Daniel Vetter <daniel@ffwll.ch>
Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
I think this might fix the problems that blew up the CI system recently.

 drivers/gpu/drm/i915/intel_display.c | 10 ++++++++--
 1 file changed, 8 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 391cc7f..fdff460 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -15316,8 +15316,13 @@ retry:
 	}
 
 	state = drm_atomic_helper_duplicate_state(dev, &ctx);
-	if (WARN_ON(IS_ERR(state)))
-		return;
+	ret = PTR_ERR_OR_ZERO(state);
+	if (ret == -EDEADLK) {
+		drm_modeset_backoff(&ctx);
+		goto retry;
+	} else if (WARN_ON(ret)) {
+		goto fail;
+	}
 
 	ret = intel_atomic_check(dev, state);
 	if (ret) {
@@ -15345,6 +15350,7 @@ retry:
 	}
 
 	drm_atomic_state_free(state);
+fail:
 	drm_modeset_drop_locks(&ctx);
 	drm_modeset_acquire_fini(&ctx);
 }
-- 
2.1.4

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^ permalink raw reply related	[flat|nested] 90+ messages in thread
* [PATCH] drm: Release driver references to handle before making it available again
@ 2016-01-08 20:25 Chris Wilson
  2016-01-11 10:53 ` ✗ warning: Fi.CI.BAT Patchwork
  2016-01-11 10:55 ` Patchwork
  0 siblings, 2 replies; 90+ messages in thread
From: Chris Wilson @ 2016-01-08 20:25 UTC (permalink / raw)
  To: intel-gfx; +Cc: Russell King, dri-devel, Daniel Vetter, Dan Carpenter

When userspace closes a handle, we remove it from the file->object_idr
and then tell the driver to drop its references to that file/handle.
However, as the file/handle is already available again for reuse, it may
be reallocated back to userspace and active on a new object before the
driver has had a chance to drop the old file/handle references.

Whilst calling back into the driver, we have to drop the
file->table_lock spinlock and so to prevent reusing the closed handle we
mark that handle as stale in the idr, perform the callback and then
remove the handle. It is then possible for a lookup on that handle to
return an error object and so all callers of idr_find(file->object_idr)
need to check against IS_ERR_OR_NULL() instead.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: dri-devel@lists.freedesktop.org
Cc: David Airlie <airlied@linux.ie>
Cc: Lucas Stach <l.stach@pengutronix.de>
Cc: Russell King <linux+etnaviv@arm.linux.org.uk>
Cc: Christian Gmeiner <christian.gmeiner@gmail.com>
Cc: Daniel Vetter <daniel.vetter@intel.com>
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Cc: Rob Clark <robdclark@gmail.com>
Cc: Eric Anholt <eric@anholt.net>
Cc: Dan Carpenter <dan.carpenter@oracle.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/drm_gem.c                    | 11 +++++++----
 drivers/gpu/drm/etnaviv/etnaviv_gem_submit.c |  2 +-
 drivers/gpu/drm/i915/i915_gem_execbuffer.c   |  2 +-
 drivers/gpu/drm/msm/msm_gem_submit.c         |  2 +-
 drivers/gpu/drm/vc4/vc4_gem.c                |  2 +-
 5 files changed, 11 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/drm_gem.c b/drivers/gpu/drm/drm_gem.c
index 2e8c77e71e1f..c56a0b49d829 100644
--- a/drivers/gpu/drm/drm_gem.c
+++ b/drivers/gpu/drm/drm_gem.c
@@ -294,18 +294,21 @@ drm_gem_handle_delete(struct drm_file *filp, u32 handle)
 	spin_lock(&filp->table_lock);
 
 	/* Check if we currently have a reference on the object */
-	obj = idr_find(&filp->object_idr, handle);
-	if (obj == NULL) {
+	obj = idr_replace(&filp->object_idr, ERR_PTR(-ENOENT), handle);
+	if (IS_ERR(obj)) {
 		spin_unlock(&filp->table_lock);
 		return -EINVAL;
 	}
 	dev = obj->dev;
+	spin_unlock(&filp->table_lock);
 
 	/* Release reference and decrement refcount. */
+	drm_gem_object_release_handle(handle, obj, filp);
+
+	spin_lock(&filp->table_lock);
 	idr_remove(&filp->object_idr, handle);
 	spin_unlock(&filp->table_lock);
 
-	drm_gem_object_release_handle(handle, obj, filp);
 	return 0;
 }
 EXPORT_SYMBOL(drm_gem_handle_delete);
@@ -597,7 +600,7 @@ drm_gem_object_lookup(struct drm_device *dev, struct drm_file *filp,
 
 	/* Check if we currently have a reference on the object */
 	obj = idr_find(&filp->object_idr, handle);
-	if (obj == NULL) {
+	if (IS_ERR_OR_NULL(obj)) {
 		spin_unlock(&filp->table_lock);
 		return NULL;
 	}
diff --git a/drivers/gpu/drm/etnaviv/etnaviv_gem_submit.c b/drivers/gpu/drm/etnaviv/etnaviv_gem_submit.c
index 1aba01a999df..77b549cb1301 100644
--- a/drivers/gpu/drm/etnaviv/etnaviv_gem_submit.c
+++ b/drivers/gpu/drm/etnaviv/etnaviv_gem_submit.c
@@ -78,7 +78,7 @@ static int submit_lookup_objects(struct etnaviv_gem_submit *submit,
 		 * all under single table_lock just hit object_idr directly:
 		 */
 		obj = idr_find(&file->object_idr, bo->handle);
-		if (!obj) {
+		if (IS_ERR_OR_NULL(obj)) {
 			DRM_ERROR("invalid handle %u at index %u\n",
 				  bo->handle, i);
 			ret = -EINVAL;
diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
index dccb517361b3..500bcff9ad48 100644
--- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
@@ -106,7 +106,7 @@ eb_lookup_vmas(struct eb_vmas *eb,
 	 * or create the VMA without using GFP_ATOMIC */
 	for (i = 0; i < args->buffer_count; i++) {
 		obj = to_intel_bo(idr_find(&file->object_idr, exec[i].handle));
-		if (obj == NULL) {
+		if (IS_ERR_OR_NULL(obj)) {
 			spin_unlock(&file->table_lock);
 			DRM_DEBUG("Invalid object handle %d at index %d\n",
 				   exec[i].handle, i);
diff --git a/drivers/gpu/drm/msm/msm_gem_submit.c b/drivers/gpu/drm/msm/msm_gem_submit.c
index 6d7cd3fe21e7..c6d7abd53d20 100644
--- a/drivers/gpu/drm/msm/msm_gem_submit.c
+++ b/drivers/gpu/drm/msm/msm_gem_submit.c
@@ -90,7 +90,7 @@ static int submit_lookup_objects(struct msm_gem_submit *submit,
 		 * all under single table_lock just hit object_idr directly:
 		 */
 		obj = idr_find(&file->object_idr, submit_bo.handle);
-		if (!obj) {
+		if (IS_ERR_OR_NULL(obj)) {
 			DRM_ERROR("invalid handle %u at index %u\n", submit_bo.handle, i);
 			ret = -EINVAL;
 			goto out_unlock;
diff --git a/drivers/gpu/drm/vc4/vc4_gem.c b/drivers/gpu/drm/vc4/vc4_gem.c
index 48ce30a6f4b5..9138702a1c67 100644
--- a/drivers/gpu/drm/vc4/vc4_gem.c
+++ b/drivers/gpu/drm/vc4/vc4_gem.c
@@ -494,7 +494,7 @@ vc4_cl_lookup_bos(struct drm_device *dev,
 	for (i = 0; i < exec->bo_count; i++) {
 		struct drm_gem_object *bo = idr_find(&file_priv->object_idr,
 						     handles[i]);
-		if (!bo) {
+		if (IS_ERR_OR_NULL(bo)) {
 			DRM_ERROR("Failed to look up GEM BO %d: %d\n",
 				  i, handles[i]);
 			ret = -EINVAL;
-- 
2.7.0.rc3

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^ permalink raw reply related	[flat|nested] 90+ messages in thread
* [PATCH 1/2] drm/i915: Store edram capabilities instead of fixed size
@ 2016-01-08 16:58 Mika Kuoppala
  2016-01-11 10:27 ` ✗ warning: Fi.CI.BAT Patchwork
  0 siblings, 1 reply; 90+ messages in thread
From: Mika Kuoppala @ 2016-01-08 16:58 UTC (permalink / raw)
  To: intel-gfx

Store the edram capabilities instead of only the size of
edram. This is preparatory patch to allow edram size calculation
based on edram capability bits for gen9+.

Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
---
 drivers/gpu/drm/i915/i915_debugfs.c |  2 +-
 drivers/gpu/drm/i915/i915_drv.h     |  7 +++++--
 drivers/gpu/drm/i915/i915_gem.c     |  2 +-
 drivers/gpu/drm/i915/i915_gem_gtt.c |  2 +-
 drivers/gpu/drm/i915/i915_reg.h     |  2 +-
 drivers/gpu/drm/i915/intel_uncore.c | 39 +++++++++++++++++++++++++------------
 6 files changed, 36 insertions(+), 18 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index e3377abc0d4d..039ace6e4524 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2401,7 +2401,7 @@ static int i915_llc(struct seq_file *m, void *data)
 
 	/* Size calculation for LLC is a bit of a pain. Ignore for now. */
 	seq_printf(m, "LLC: %s\n", yesno(HAS_LLC(dev)));
-	seq_printf(m, "eLLC: %zuMB\n", dev_priv->ellc_size);
+	seq_printf(m, "eLLC: %zuMB\n", intel_uncore_edram_size_mb(dev_priv));
 
 	return 0;
 }
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 6ef03eea3518..c81f537b2da7 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1846,7 +1846,7 @@ struct drm_i915_private {
 	struct intel_l3_parity l3_parity;
 
 	/* Cannot be determined by PCIID. You must always read a register. */
-	size_t ellc_size;
+	u32 edram_cap;
 
 	/* gen6+ rps state */
 	struct intel_gen6_power_mgmt rps;
@@ -2567,8 +2567,9 @@ struct drm_i915_cmd_table {
 #define HAS_BLT(dev)		(INTEL_INFO(dev)->ring_mask & BLT_RING)
 #define HAS_VEBOX(dev)		(INTEL_INFO(dev)->ring_mask & VEBOX_RING)
 #define HAS_LLC(dev)		(INTEL_INFO(dev)->has_llc)
+#define HAS_EDRAM(dev)		(__I915__(dev)->edram_cap & EDRAM_ENABLED)
 #define HAS_WT(dev)		((IS_HASWELL(dev) || IS_BROADWELL(dev)) && \
-				 __I915__(dev)->ellc_size)
+				 HAS_EDRAM(dev))
 #define I915_NEED_GFX_HWS(dev)	(INTEL_INFO(dev)->need_gfx_hws)
 
 #define HAS_HW_CONTEXTS(dev)	(INTEL_INFO(dev)->gen >= 6)
@@ -2735,6 +2736,8 @@ void intel_uncore_forcewake_get__locked(struct drm_i915_private *dev_priv,
 					enum forcewake_domains domains);
 void intel_uncore_forcewake_put__locked(struct drm_i915_private *dev_priv,
 					enum forcewake_domains domains);
+unsigned intel_uncore_edram_size_mb(struct drm_i915_private *dev_priv);
+
 void assert_forcewakes_inactive(struct drm_i915_private *dev_priv);
 static inline bool intel_vgpu_active(struct drm_device *dev)
 {
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index d8efc9dfbc48..0a5e5524def3 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -4799,7 +4799,7 @@ i915_gem_init_hw(struct drm_device *dev)
 	/* Double layer security blanket, see i915_gem_init() */
 	intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
 
-	if (dev_priv->ellc_size)
+	if (HAS_EDRAM(dev_priv))
 		I915_WRITE(HSW_IDICR, I915_READ(HSW_IDICR) | IDIHASHMSK(0xf));
 
 	if (IS_HASWELL(dev))
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 56f4f2e58d53..1d1933130b7a 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -3157,7 +3157,7 @@ int i915_gem_gtt_init(struct drm_device *dev)
 	} else if (INTEL_INFO(dev)->gen < 8) {
 		gtt->gtt_probe = gen6_gmch_probe;
 		gtt->base.cleanup = gen6_gmch_remove;
-		if (IS_HASWELL(dev) && dev_priv->ellc_size)
+		if (HAS_EDRAM(dev))
 			gtt->base.pte_encode = iris_pte_encode;
 		else if (IS_HASWELL(dev))
 			gtt->base.pte_encode = hsw_pte_encode;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 556a458d669e..f88b75ec5047 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6818,7 +6818,7 @@ enum skl_disp_power_wells {
 
 #define  HSW_IDICR				_MMIO(0x9008)
 #define    IDIHASHMSK(x)			(((x) & 0x3f) << 16)
-#define  HSW_EDRAM_PRESENT			_MMIO(0x120010)
+#define  HSW_EDRAM_CAP				_MMIO(0x120010)
 #define    EDRAM_ENABLED			0x1
 
 #define GEN6_UCGCTL1				_MMIO(0x9400)
diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
index d0973e08e7eb..0c9059cb3d13 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -310,21 +310,36 @@ void intel_uncore_forcewake_reset(struct drm_device *dev, bool restore)
 	spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 }
 
-static void intel_uncore_ellc_detect(struct drm_device *dev)
+unsigned intel_uncore_edram_size_mb(struct drm_i915_private *dev_priv)
 {
-	struct drm_i915_private *dev_priv = dev->dev_private;
+	if (!HAS_EDRAM(dev_priv))
+		return 0;
+
+	/* The docs do not explain exactly how the calculation can be
+	 * made. It is somewhat guessable, but for now, it's always
+	 * 128MB.
+	 */
+
+	return 128;
+}
 
-	if ((IS_HASWELL(dev) || IS_BROADWELL(dev) ||
-	     INTEL_INFO(dev)->gen >= 9) &&
-	    (__raw_i915_read32(dev_priv, HSW_EDRAM_PRESENT) & EDRAM_ENABLED)) {
-		/* The docs do not explain exactly how the calculation can be
-		 * made. It is somewhat guessable, but for now, it's always
-		 * 128MB.
-		 * NB: We can't write IDICR yet because we do not have gt funcs
+static void intel_uncore_edram_detect(struct drm_i915_private *dev_priv)
+{
+	if (IS_HASWELL(dev_priv) ||
+	    IS_BROADWELL(dev_priv) ||
+	    INTEL_INFO(dev_priv)->gen >= 9) {
+		dev_priv->edram_cap = __raw_i915_read32(dev_priv,
+							HSW_EDRAM_CAP);
+
+		/* NB: We can't write IDICR yet because we do not have gt funcs
 		 * set up */
-		dev_priv->ellc_size = 128;
-		DRM_INFO("Found %zuMB of eLLC\n", dev_priv->ellc_size);
+	} else {
+		dev_priv->edram_cap = 0;
 	}
+
+	if (HAS_EDRAM(dev_priv))
+		DRM_INFO("Found %zuMB of eLLC\n",
+			 intel_uncore_edram_size_mb(dev_priv));
 }
 
 static bool
@@ -1239,7 +1254,7 @@ void intel_uncore_init(struct drm_device *dev)
 
 	i915_check_vgpu(dev);
 
-	intel_uncore_ellc_detect(dev);
+	intel_uncore_edram_detect(dev_priv);
 	intel_uncore_fw_domains_init(dev);
 	__intel_uncore_early_sanitize(dev, false);
 
-- 
2.5.0

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^ permalink raw reply related	[flat|nested] 90+ messages in thread
* [PATCH 0/3] Enabling GuC Loading on Broxton
@ 2016-01-08 15:03 Peter Antoine
  2016-01-11 10:13 ` ✗ warning: Fi.CI.BAT Patchwork
  0 siblings, 1 reply; 90+ messages in thread
From: Peter Antoine @ 2016-01-08 15:03 UTC (permalink / raw)
  To: intel-gfx; +Cc: daniel.vetter, dave.gordon

This set of patches will enable the GuC loading for BXT.
There is also a fix that is required for GuC submission with the BXT GuC
to make it reliable.

Peter Antoine (3):
  drm/i915: Adding Broxton GuC Loader Support
  drm/i915: resize the GuC WOPCM for rc6
  drm/i915: Wait after context init with GuC Submission

 drivers/gpu/drm/i915/i915_gem.c         | 10 ++++++++++
 drivers/gpu/drm/i915/i915_guc_reg.h     |  3 ++-
 drivers/gpu/drm/i915/intel_guc_loader.c | 12 ++++++++++++
 drivers/gpu/drm/i915/intel_lrc.c        | 11 +++++++++++
 4 files changed, 35 insertions(+), 1 deletion(-)

-- 
1.9.1

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^ permalink raw reply	[flat|nested] 90+ messages in thread
* [PATCH 0/5] Add encoder_mask to crtc_state, v2.
@ 2016-01-07  9:59 Maarten Lankhorst
  2016-01-11  8:52 ` ✗ warning: Fi.CI.BAT Patchwork
  0 siblings, 1 reply; 90+ messages in thread
From: Maarten Lankhorst @ 2016-01-07  9:59 UTC (permalink / raw)
  To: dri-devel; +Cc: intel-gfx

Another attempt at adding encoder_mask, with some behavioral fixes.

Maarten Lankhorst (5):
  drm/core: Add drm_encoder_index.
  drm/core: Add drm_for_each_encoder_mask, v2.
  drm/i915: Do not touch best_encoder for load detect.
  drm/atomic: Do not unset crtc when an encoder is stolen
  drm/atomic: Add encoder_mask to crtc_state, v2.

 drivers/gpu/drm/drm_atomic_helper.c  | 46 ++++++++++++++++++++++++++++++------
 drivers/gpu/drm/drm_crtc.c           | 23 ++++++++++++++++++
 drivers/gpu/drm/i915/intel_display.c |  5 ++--
 include/drm/drm_crtc.h               | 14 +++++++++++
 4 files changed, 79 insertions(+), 9 deletions(-)

-- 
2.1.0

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^ permalink raw reply	[flat|nested] 90+ messages in thread
* [PATCH] drm/i915/guc: Fix a memory leak where guc->execbuf_client is not freed
@ 2016-01-06 20:53 yu.dai
  2016-01-14  9:49 ` ✗ warning: Fi.CI.BAT Patchwork
  0 siblings, 1 reply; 90+ messages in thread
From: yu.dai @ 2016-01-06 20:53 UTC (permalink / raw)
  To: intel-gfx

From: Alex Dai <yu.dai@intel.com>

During driver unloading, the guc_client created for command submission
needs to be released to avoid memory leak.

Signed-off-by: Alex Dai <yu.dai@intel.com>
---
 drivers/gpu/drm/i915/i915_guc_submission.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c b/drivers/gpu/drm/i915/i915_guc_submission.c
index 9c24424..8ce4f32 100644
--- a/drivers/gpu/drm/i915/i915_guc_submission.c
+++ b/drivers/gpu/drm/i915/i915_guc_submission.c
@@ -995,6 +995,9 @@ void i915_guc_submission_fini(struct drm_device *dev)
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct intel_guc *guc = &dev_priv->guc;
 
+	if (i915.enable_guc_submission)
+		i915_guc_submission_disable(dev);
+
 	gem_release_guc_obj(dev_priv->guc.ads_obj);
 	guc->ads_obj = NULL;
 
-- 
2.5.0

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^ permalink raw reply related	[flat|nested] 90+ messages in thread
* [PATCH 0/5] Some minor CSB/execlist stuff
@ 2016-01-05 18:30 Ben Widawsky
  2016-01-06  8:20 ` ✗ warning: Fi.CI.BAT Patchwork
  0 siblings, 1 reply; 90+ messages in thread
From: Ben Widawsky @ 2016-01-05 18:30 UTC (permalink / raw)
  To: Intel GFX; +Cc: Rodrigo Vivi, Ben Widawsky

While doing some debug in simulation, I came across a handful of patches which I
think are beneficial today. Mostly this just has some minor cleanups and error
state additions. They're pretty optional, though I have a private branch that
depends on some of this stuff, so it'd be nice to land as much as possible - but
I'll live without it.

Ben Widawsky (5):
  drm/i915: Cleanup some of the CSB handling
  drm/i915: change WARN to ERROR in CSB count
  drm/i915: Extract CSB status read
  drm/i915: Add basic execlist info to error state
  drm/i915: Use CSB helper in debugfs

 drivers/gpu/drm/i915/i915_debugfs.c   |  9 ++++-----
 drivers/gpu/drm/i915/i915_drv.h       |  7 ++++++-
 drivers/gpu/drm/i915/i915_gpu_error.c | 23 +++++++++++++++++++++
 drivers/gpu/drm/i915/intel_lrc.c      | 38 ++++++++++++++++++++++++++---------
 drivers/gpu/drm/i915/intel_lrc.h      | 22 ++++++++++++++++++--
 5 files changed, 81 insertions(+), 18 deletions(-)

-- 
2.6.4

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^ permalink raw reply	[flat|nested] 90+ messages in thread
* [PATCH] drm/i915: Update Skylake DDI translation table for DP.
@ 2016-01-05 15:58 Rodrigo Vivi
  2016-01-06  7:20 ` ✗ warning: Fi.CI.BAT Patchwork
  0 siblings, 1 reply; 90+ messages in thread
From: Rodrigo Vivi @ 2016-01-05 15:58 UTC (permalink / raw)
  To: intel-gfx; +Cc: Rodrigo Vivi

When reviewing DDI translation table I noticed few changes we
haven't incorporated yet and it is always good to follow latest
spec.

Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/i915/intel_ddi.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index c7e3114..8f16b13 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -145,7 +145,7 @@ static const struct ddi_buf_trans skl_ddi_translations_dp[] = {
 static const struct ddi_buf_trans skl_u_ddi_translations_dp[] = {
 	{ 0x0000201B, 0x000000A2, 0x0 },
 	{ 0x00005012, 0x00000088, 0x0 },
-	{ 0x00007011, 0x00000087, 0x0 },
+	{ 0x80007011, 0x000000CD, 0x0 },
 	{ 0x80009010, 0x000000C0, 0x1 },	/* Uses I_boost level 0x1 */
 	{ 0x0000201B, 0x0000009D, 0x0 },
 	{ 0x80005012, 0x000000C0, 0x1 },	/* Uses I_boost level 0x1 */
@@ -158,7 +158,7 @@ static const struct ddi_buf_trans skl_u_ddi_translations_dp[] = {
 static const struct ddi_buf_trans skl_y_ddi_translations_dp[] = {
 	{ 0x00000018, 0x000000A2, 0x0 },
 	{ 0x00005012, 0x00000088, 0x0 },
-	{ 0x00007011, 0x00000087, 0x0 },
+	{ 0x80007011, 0x000000CD, 0x0 },
 	{ 0x80009010, 0x000000C0, 0x3 },	/* Uses I_boost level 0x3 */
 	{ 0x00000018, 0x0000009D, 0x0 },
 	{ 0x80005012, 0x000000C0, 0x3 },	/* Uses I_boost level 0x3 */
-- 
2.4.3

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^ permalink raw reply related	[flat|nested] 90+ messages in thread
* [PATCH] drm/i915: Update Skylake DDI translation table for HDMI.
@ 2016-01-05 15:32 Rodrigo Vivi
  2016-01-05 17:49 ` ✗ warning: Fi.CI.BAT Patchwork
  0 siblings, 1 reply; 90+ messages in thread
From: Rodrigo Vivi @ 2016-01-05 15:32 UTC (permalink / raw)
  To: intel-gfx; +Cc: alex.feinman, Rodrigo Vivi

When debuging an intermittent corrupted screen I suspected on DDI
translation table and checked we are out of date with the spec.

I'm not sure this will fix my bug yet, but it is always good to follow
the spec.

Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/i915/intel_ddi.c | 20 ++++++++++----------
 1 file changed, 10 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index e6408e5..c7e3114 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -225,27 +225,27 @@ static const struct ddi_buf_trans skl_ddi_translations_hdmi[] = {
 	{ 0x00007011, 0x00000088, 0x0 },
 	{ 0x00000018, 0x000000A1, 0x0 },
 	{ 0x00000018, 0x00000098, 0x0 },
-	{ 0x00004013, 0x00000088, 0x0 },
-	{ 0x00006012, 0x00000087, 0x0 },
+	{ 0x00004013, 0x00000088, 0x1 },
+	{ 0x80006012, 0x000000CD, 0x0 },
 	{ 0x00000018, 0x000000DF, 0x0 },
-	{ 0x00003015, 0x00000087, 0x0 },	/* Default */
-	{ 0x00003015, 0x000000C7, 0x0 },
-	{ 0x00000018, 0x000000C7, 0x0 },
+	{ 0x80003015, 0x000000CD, 0x1 },	/* Default */
+	{ 0x80003015, 0x000000C0, 0x1 },
+	{ 0x80000018, 0x000000C0, 0x1 },
 };
 
 /* Skylake Y */
 static const struct ddi_buf_trans skl_y_ddi_translations_hdmi[] = {
 	{ 0x00000018, 0x000000A1, 0x0 },
 	{ 0x00005012, 0x000000DF, 0x0 },
-	{ 0x00007011, 0x00000084, 0x0 },
+	{ 0x80007011, 0x000000CB, 0x3 },
 	{ 0x00000018, 0x000000A4, 0x0 },
 	{ 0x00000018, 0x0000009D, 0x0 },
 	{ 0x00004013, 0x00000080, 0x0 },
-	{ 0x00006013, 0x000000C7, 0x0 },
+	{ 0x80006013, 0x000000C0, 0x3 },
 	{ 0x00000018, 0x0000008A, 0x0 },
-	{ 0x00003015, 0x000000C7, 0x0 },	/* Default */
-	{ 0x80003015, 0x000000C7, 0x7 },	/* Uses I_boost level 0x7 */
-	{ 0x00000018, 0x000000C7, 0x0 },
+	{ 0x80003015, 0x000000C0, 0x3 },	/* Default */
+	{ 0x80003015, 0x000000C0, 0x3 },
+	{ 0x80000018, 0x000000C0, 0x3 },
 };
 
 struct bxt_ddi_buf_trans {
-- 
2.4.3

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^ permalink raw reply related	[flat|nested] 90+ messages in thread
* [PATCH 0/6] Fixing sink count related detection over
@ 2016-01-05 12:50 Shubhangi Shrivastava
  2016-01-05 13:49 ` ✗ warning: Fi.CI.BAT Patchwork
  0 siblings, 1 reply; 90+ messages in thread
From: Shubhangi Shrivastava @ 2016-01-05 12:50 UTC (permalink / raw)
  To: intel-gfx; +Cc: Shubhangi Shrivastava

This patch set cleans up DP detection logic to bring all DPCD
operations at one place and to create a clear demarcation
between handling of long and short pulses. This simplifies
fixing of sink count related detection for DP panels.

Patches:
1. First two patches clean up intel_dp_detect and form a new
function which will include all DPCD related operations.
2. Third patch splits up intel_dp_check_link_status to form
a new function which will handle short pulse requests.
3. Last three patches fixes the detection logic related to
sink count i.e detect changes in sink count and handle them
appropriately. 

Shubhangi Shrivastava (6):
  drm/i915: Splitting intel_dp_detect
  drm/i915: Cleaning up intel_dp_hpd_pulse
  drm/i915: Splitting intel_dp_check_link_status
  drm/i915: Save sink_count for tracking changes to it
  drm/i915: read sink_count dpcd always
  drm/i915: force full detect on sink count change

 drivers/gpu/drm/i915/intel_dp.c  | 170 +++++++++++++++++++++++++--------------
 drivers/gpu/drm/i915/intel_drv.h |   1 +
 2 files changed, 110 insertions(+), 61 deletions(-)

-- 
2.6.1

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^ permalink raw reply	[flat|nested] 90+ messages in thread
* [PATCH] [trivial] drm/i915 Fix typos in i915_gem_fence.c
@ 2016-01-05  3:29 Masanari Iida
  2016-01-05  8:20 ` ✗ warning: Fi.CI.BAT Patchwork
  0 siblings, 1 reply; 90+ messages in thread
From: Masanari Iida @ 2016-01-05  3:29 UTC (permalink / raw)
  To: linux-kernel, daniel.vetter, trivial, jani.nikula, dri-devel,
	intel-gfx, rdunlap
  Cc: corbet, Masanari Iida

This patch fix some spelling typos found in Documentation/Docbook
gpu/ch04s03.html.  This file was generated from comments within
source, so I have to fix typos in i915_gem_fence.c.

Signed-off-by: Masanari Iida <standby24x7@gmail.com>
---
 drivers/gpu/drm/i915/i915_gem_fence.c | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_fence.c b/drivers/gpu/drm/i915/i915_gem_fence.c
index 5981985..a2b938e 100644
--- a/drivers/gpu/drm/i915/i915_gem_fence.c
+++ b/drivers/gpu/drm/i915/i915_gem_fence.c
@@ -34,8 +34,8 @@
  * set of these objects.
  *
  * Fences are used to detile GTT memory mappings. They're also connected to the
- * hardware frontbuffer render tracking and hence interract with frontbuffer
- * conmpression. Furthermore on older platforms fences are required for tiled
+ * hardware frontbuffer render tracking and hence interact with frontbuffer
+ * compression. Furthermore on older platforms fences are required for tiled
  * objects used by the display engine. They can also be used by the render
  * engine - they're required for blitter commands and are optional for render
  * commands. But on gen4+ both display (with the exception of fbc) and rendering
@@ -46,8 +46,8 @@
  *
  * Finally note that because fences are such a restricted resource they're
  * dynamically associated with objects. Furthermore fence state is committed to
- * the hardware lazily to avoid unecessary stalls on gen2/3. Therefore code must
- * explictly call i915_gem_object_get_fence() to synchronize fencing status
+ * the hardware lazily to avoid unnecessary stalls on gen2/3. Therefore code must
+ * explicitly call i915_gem_object_get_fence() to synchronize fencing status
  * for cpu access. Also note that some code wants an unfenced view, for those
  * cases the fence can be removed forcefully with i915_gem_object_put_fence().
  *
@@ -527,7 +527,7 @@ void i915_gem_restore_fences(struct drm_device *dev)
  * required.
  *
  * When bit 17 is XORed in, we simply refuse to tile at all.  Bit
- * 17 is not just a page offset, so as we page an objet out and back in,
+ * 17 is not just a page offset, so as we page an object out and back in,
  * individual pages in it will have different bit 17 addresses, resulting in
  * each 64 bytes being swapped with its neighbor!
  *
-- 
2.7.0.rc3


^ permalink raw reply related	[flat|nested] 90+ messages in thread
* [PATCH 1/3] drm/i915: Move HAS_PSR definition to the platform definition.
@ 2016-01-05  1:10 Rodrigo Vivi
  2016-01-05  7:49 ` ✗ warning: Fi.CI.BAT Patchwork
  0 siblings, 1 reply; 90+ messages in thread
From: Rodrigo Vivi @ 2016-01-05  1:10 UTC (permalink / raw)
  To: intel-gfx; +Cc: Rodrigo Vivi

No functional changes with this patch. The idea is just to organize
the platform features in a standard place making new platform aditions
easily and possible to see all the present features of the platform on
the intel info dumped information at dmesg.

Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.c | 3 +++
 drivers/gpu/drm/i915/i915_drv.h | 5 ++---
 2 files changed, 5 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 3ac616d..6fea26f 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -251,6 +251,7 @@ static const struct intel_device_info intel_ivybridge_q_info = {
 
 #define VLV_FEATURES  \
 	.gen = 7, .num_pipes = 2, \
+	.has_psr = 1, \
 	.need_gfx_hws = 1, .has_hotplug = 1, \
 	.ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
 	.display_mmio_offset = VLV_DISPLAY_BASE, \
@@ -272,6 +273,7 @@ static const struct intel_device_info intel_valleyview_d_info = {
 	GEN7_FEATURES, \
 	.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, \
 	.has_ddi = 1, \
+	.has_psr = 1, \
 	.has_fpga_dbg = 1
 
 static const struct intel_device_info intel_haswell_d_info = {
@@ -312,6 +314,7 @@ static const struct intel_device_info intel_cherryview_info = {
 	.need_gfx_hws = 1, .has_hotplug = 1,
 	.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
 	.is_cherryview = 1,
+	.has_psr = 1,
 	.display_mmio_offset = VLV_DISPLAY_BASE,
 	GEN_CHV_PIPEOFFSETS,
 	CURSOR_OFFSETS,
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index cf7e0fc..20840f0 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -763,6 +763,7 @@ struct intel_csr {
 	func(is_kabylake) sep \
 	func(is_preliminary) sep \
 	func(has_fbc) sep \
+	func(has_psr) sep \
 	func(has_pipe_cxsr) sep \
 	func(has_hotplug) sep \
 	func(cursor_needs_physical) sep \
@@ -2604,9 +2605,7 @@ struct drm_i915_cmd_table {
 
 #define HAS_DDI(dev)		(INTEL_INFO(dev)->has_ddi)
 #define HAS_FPGA_DBG_UNCLAIMED(dev)	(INTEL_INFO(dev)->has_fpga_dbg)
-#define HAS_PSR(dev)		(IS_HASWELL(dev) || IS_BROADWELL(dev) || \
-				 IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev) || \
-				 IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
+#define HAS_PSR(dev)		(INTEL_INFO(dev)->has_psr)
 #define HAS_RUNTIME_PM(dev)	(IS_GEN6(dev) || IS_HASWELL(dev) || \
 				 IS_BROADWELL(dev) || IS_VALLEYVIEW(dev) || \
 				 IS_CHERRYVIEW(dev) || IS_SKYLAKE(dev) || \
-- 
2.4.3

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^ permalink raw reply related	[flat|nested] 90+ messages in thread
* [PATCH] drm/i915: Allow a way to disable watermark for debuging purposes.
@ 2016-01-04 23:00 Rodrigo Vivi
  2016-01-05  7:20 ` ✗ warning: Fi.CI.BAT Patchwork
  0 siblings, 1 reply; 90+ messages in thread
From: Rodrigo Vivi @ 2016-01-04 23:00 UTC (permalink / raw)
  To: intel-gfx; +Cc: Rodrigo Vivi

Without watermark the power consumption will blow up, but
when enabling platforms and dealing with different kinds of
crashes, screen corruptions, pipe underuns, etc we need to be
able to easily disable watermark to see if we are on the right
investigation track.

Another possibility was to skip at the beginning and avoid all
calculations, but I'm not sure about it. Maybe it might be still
useful to know the calculated values when debuging.

Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/i915/i915_params.c |  4 ++++
 drivers/gpu/drm/i915/i915_params.h |  1 +
 drivers/gpu/drm/i915/intel_pm.c    | 14 +++++++++-----
 3 files changed, 14 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_params.c b/drivers/gpu/drm/i915/i915_params.c
index 8d90c25..7a0909d 100644
--- a/drivers/gpu/drm/i915/i915_params.c
+++ b/drivers/gpu/drm/i915/i915_params.c
@@ -42,6 +42,7 @@ struct i915_params i915 __read_mostly = {
 	.preliminary_hw_support = IS_ENABLED(CONFIG_DRM_I915_PRELIMINARY_HW_SUPPORT),
 	.disable_power_well = -1,
 	.enable_ips = 1,
+	.enable_watermark = 1,
 	.fastboot = 0,
 	.prefault_disable = 0,
 	.load_detect_test = 0,
@@ -141,6 +142,9 @@ MODULE_PARM_DESC(disable_power_well,
 module_param_named_unsafe(enable_ips, i915.enable_ips, int, 0600);
 MODULE_PARM_DESC(enable_ips, "Enable IPS (default: true)");
 
+module_param_named_unsafe(enable_watermark, i915.enable_watermark, int, 0600);
+MODULE_PARM_DESC(enable_watermark, "Enable Watermark (default: true)");
+
 module_param_named(fastboot, i915.fastboot, bool, 0600);
 MODULE_PARM_DESC(fastboot,
 	"Try to skip unnecessary mode sets at boot time (default: false)");
diff --git a/drivers/gpu/drm/i915/i915_params.h b/drivers/gpu/drm/i915/i915_params.h
index 5299290..a1856e0 100644
--- a/drivers/gpu/drm/i915/i915_params.h
+++ b/drivers/gpu/drm/i915/i915_params.h
@@ -43,6 +43,7 @@ struct i915_params {
 	unsigned int preliminary_hw_support;
 	int disable_power_well;
 	int enable_ips;
+	int enable_watermark;
 	int invert_brightness;
 	int enable_cmd_parser;
 	int guc_log_level;
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 02fe081..6f14cd7 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -2484,7 +2484,7 @@ static void ilk_compute_wm_results(struct drm_device *dev,
 			(r->pri_val << WM1_LP_SR_SHIFT) |
 			r->cur_val;
 
-		if (r->enable)
+		if (r->enable && i915.enable_watermark)
 			results->wm_lp[wm_lp - 1] |= WM1_LP_SR_EN;
 
 		if (INTEL_INFO(dev)->gen >= 8)
@@ -3258,7 +3258,8 @@ static void skl_compute_wm_results(struct drm_device *dev,
 			temp |= p_wm->wm[level].plane_res_l[i] <<
 					PLANE_WM_LINES_SHIFT;
 			temp |= p_wm->wm[level].plane_res_b[i];
-			if (p_wm->wm[level].plane_en[i])
+			if (p_wm->wm[level].plane_en[i]
+			    && i915.enable_watermark)
 				temp |= PLANE_WM_EN;
 
 			r->plane[pipe][i][level] = temp;
@@ -3269,7 +3270,8 @@ static void skl_compute_wm_results(struct drm_device *dev,
 		temp |= p_wm->wm[level].plane_res_l[PLANE_CURSOR] << PLANE_WM_LINES_SHIFT;
 		temp |= p_wm->wm[level].plane_res_b[PLANE_CURSOR];
 
-		if (p_wm->wm[level].plane_en[PLANE_CURSOR])
+		if (p_wm->wm[level].plane_en[PLANE_CURSOR]
+		    && i915.enable_watermark)
 			temp |= PLANE_WM_EN;
 
 		r->plane[pipe][PLANE_CURSOR][level] = temp;
@@ -3281,7 +3283,8 @@ static void skl_compute_wm_results(struct drm_device *dev,
 		temp = 0;
 		temp |= p_wm->trans_wm.plane_res_l[i] << PLANE_WM_LINES_SHIFT;
 		temp |= p_wm->trans_wm.plane_res_b[i];
-		if (p_wm->trans_wm.plane_en[i])
+		if (p_wm->trans_wm.plane_en[i]
+		    && i915.enable_watermark)
 			temp |= PLANE_WM_EN;
 
 		r->plane_trans[pipe][i] = temp;
@@ -3290,7 +3293,8 @@ static void skl_compute_wm_results(struct drm_device *dev,
 	temp = 0;
 	temp |= p_wm->trans_wm.plane_res_l[PLANE_CURSOR] << PLANE_WM_LINES_SHIFT;
 	temp |= p_wm->trans_wm.plane_res_b[PLANE_CURSOR];
-	if (p_wm->trans_wm.plane_en[PLANE_CURSOR])
+	if (p_wm->trans_wm.plane_en[PLANE_CURSOR]
+	    && i915.enable_watermark)
 		temp |= PLANE_WM_EN;
 
 	r->plane_trans[pipe][PLANE_CURSOR] = temp;
-- 
2.4.3

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^ permalink raw reply related	[flat|nested] 90+ messages in thread
* [PATCH v2 1/6] drm/i915: Set connector_state->connector using the helper.
@ 2016-01-04 11:53 Maarten Lankhorst
  2016-01-04 12:49 ` ✗ warning: Fi.CI.BAT Patchwork
  0 siblings, 1 reply; 90+ messages in thread
From: Maarten Lankhorst @ 2016-01-04 11:53 UTC (permalink / raw)
  To: dri-devel; +Cc: intel-gfx

The atomic helper sets connector_state->connector, which the i915
code didn't. This will become a problem when we start using it.

Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Acked-by: Thierry Reding <treding@nvidia.com>
---
 drivers/gpu/drm/i915/intel_display.c | 6 ++----
 1 file changed, 2 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 7dd7200d3ba9..1e42309ec40a 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -6477,13 +6477,11 @@ static void intel_connector_check_state(struct intel_connector *connector)
 
 int intel_connector_init(struct intel_connector *connector)
 {
-	struct drm_connector_state *connector_state;
+	drm_atomic_helper_connector_reset(&connector->base);
 
-	connector_state = kzalloc(sizeof *connector_state, GFP_KERNEL);
-	if (!connector_state)
+	if (!connector->base.state)
 		return -ENOMEM;
 
-	connector->base.state = connector_state;
 	return 0;
 }
 
-- 
2.1.0

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^ permalink raw reply related	[flat|nested] 90+ messages in thread
* [PATCH v5 0/3] drm/i915: Disable link training optimization if DP config has changed
@ 2016-01-04 11:21 Mika Kahola
  2016-01-04 11:49 ` ✗ warning: Fi.CI.BAT Patchwork
  0 siblings, 1 reply; 90+ messages in thread
From: Mika Kahola @ 2016-01-04 11:21 UTC (permalink / raw)
  To: intel-gfx

These three patches are fixes for DP link trainging failures and flickering issues
reported by 

Mika Kahola (3):
  drm/i915: Disable fast link training if DP config changes
  drm/i915: Check DP no aux transaction bit on link training
  drm/i915: DP channel EQ check for use of DP link training optimization

 drivers/gpu/drm/i915/intel_dp.c               |  8 +++++++-
 drivers/gpu/drm/i915/intel_dp_link_training.c | 22 ++++++++++++++++++++++
 drivers/gpu/drm/i915/intel_drv.h              |  1 +
 3 files changed, 30 insertions(+), 1 deletion(-)

-- 
1.9.1

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^ permalink raw reply	[flat|nested] 90+ messages in thread
* [PATCH] drm/i915: Add RPM references in the *_get_hw_state functions
@ 2015-12-31 12:45 Gabriel Feceoru
  2015-12-31 16:20 ` ✗ warning: Fi.CI.BAT Patchwork
  0 siblings, 1 reply; 90+ messages in thread
From: Gabriel Feceoru @ 2015-12-31 12:45 UTC (permalink / raw)
  To: intel-gfx

This gets rid of errors like:

[  906.286213] ------------[ cut here ]------------
[  906.286233] WARNING: CPU: 0 PID: 12252 at drivers/gpu/drm/i915/intel_drv.h:1457 gen6_read32+0x1ca/0x1e0 [i915]()
[  906.286234] RPM wakelock ref not held during HW access
[  906.286235] Modules linked in:
[  906.286236]  snd_hda_intel i915 drm_kms_helper drm msr snd_hda_codec_hdmi snd_hda_codec_realtek snd_hda_codec_generic snd_hda_codec snd_hwdep x86_pkg_temp_thermal snd_hda_core i2c_algo_bit ehci_pci syscopyarea sysfillrect sysimgblt fb_sys_fops ehci_hcd r8169 xhci_pci mii xhci_hcd video [last unloaded: drm]
[  906.286246] CPU: 0 PID: 12252 Comm: kms_pipe_crc_ba Tainted: G     U  W       4.4.0-rc6+ #45
[  906.286247] Hardware name: Dell Inc. Inspiron 3847/088DT1       , BIOS A06 01/15/2015
[  906.286248]  ffffffffc022c098 ffff880210dbbae0 ffffffff813e0e4f ffff880210dbbb28
[  906.286250]  ffff880210dbbb18 ffffffff8105f5f2 ffff8801fff40000 0000000000046040
[  906.286251]  ffff8801fff49170 ffff8801fff49170 ffff8801fff40000 ffff880210dbbb78
[  906.286253] Call Trace:
[  906.286256]  [<ffffffff813e0e4f>] dump_stack+0x44/0x55
[  906.286259]  [<ffffffff8105f5f2>] warn_slowpath_common+0x82/0xc0
[  906.286261]  [<ffffffff8105f67c>] warn_slowpath_fmt+0x4c/0x50
[  906.286270]  [<ffffffffc007e29c>] ? drm_property_free_blob+0x8c/0xb0 [drm]
[  906.286280]  [<ffffffffc01a32ea>] gen6_read32+0x1ca/0x1e0 [i915]
[  906.286283]  [<ffffffff8172cd12>] ? mutex_lock+0x12/0x30
[  906.286294]  [<ffffffffc01e0ef0>] hsw_ddi_wrpll_get_hw_state+0x40/0x50 [i915]
[  906.286304]  [<ffffffffc01c3fa1>] intel_atomic_commit+0xd41/0x1740 [i915]
[  906.286312]  [<ffffffffc008c597>] drm_atomic_commit+0x37/0x60 [drm]
[  906.286316]  [<ffffffffc01373e6>] drm_atomic_helper_set_config+0x76/0xb0 [drm_kms_helper]
[  906.286323]  [<ffffffffc008ac0a>] ? drm_modeset_lock_all_ctx+0x9a/0xb0 [drm]
[  906.286329]  [<ffffffffc007b852>] drm_mode_set_config_internal+0x62/0x100 [drm]
[  906.286335]  [<ffffffffc007fcfd>] drm_mode_setcrtc+0x3cd/0x4e0 [drm]
[  906.286339]  [<ffffffffc0071762>] drm_ioctl+0x152/0x540 [drm]
[  906.286341]  [<ffffffff8109d914>] ? __wake_up+0x44/0x50
[  906.286346]  [<ffffffffc007f930>] ? drm_mode_setplane+0x1b0/0x1b0 [drm]
[  906.286348]  [<ffffffff811dc844>] ? mntput+0x24/0x40
[  906.286350]  [<ffffffff811bfe22>] ? __fput+0x172/0x1e0
[  906.286352]  [<ffffffff811d0758>] do_vfs_ioctl+0x288/0x460
[  906.286353]  [<ffffffff811bfece>] ? ____fput+0xe/0x10

Signed-off-by: Gabriel Feceoru <gabriel.feceoru@intel.com>
---
 drivers/gpu/drm/i915/intel_ddi.c | 48 ++++++++++++++++++++++++++++++----------
 1 file changed, 36 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index e6408e5..4ba9f2c 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -2014,15 +2014,18 @@ bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
 	enum intel_display_power_domain power_domain;
 	u32 tmp;
 	int i;
+	bool ret = false;
 
 	power_domain = intel_display_port_power_domain(encoder);
 	if (!intel_display_power_is_enabled(dev_priv, power_domain))
-		return false;
+		return ret;
+
+	intel_runtime_pm_get(dev_priv);
 
 	tmp = I915_READ(DDI_BUF_CTL(port));
 
 	if (!(tmp & DDI_BUF_CTL_ENABLE))
-		return false;
+		goto out;
 
 	if (port == PORT_A) {
 		tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
@@ -2040,7 +2043,8 @@ bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
 			break;
 		}
 
-		return true;
+		ret = true;
+		goto out;
 	} else {
 		for (i = TRANSCODER_A; i <= TRANSCODER_C; i++) {
 			tmp = I915_READ(TRANS_DDI_FUNC_CTL(i));
@@ -2048,17 +2052,19 @@ bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
 			if ((tmp & TRANS_DDI_PORT_MASK)
 			    == TRANS_DDI_SELECT_PORT(port)) {
 				if ((tmp & TRANS_DDI_MODE_SELECT_MASK) == TRANS_DDI_MODE_SELECT_DP_MST)
-					return false;
+					goto out;
 
 				*pipe = i;
-				return true;
+				ret = true;
+				goto out;
 			}
 		}
 	}
 
 	DRM_DEBUG_KMS("No pipe for ddi port %c found\n", port_name(port));
-
-	return false;
+out:
+	intel_runtime_pm_put(dev_priv);
+	return ret;
 }
 
 void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc)
@@ -2510,7 +2516,10 @@ static bool hsw_ddi_wrpll_get_hw_state(struct drm_i915_private *dev_priv,
 	if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
 		return false;
 
+	intel_runtime_pm_get(dev_priv);
 	val = I915_READ(WRPLL_CTL(pll->id));
+	intel_runtime_pm_put(dev_priv);
+
 	hw_state->wrpll = val;
 
 	return val & WRPLL_PLL_ENABLE;
@@ -2525,7 +2534,10 @@ static bool hsw_ddi_spll_get_hw_state(struct drm_i915_private *dev_priv,
 	if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
 		return false;
 
+	intel_runtime_pm_get(dev_priv);
 	val = I915_READ(SPLL_CTL);
+	intel_runtime_pm_put(dev_priv);
+
 	hw_state->spll = val;
 
 	return val & SPLL_PLL_ENABLE;
@@ -2644,16 +2656,19 @@ static bool skl_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv,
 	uint32_t val;
 	unsigned int dpll;
 	const struct skl_dpll_regs *regs = skl_dpll_regs;
+	bool ret = false;
 
 	if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
-		return false;
+		return ret;
 
 	/* DPLL0 is not part of the shared DPLLs, so pll->id is 0 for DPLL1 */
 	dpll = pll->id + 1;
 
+	intel_runtime_pm_get(dev_priv);
+
 	val = I915_READ(regs[pll->id].ctl);
 	if (!(val & LCPLL_PLL_ENABLE))
-		return false;
+		goto out;
 
 	val = I915_READ(DPLL_CTRL1);
 	hw_state->ctrl1 = (val >> (dpll * 6)) & 0x3f;
@@ -2664,6 +2679,9 @@ static bool skl_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv,
 		hw_state->cfgcr2 = I915_READ(regs[pll->id].cfgcr2);
 	}
 
+	ret = true;
+out:
+	intel_runtime_pm_put(dev_priv);
 	return true;
 }
 
@@ -2931,13 +2949,16 @@ static bool bxt_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv,
 {
 	enum port port = (enum port)pll->id;	/* 1:1 port->PLL mapping */
 	uint32_t val;
+	bool ret = false;
 
 	if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
-		return false;
+		return ret;
+
+	intel_runtime_pm_get(dev_priv);
 
 	val = I915_READ(BXT_PORT_PLL_ENABLE(port));
 	if (!(val & PORT_PLL_ENABLE))
-		return false;
+		goto out;
 
 	hw_state->ebb0 = I915_READ(BXT_PORT_PLL_EBB_0(port));
 	hw_state->ebb0 &= PORT_PLL_P1_MASK | PORT_PLL_P2_MASK;
@@ -2984,7 +3005,10 @@ static bool bxt_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv,
 				 I915_READ(BXT_PORT_PCS_DW12_LN23(port)));
 	hw_state->pcsdw12 &= LANE_STAGGER_MASK | LANESTAGGER_STRAP_OVRD;
 
-	return true;
+	ret = true;
+out:
+	intel_runtime_pm_put(dev_priv);
+	return ret;
 }
 
 static void bxt_shared_dplls_init(struct drm_i915_private *dev_priv)
-- 
2.5.0

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http://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 90+ messages in thread
* [PATCH] drm/i915/bxt: Save/Restore Backlight registers when PG0 is gated
@ 2015-12-31 10:00 Vidya Srinivas
  2015-12-31 10:20 ` ✗ warning: Fi.CI.BAT Patchwork
  0 siblings, 1 reply; 90+ messages in thread
From: Vidya Srinivas @ 2015-12-31 10:00 UTC (permalink / raw)
  To: intel-gfx; +Cc: Vidya Srinivas

Currently Backlight registers which are associated with Power Well 0
are not being saved before gating the power well for S0ix. Hence,
upon resume from S0ix, these registers are not being restored. Due to
this, the display has resumed and since there is no backlight, nothing is
seen. Patch fixes this issue by saving/restoring BLC registers for S0ix.

Signed-off-by: A.Sunil Kamath <sunil.kamath@intel.com>
Signed-off-by: Vidya Srinivas <vidya.srinivas@intel.com>
---
 drivers/gpu/drm/i915/intel_drv.h   |  4 ++++
 drivers/gpu/drm/i915/intel_panel.c | 18 ++++++++++++++++++
 2 files changed, 22 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 50f83d2..752fb58 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -193,6 +193,10 @@ struct intel_panel {
 				      uint32_t hz);
 		void (*power)(struct intel_connector *, bool enable);
 	} backlight;
+
+	u32 blc_pwm_ctl;
+	u32 blc_pwm_freq;
+	u32 blc_pwm_duty;
 };
 
 struct intel_connector {
diff --git a/drivers/gpu/drm/i915/intel_panel.c b/drivers/gpu/drm/i915/intel_panel.c
index ae808b6..421cd3a 100644
--- a/drivers/gpu/drm/i915/intel_panel.c
+++ b/drivers/gpu/drm/i915/intel_panel.c
@@ -816,6 +816,16 @@ static void bxt_disable_backlight(struct intel_connector *connector)
 		val &= ~UTIL_PIN_ENABLE;
 		I915_WRITE(UTIL_PIN_CTL, val);
 	}
+
+	/* Saving BLC registers for PG0 gating */
+	panel->blc_pwm_ctl =
+		I915_READ(BXT_BLC_PWM_CTL(panel->backlight.controller));
+	panel->blc_pwm_freq =
+		I915_READ(BXT_BLC_PWM_FREQ(panel->backlight.controller));
+	panel->blc_pwm_duty =
+		I915_READ(BXT_BLC_PWM_DUTY(panel->backlight.controller));
+
+
 }
 
 static void pwm_disable_backlight(struct intel_connector *connector)
@@ -1050,6 +1060,14 @@ static void bxt_enable_backlight(struct intel_connector *connector)
 	enum pipe pipe = intel_get_pipe_from_connector(connector);
 	u32 pwm_ctl, val;
 
+	/* Restore BLC registers if PG0 was gated */
+	I915_WRITE(BXT_BLC_PWM_CTL(panel->backlight.controller),
+				panel->blc_pwm_ctl);
+	I915_WRITE(BXT_BLC_PWM_FREQ(panel->backlight.controller),
+				panel->blc_pwm_freq);
+	I915_WRITE(BXT_BLC_PWM_DUTY(panel->backlight.controller),
+				panel->blc_pwm_duty);
+
 	/* To use 2nd set of backlight registers, utility pin has to be
 	 * enabled with PWM mode.
 	 * The field should only be changed when the utility pin is disabled
-- 
1.9.1

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http://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 90+ messages in thread
* [PATCH v2] i915: correctly handling failed allocation
@ 2015-12-30 15:59 Insu Yun
  2016-01-04  8:14 ` ✗ warning: Fi.CI.BAT Patchwork
  0 siblings, 1 reply; 90+ messages in thread
From: Insu Yun @ 2015-12-30 15:59 UTC (permalink / raw)
  To: daniel.vetter, jani.nikula, airlied, intel-gfx, dri-devel, linux-kernel
  Cc: taesoo, yeongjin.jang, insu, changwoo, Insu Yun

Since devm_kzalloc can be failed, it needs to be checked
if not, NULL dereference could be happened.

Signed-off-by: Insu Yun <wuninsu@gmail.com>
---
 drivers/gpu/drm/i915/intel_dsi_panel_vbt.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
index a5e99ac..aa1f7bc 100644
--- a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
+++ b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
@@ -666,6 +666,8 @@ struct drm_panel *vbt_panel_init(struct intel_dsi *intel_dsi, u16 panel_id)
 
 	/* This is cheating a bit with the cleanup. */
 	vbt_panel = devm_kzalloc(dev->dev, sizeof(*vbt_panel), GFP_KERNEL);
+	if (!vbt_panel)
+		return NULL;
 
 	vbt_panel->intel_dsi = intel_dsi;
 	drm_panel_init(&vbt_panel->panel);
-- 
1.9.1


^ permalink raw reply related	[flat|nested] 90+ messages in thread
* [PATCH] drm/i915: Fix whitespace (trivial)
@ 2015-12-29 22:20 Ben Widawsky
  2015-12-30  7:20 ` ✗ warning: Fi.CI.BAT Patchwork
  0 siblings, 1 reply; 90+ messages in thread
From: Ben Widawsky @ 2015-12-29 22:20 UTC (permalink / raw)
  To: Intel GFX; +Cc: Ben Widawsky

Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com>
---
 drivers/gpu/drm/i915/intel_lrc.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index ca5c0e8..973487a 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -538,8 +538,8 @@ void intel_lrc_irq_handler(struct intel_engine_cs *ring)
 				WARN(1, "Preemption without Lite Restore\n");
 		}
 
-		 if ((status & GEN8_CTX_STATUS_ACTIVE_IDLE) ||
-		     (status & GEN8_CTX_STATUS_ELEMENT_SWITCH)) {
+		if ((status & GEN8_CTX_STATUS_ACTIVE_IDLE) ||
+		    (status & GEN8_CTX_STATUS_ELEMENT_SWITCH)) {
 			if (execlists_check_remove_request(ring, status_id))
 				submit_contexts++;
 		}
-- 
2.6.4

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http://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 90+ messages in thread
* [PATCH] drm/i915: Hold a RPM reference during i915_driver_unload
@ 2015-12-29 10:55 Gabriel Feceoru
  2015-12-29 12:32 ` ✗ warning: Fi.CI.BAT Patchwork
  2015-12-29 12:40 ` Patchwork
  0 siblings, 2 replies; 90+ messages in thread
From: Gabriel Feceoru @ 2015-12-29 10:55 UTC (permalink / raw)
  To: intel-gfx

This fixes an issue added with: "1f814da drm/i915: add support for checking
if we hold an RPM reference", noticed while running drv_module_reload_basic.

WARNING: CPU: 1 PID: 2032 at drivers/gpu/drm/i915/intel_drv.h:1446 gen6_read32+0x1ca/0x1e0 [i915]()
[  138.682686] RPM wakelock ref not held during HW access
[  138.682687] Modules linked in:
[  138.682688]  i915(-) drm_kms_helper drm snd_hda_codec_hdmi snd_hda_codec_realtek snd_hda_codec_generic snd_hda_codec snd_hwdep x86_pkg_temp_thermal snd_hda_core i2c_algo_bit syscopyarea sysfillrect sysimgblt fb_sys_fops xhci_pci ehci_pci r8169 xhci_hcd mii ehci_hcd video [last unloaded: snd_hda_intel]
[  138.682699] CPU: 1 PID: 2032 Comm: rmmod Tainted: G        W       4.4.0-rc4+ #44
[  138.682701] Hardware name: Dell Inc. Inspiron 3847/088DT1       , BIOS A06 01/15/2015
[  138.682702]  ffffffffc03b6358 ffff880210d8ba58 ffffffff813e0c0f ffff880210d8baa0
[  138.682703]  ffff880210d8ba90 ffffffff8105f6a2 ffff8800daa40000 0000000000064400
[  138.682705]  0000000000000004 ffff880210d8bb9c ffff8800daa40000 ffff880210d8baf0
[  138.682706] Call Trace:
[  138.682710]  [<ffffffff813e0c0f>] dump_stack+0x44/0x55
[  138.682713]  [<ffffffff8105f6a2>] warn_slowpath_common+0x82/0xc0
[  138.682715]  [<ffffffff8105f72c>] warn_slowpath_fmt+0x4c/0x50
[  138.682725]  [<ffffffffc031aefc>] ? i915_gem_object_unpin_from_display_plane+0x1c/0x50 [i915]
[  138.682734]  [<ffffffffc0333b9a>] gen6_read32+0x1ca/0x1e0 [i915]
[  138.682737]  [<ffffffff8172c562>] ? mutex_lock+0x12/0x30
[  138.682747]  [<ffffffffc03715ca>] intel_ddi_get_hw_state+0x7a/0x180 [i915]
[  138.682758]  [<ffffffffc0355c88>] intel_connector_get_hw_state+0x28/0x30 [i915]
[  138.682767]  [<ffffffffc03543fc>] intel_atomic_commit+0xa9c/0x17e0 [i915]
[  138.682779]  [<ffffffffc00a7e8e>] ? drm_atomic_check_only+0x18e/0x590 [drm]
[  138.682786]  [<ffffffffc00a78cc>] ? drm_atomic_add_affected_connectors+0x8c/0xf0 [drm]
[  138.682792]  [<ffffffffc00a82c7>] drm_atomic_commit+0x37/0x60 [drm]
[  138.682797]  [<ffffffffc0163356>] drm_atomic_helper_set_config+0x76/0xb0 [drm_kms_helper]
[  138.682804]  [<ffffffffc00a696a>] ? drm_modeset_lock_all_ctx+0x9a/0xb0 [drm]
[  138.682809]  [<ffffffffc00979c2>] drm_mode_set_config_internal+0x62/0x100 [drm]
[  138.682814]  [<ffffffffc0097b48>] drm_framebuffer_remove+0xe8/0x120 [drm]
[  138.682826]  [<ffffffffc036bb4d>] intel_fbdev_fini+0x6d/0x90 [i915]
[  138.682838]  [<ffffffffc0396b9a>] i915_driver_unload+0x1a/0x290 [i915]
[  138.682844]  [<ffffffffc0090ff9>] drm_dev_unregister+0x29/0xb0 [drm]
[  138.682848]  [<ffffffffc0091673>] drm_put_dev+0x23/0x60 [drm]
[  138.682854]  [<ffffffffc02dc315>] i915_pci_remove+0x15/0x20 [i915]
[  138.682856]  [<ffffffff8141f409>] pci_device_remove+0x39/0xc0
[  138.682859]  [<ffffffff814e3d61>] __device_release_driver+0xa1/0x150
[  138.682860]  [<ffffffff814e4833>] driver_detach+0xa3/0xb0
[  138.682862]  [<ffffffff814e3825>] bus_remove_driver+0x55/0xd0
[  138.682864]  [<ffffffff814e4e2c>] driver_unregister+0x2c/0x50
[  138.682866]  [<ffffffff8141db31>] pci_unregister_driver+0x21/0x90
[  138.682871]  [<ffffffffc0092ec4>] drm_pci_exit+0x94/0xb0 [drm]
[  138.682883]  [<ffffffffc0397404>] i915_exit+0x20/0xc1c [i915]

Reported-by: Marius Vlad <marius.c.vlad@intel.com>
Signed-off-by: Gabriel Feceoru <gabriel.feceoru@intel.com>
---
 drivers/gpu/drm/i915/i915_dma.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index 988a380..08ad01f0 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -1136,6 +1136,8 @@ int i915_driver_unload(struct drm_device *dev)
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	int ret;
 
+	intel_runtime_pm_get(dev_priv);
+
 	intel_fbdev_fini(dev);
 
 	i915_audio_component_cleanup(dev_priv);
@@ -1143,6 +1145,7 @@ int i915_driver_unload(struct drm_device *dev)
 	ret = i915_gem_suspend(dev);
 	if (ret) {
 		DRM_ERROR("failed to idle hardware: %d\n", ret);
+		intel_runtime_pm_put(dev_priv);
 		return ret;
 	}
 
@@ -1221,6 +1224,9 @@ int i915_driver_unload(struct drm_device *dev)
 	kmem_cache_destroy(dev_priv->vmas);
 	kmem_cache_destroy(dev_priv->objects);
 	pci_dev_put(dev_priv->bridge_dev);
+
+	intel_runtime_pm_put(dev_priv);
+
 	kfree(dev_priv);
 
 	return 0;
-- 
1.9.1

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^ permalink raw reply related	[flat|nested] 90+ messages in thread
* [PATCH v2, 0/4] improve handling of the driver's default context
@ 2015-12-23 19:33 Dave Gordon
  2015-12-24  7:49 ` ✗ warning: Fi.CI.BAT Patchwork
  0 siblings, 1 reply; 90+ messages in thread
From: Dave Gordon @ 2015-12-23 19:33 UTC (permalink / raw)
  To: intel-gfx; +Cc: daniel.vetter

A reworking of the previous patchset, incorporating Daniel Vetter's
point that we don't need intel_context::file_priv and Chris Wilson's
wish to abolish engine::default_context.

Patch 1/4 starts the process by eliminating file_priv, which was only used
in one place. Patch 2/4 removes lots of references to default_context,
wherever it was used in a comparison. Patch 3/4 continues by removing
more references to default_context, wherever it was used for allocation.
And at the last, patch 4/4 replaces the remaining per-engine uses with a
single per-device pointer, thus finally making the refcounting sane.

Enjoy :)


_______________________________________________
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Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 90+ messages in thread
* [PATCH 1/2] drm/i915: fix get digital port issue in intel_audio
@ 2015-12-23  6:50 libin.yang
  2015-12-23  7:49 ` ✗ warning: Fi.CI.BAT Patchwork
  0 siblings, 1 reply; 90+ messages in thread
From: libin.yang @ 2015-12-23  6:50 UTC (permalink / raw)
  To: intel-gfx, conselvan2, tiwai, jani.nikula, ville.syrjala, daniel.vetter
  Cc: Libin Yang

From: Libin Yang <libin.yang@linux.intel.com>

For DP MST, use enc_to_mst(encoder)->primary to get intel_digital_port,
instead of using enc_to_dig_port(encoder).

Signed-off-by: Libin Yang <libin.yang@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_audio.c | 21 +++++++++++++++++----
 1 file changed, 17 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_audio.c b/drivers/gpu/drm/i915/intel_audio.c
index 31f6d21..431487a0 100644
--- a/drivers/gpu/drm/i915/intel_audio.c
+++ b/drivers/gpu/drm/i915/intel_audio.c
@@ -187,6 +187,16 @@ static bool intel_eld_uptodate(struct drm_connector *connector,
 	return true;
 }
 
+static struct intel_digital_port *
+intel_encoder_to_dig_port(struct intel_encoder *intel_encoder)
+{
+	struct drm_encoder *encoder = &intel_encoder->base;
+
+	if (intel_encoder->type == INTEL_OUTPUT_DP_MST)
+		return enc_to_mst(encoder)->primary;
+	return enc_to_dig_port(encoder);
+}
+
 static void g4x_audio_codec_disable(struct intel_encoder *encoder)
 {
 	struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
@@ -286,7 +296,7 @@ static void hsw_audio_codec_enable(struct drm_connector *connector,
 	struct i915_audio_component *acomp = dev_priv->audio_component;
 	const uint8_t *eld = connector->eld;
 	struct intel_digital_port *intel_dig_port =
-		enc_to_dig_port(&encoder->base);
+		intel_encoder_to_dig_port(encoder);
 	enum port port = intel_dig_port->port;
 	uint32_t tmp;
 	int len, i;
@@ -500,7 +510,8 @@ void intel_audio_codec_enable(struct intel_encoder *intel_encoder)
 	struct drm_device *dev = encoder->dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct i915_audio_component *acomp = dev_priv->audio_component;
-	struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
+	struct intel_digital_port *intel_dig_port =
+		intel_encoder_to_dig_port(intel_encoder);
 	enum port port = intel_dig_port->port;
 
 	connector = drm_select_eld(encoder);
@@ -546,7 +557,8 @@ void intel_audio_codec_disable(struct intel_encoder *intel_encoder)
 	struct drm_device *dev = encoder->dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct i915_audio_component *acomp = dev_priv->audio_component;
-	struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
+	struct intel_digital_port *intel_dig_port =
+		intel_encoder_to_dig_port(intel_encoder);
 	enum port port = intel_dig_port->port;
 
 	if (dev_priv->display.audio_codec_disable)
@@ -724,7 +736,8 @@ static int i915_audio_component_get_eld(struct device *dev, int port,
 	/* intel_encoder might be NULL for DP MST */
 	if (intel_encoder) {
 		ret = 0;
-		intel_dig_port = enc_to_dig_port(&intel_encoder->base);
+		intel_dig_port =
+			intel_encoder_to_dig_port(intel_encoder);
 		*enabled = intel_dig_port->audio_connector != NULL;
 		if (*enabled) {
 			eld = intel_dig_port->audio_connector->eld;
-- 
1.9.1

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^ permalink raw reply related	[flat|nested] 90+ messages in thread
* [PATCH] drm/i915/bxt: Fix wm calculation for pixel format change
@ 2015-12-23  5:22 Nabendu Maiti
  2015-12-23  7:20 ` ✗ warning: Fi.CI.BAT Patchwork
  0 siblings, 1 reply; 90+ messages in thread
From: Nabendu Maiti @ 2015-12-23  5:22 UTC (permalink / raw)
  To: intel-gfx

Recalculate watermark when there is a change in pixel format.

Signed-off-by: Nabendu Maiti <nabendu.bikash.maiti@intel.com>
---
 drivers/gpu/drm/i915/intel_display.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 2d0b006..4bd5080 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -11819,6 +11819,7 @@ static bool intel_wm_need_update(struct drm_plane *plane,
 		return false;
 
 	if (cur->base.fb->modifier[0] != new->base.fb->modifier[0] ||
+	    cur->base.fb->pixel_format != new->base.fb->pixel_format ||
 	    cur->base.rotation != new->base.rotation ||
 	    drm_rect_width(&new->src) != drm_rect_width(&cur->src) ||
 	    drm_rect_height(&new->src) != drm_rect_height(&cur->src) ||
-- 
1.9.1

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^ permalink raw reply related	[flat|nested] 90+ messages in thread
* [PATCH] drm/i915: edp resume/On time optimization.
@ 2015-12-22  1:18 abhay.kumar
  2015-12-22  8:49 ` ✗ warning: Fi.CI.BAT Patchwork
  0 siblings, 1 reply; 90+ messages in thread
From: abhay.kumar @ 2015-12-22  1:18 UTC (permalink / raw)
  To: Intel-gfx

From: Abhay Kumar <abhay.kumar@intel.com>

Make resume/on codepath not to wait for panel_power_cycle_delay(t11_t12)
if this time is already spent in suspend/poweron time.

v2: Use CLOCK_BOOTTIME and remove jiffies for panel power cycle
    delay calculation(Ville).

Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Abhay Kumar <abhay.kumar@intel.com>
---
 drivers/gpu/drm/i915/intel_ddi.c |  3 +++
 drivers/gpu/drm/i915/intel_dp.c  | 22 ++++++++++++++--------
 drivers/gpu/drm/i915/intel_drv.h |  2 +-
 3 files changed, 18 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index e6408e5..480697d 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -2395,6 +2395,9 @@ static void intel_ddi_post_disable(struct intel_encoder *intel_encoder)
 		intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
 		intel_edp_panel_vdd_on(intel_dp);
 		intel_edp_panel_off(intel_dp);
+
+		/* storing panel power off time */
+		intel_dp->panel_power_off_time = ktime_get_with_offset(TK_OFFS_BOOT);
 	}
 
 	if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 796e3d3..c813605 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -38,7 +38,6 @@
 #include "intel_drv.h"
 #include <drm/i915_drm.h>
 #include "i915_drv.h"
-
 #define DP_LINK_CHECK_TIMEOUT	(10 * 1000)
 
 /* Compliance test status bits  */
@@ -1812,13 +1811,22 @@ static void wait_panel_off(struct intel_dp *intel_dp)
 
 static void wait_panel_power_cycle(struct intel_dp *intel_dp)
 {
+	ktime_t panel_power_on_time;
+	u32 panel_power_off_duration;
+
 	DRM_DEBUG_KMS("Wait for panel power cycle\n");
 
-	/* When we disable the VDD override bit last we have to do the manual
-	 * wait. */
-	wait_remaining_ms_from_jiffies(intel_dp->last_power_cycle,
-				       intel_dp->panel_power_cycle_delay);
+        /* take the diffrence of currrent time and panel power off time
+           and then make panel wait for t11_t12 if needed */
+	panel_power_on_time = ktime_get_with_offset(TK_OFFS_BOOT);
+	panel_power_off_duration = (panel_power_on_time.tv64 - intel_dp->panel_power_off_time.tv64);
+	panel_power_off_duration = panel_power_off_duration / 1000000;
 
+	/* When we disable the VDD override bit last we have to do the manual
+	 * wait */
+	if (panel_power_off_duration < intel_dp->panel_power_cycle_delay)
+		wait_remaining_ms_from_jiffies(jiffies,
+				       (intel_dp->panel_power_cycle_delay - panel_power_off_duration));
 	wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
 }
 
@@ -1969,7 +1977,7 @@ static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
 	I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
 
 	if ((pp & POWER_TARGET_ON) == 0)
-		intel_dp->last_power_cycle = jiffies;
+		intel_dp->panel_power_off_time = ktime_get_with_offset(TK_OFFS_BOOT);
 
 	power_domain = intel_display_port_aux_power_domain(intel_encoder);
 	intel_display_power_put(dev_priv, power_domain);
@@ -2118,7 +2126,6 @@ static void edp_panel_off(struct intel_dp *intel_dp)
 	I915_WRITE(pp_ctrl_reg, pp);
 	POSTING_READ(pp_ctrl_reg);
 
-	intel_dp->last_power_cycle = jiffies;
 	wait_panel_off(intel_dp);
 
 	/* We got a reference when we enabled the VDD. */
@@ -5122,7 +5129,6 @@ intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connect
 
 static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
 {
-	intel_dp->last_power_cycle = jiffies;
 	intel_dp->last_power_on = jiffies;
 	intel_dp->last_backlight_off = jiffies;
 }
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index d523ebb..84ad134 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -765,9 +765,9 @@ struct intel_dp {
 	int backlight_off_delay;
 	struct delayed_work panel_vdd_work;
 	bool want_panel_vdd;
-	unsigned long last_power_cycle;
 	unsigned long last_power_on;
 	unsigned long last_backlight_off;
+	ktime_t panel_power_off_time;
 
 	struct notifier_block edp_notifier;
 
-- 
1.9.1

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http://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 90+ messages in thread
* [PATCH] drm/i915: Drop ilk_wm_max_level()
@ 2015-12-21 19:32 Matt Roper
  2015-12-22  8:20 ` ✗ warning: Fi.CI.BAT Patchwork
  0 siblings, 1 reply; 90+ messages in thread
From: Matt Roper @ 2015-12-21 19:32 UTC (permalink / raw)
  To: intel-gfx

Storing the max_level in dev_priv as VLV/CHV already do is a bit simpler
than calling this standalone function, especially since some of the
callsites need to special-case the call to check whether they're running
on VLV/CHV.

This function was further confusing since it wasn't actually specific to
ILK-style platforms as its name implied (it was also used on Skylake and
would even be called on pre-ILK platforms via debugfs).  Aside from this
function, our watermark programming across various platform-types
doesn't really have any overlap.

Note that we do change debugfs behavior slightly with this patch;
i915_*_wm_latency files will all now appear empty on pre-ILK platforms
rather than showing two watermark levels of 0.

Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
 drivers/gpu/drm/i915/i915_debugfs.c | 18 ++-------------
 drivers/gpu/drm/i915/intel_pm.c     | 44 +++++++++++++++++--------------------
 2 files changed, 22 insertions(+), 40 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 0fc38bb..ae36656 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -4445,14 +4445,7 @@ static void wm_latency_show(struct seq_file *m, const uint16_t wm[8])
 {
 	struct drm_device *dev = m->private;
 	int level;
-	int num_levels;
-
-	if (IS_CHERRYVIEW(dev))
-		num_levels = 3;
-	else if (IS_VALLEYVIEW(dev))
-		num_levels = 1;
-	else
-		num_levels = ilk_wm_max_level(dev) + 1;
+	int num_levels = to_i915(dev)->wm.max_level + 1;
 
 	drm_modeset_lock_all(dev);
 
@@ -4560,18 +4553,11 @@ static ssize_t wm_latency_write(struct file *file, const char __user *ubuf,
 	struct seq_file *m = file->private_data;
 	struct drm_device *dev = m->private;
 	uint16_t new[8] = { 0 };
-	int num_levels;
+	int num_levels = to_i915(dev)->wm.max_level + 1;
 	int level;
 	int ret;
 	char tmp[32];
 
-	if (IS_CHERRYVIEW(dev))
-		num_levels = 3;
-	else if (IS_VALLEYVIEW(dev))
-		num_levels = 1;
-	else
-		num_levels = ilk_wm_max_level(dev) + 1;
-
 	if (len >= sizeof(tmp))
 		return -EINVAL;
 
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index b076580..71d814c 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -2027,7 +2027,7 @@ static void intel_read_wm_latency(struct drm_device *dev, uint16_t wm[8])
 	if (IS_GEN9(dev)) {
 		uint32_t val;
 		int ret, i;
-		int level, max_level = ilk_wm_max_level(dev);
+		int level, max_level = dev_priv->wm.max_level;
 
 		/* read the first set of memory latencies[0:3] */
 		val = 0; /* data0 to be programmed to 0 for first set */
@@ -2142,24 +2142,11 @@ static void intel_fixup_cur_wm_latency(struct drm_device *dev, uint16_t wm[5])
 		wm[3] *= 2;
 }
 
-int ilk_wm_max_level(const struct drm_device *dev)
-{
-	/* how many WM levels are we expecting */
-	if (INTEL_INFO(dev)->gen >= 9)
-		return 7;
-	else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
-		return 4;
-	else if (INTEL_INFO(dev)->gen >= 6)
-		return 3;
-	else
-		return 2;
-}
-
 static void intel_print_wm_latency(struct drm_device *dev,
 				   const char *name,
 				   const uint16_t wm[8])
 {
-	int level, max_level = ilk_wm_max_level(dev);
+	int level, max_level = to_i915(dev)->wm.max_level;
 
 	for (level = 0; level <= max_level; level++) {
 		unsigned int latency = wm[level];
@@ -2188,7 +2175,7 @@ static void intel_print_wm_latency(struct drm_device *dev,
 static bool ilk_increase_wm_latency(struct drm_i915_private *dev_priv,
 				    uint16_t wm[5], uint16_t min)
 {
-	int level, max_level = ilk_wm_max_level(dev_priv->dev);
+	int level, max_level = dev_priv->wm.max_level;
 
 	if (wm[0] >= min)
 		return false;
@@ -2242,6 +2229,13 @@ static void ilk_setup_wm_latency(struct drm_device *dev)
 
 	if (IS_GEN6(dev))
 		snb_wm_latency_quirk(dev);
+
+	if (IS_HASWELL(dev) || IS_BROADWELL(dev))
+		dev_priv->wm.max_level = 4;
+	else if (INTEL_INFO(dev)->gen >= 6)
+		dev_priv->wm.max_level = 3;
+	else
+		dev_priv->wm.max_level = 2;
 }
 
 static void skl_setup_wm_latency(struct drm_device *dev)
@@ -2250,6 +2244,8 @@ static void skl_setup_wm_latency(struct drm_device *dev)
 
 	intel_read_wm_latency(dev, dev_priv->wm.skl_latency);
 	intel_print_wm_latency(dev, "Gen9 Plane", dev_priv->wm.skl_latency);
+
+	dev_priv->wm.max_level = 7;
 }
 
 /* Compute new watermarks for the pipe */
@@ -2265,7 +2261,7 @@ static int ilk_compute_pipe_wm(struct intel_crtc *intel_crtc,
 	struct intel_plane_state *pristate = NULL;
 	struct intel_plane_state *sprstate = NULL;
 	struct intel_plane_state *curstate = NULL;
-	int level, max_level = ilk_wm_max_level(dev);
+	int level, max_level = dev_priv->wm.max_level;
 	/* LP0 watermark maximums depend on this pipe alone */
 	struct intel_wm_config config = {
 		.num_pipes_active = 1,
@@ -2389,7 +2385,7 @@ static void ilk_wm_merge(struct drm_device *dev,
 			 struct intel_pipe_wm *merged)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
-	int level, max_level = ilk_wm_max_level(dev);
+	int level, max_level = dev_priv->wm.max_level;
 	int last_enabled_level = max_level;
 
 	/* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */
@@ -2530,7 +2526,7 @@ static struct intel_pipe_wm *ilk_find_best_result(struct drm_device *dev,
 						  struct intel_pipe_wm *r1,
 						  struct intel_pipe_wm *r2)
 {
-	int level, max_level = ilk_wm_max_level(dev);
+	int level, max_level = to_i915(dev)->wm.max_level;
 	int level1 = 0, level2 = 0;
 
 	for (level = 1; level <= max_level; level++) {
@@ -3232,7 +3228,7 @@ static void skl_compute_pipe_wm(struct intel_crtc_state *cstate,
 {
 	struct drm_device *dev = cstate->base.crtc->dev;
 	const struct drm_i915_private *dev_priv = dev->dev_private;
-	int level, max_level = ilk_wm_max_level(dev);
+	int level, max_level = dev_priv->wm.max_level;
 
 	for (level = 0; level <= max_level; level++) {
 		skl_compute_wm_level(dev_priv, ddb, cstate,
@@ -3248,7 +3244,7 @@ static void skl_compute_wm_results(struct drm_device *dev,
 				   struct skl_wm_values *r,
 				   struct intel_crtc *intel_crtc)
 {
-	int level, max_level = ilk_wm_max_level(dev);
+	int level, max_level = to_i915(dev)->wm.max_level;
 	enum pipe pipe = intel_crtc->pipe;
 	uint32_t temp;
 	int i;
@@ -3317,7 +3313,7 @@ static void skl_write_wm_values(struct drm_i915_private *dev_priv,
 	struct intel_crtc *crtc;
 
 	for_each_intel_crtc(dev, crtc) {
-		int i, level, max_level = ilk_wm_max_level(dev);
+		int i, level, max_level = dev_priv->wm.max_level;
 		enum pipe pipe = crtc->pipe;
 
 		if (!new->dirty[pipe])
@@ -3711,7 +3707,7 @@ static void skl_pipe_wm_get_hw_state(struct drm_crtc *crtc)
 	int level, i, max_level;
 	uint32_t temp;
 
-	max_level = ilk_wm_max_level(dev);
+	max_level = dev_priv->wm.max_level;
 
 	hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
 
@@ -3801,7 +3797,7 @@ static void ilk_pipe_wm_get_hw_state(struct drm_crtc *crtc)
 		active->wm[0].cur_val = tmp & WM0_PIPE_CURSOR_MASK;
 		active->linetime = hw->wm_linetime[pipe];
 	} else {
-		int level, max_level = ilk_wm_max_level(dev);
+		int level, max_level = dev_priv->wm.max_level;
 
 		/*
 		 * For inactive pipes, all watermark levels
-- 
2.1.4

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^ permalink raw reply related	[flat|nested] 90+ messages in thread
* [PATCH] drm/i915/skl: Use proper plane dimensions for DDB and WM calculations
@ 2015-12-21 15:31 Matt Roper
  2015-12-21 17:20 ` ✗ warning: Fi.CI.BAT Patchwork
  0 siblings, 1 reply; 90+ messages in thread
From: Matt Roper @ 2015-12-21 15:31 UTC (permalink / raw)
  To: intel-gfx; +Cc: Ville Syrjälä, Kondapally, Kalyan

In commit

        commit 024c9045221fe45482863c47c4b4c47d37f97cbf
        Author: Matt Roper <matthew.d.roper@intel.com>
        Date:   Thu Sep 24 15:53:11 2015 -0700

            drm/i915/skl: Eliminate usage of pipe_wm_parameters from SKL-style WM (v4)

I fumbled while converting the dimensions stored in the plane_parameters
structure to the values stored in plane state and accidentally replaced
the plane dimensions with the pipe dimensions in both the DDB allocation
function and the WM calculation function.  On the DDB side this is
harmless since we effectively treat all of our non-cursor planes as
full-screen which may not be optimal, but generally won't cause any
problems either (and in 99% of the cases where there's no sprite plane
usage or primary plane windowing, there's no effect at all).  On the WM
calculation side there's more potential for this fumble to cause actual
problems since cursors also get miscalculated.

Cc: Ville Syrjälä <ville.syrjala@intel.com>
Cc: "Kondapally, Kalyan" <kalyan.kondapally@intel.com>
Cc: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 24 +++++++++++++-----------
 1 file changed, 13 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 8d0d6f5..f4d4cc7 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -2845,25 +2845,22 @@ skl_plane_relative_data_rate(const struct intel_crtc_state *cstate,
 			     const struct drm_plane_state *pstate,
 			     int y)
 {
-	struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
+	struct intel_plane_state *intel_pstate = to_intel_plane_state(pstate);
 	struct drm_framebuffer *fb = pstate->fb;
+	unsigned w = drm_rect_width(&intel_pstate->dst);
+	unsigned h = drm_rect_height(&intel_pstate->dst);
 
 	/* for planar format */
 	if (fb->pixel_format == DRM_FORMAT_NV12) {
 		if (y)  /* y-plane data rate */
-			return intel_crtc->config->pipe_src_w *
-				intel_crtc->config->pipe_src_h *
-				drm_format_plane_cpp(fb->pixel_format, 0);
+			return w * h * drm_format_plane_cpp(fb->pixel_format, 0);
 		else    /* uv-plane data rate */
-			return (intel_crtc->config->pipe_src_w/2) *
-				(intel_crtc->config->pipe_src_h/2) *
+			return (w/2) * (h/2) *
 				drm_format_plane_cpp(fb->pixel_format, 1);
 	}
 
 	/* for packed formats */
-	return intel_crtc->config->pipe_src_w *
-		intel_crtc->config->pipe_src_h *
-		drm_format_plane_cpp(fb->pixel_format, 0);
+	return w * h * drm_format_plane_cpp(fb->pixel_format, 0);
 }
 
 /*
@@ -2960,6 +2957,8 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
 	 * FIXME: we may not allocate every single block here.
 	 */
 	total_data_rate = skl_get_total_relative_data_rate(cstate);
+	if (!total_data_rate)
+		return;
 
 	start = alloc->start;
 	for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
@@ -3093,12 +3092,15 @@ static bool skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
 {
 	struct drm_plane *plane = &intel_plane->base;
 	struct drm_framebuffer *fb = plane->state->fb;
+	struct intel_plane_state *intel_pstate =
+		to_intel_plane_state(plane->state);
 	uint32_t latency = dev_priv->wm.skl_latency[level];
 	uint32_t method1, method2;
 	uint32_t plane_bytes_per_line, plane_blocks_per_line;
 	uint32_t res_blocks, res_lines;
 	uint32_t selected_result;
 	uint8_t bytes_per_pixel;
+	unsigned w = drm_rect_width(&intel_pstate->dst);
 
 	if (latency == 0 || !cstate->base.active || !fb)
 		return false;
@@ -3109,12 +3111,12 @@ static bool skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
 				 latency);
 	method2 = skl_wm_method2(skl_pipe_pixel_rate(cstate),
 				 cstate->base.adjusted_mode.crtc_htotal,
-				 cstate->pipe_src_w,
+				 w,
 				 bytes_per_pixel,
 				 fb->modifier[0],
 				 latency);
 
-	plane_bytes_per_line = cstate->pipe_src_w * bytes_per_pixel;
+	plane_bytes_per_line = w * bytes_per_pixel;
 	plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
 
 	if (fb->modifier[0] == I915_FORMAT_MOD_Y_TILED ||
-- 
2.1.4

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^ permalink raw reply related	[flat|nested] 90+ messages in thread
* [PATCH 00/15] drm/i915/bios: mipi sequence block v3, etc.
@ 2015-12-21 13:10 Jani Nikula
  2015-12-21 13:27 ` ✗ warning: Fi.CI.BAT Patchwork
  0 siblings, 1 reply; 90+ messages in thread
From: Jani Nikula @ 2015-12-21 13:10 UTC (permalink / raw)
  To: intel-gfx; +Cc: jani.nikula, Deepak M

Hi all, this is follow-up to my earlier opregion/vbt series [1]. This
covers patches 1 and 7 of Deepak's series [2], but does quite a bunch of
rework to make everything as neat as it can be given the spec. There's
also some generic VBT documentation.

Unfortunately I haven't been able to test this on a machine that
actually has MIPI sequence block v3. However most of the series does not
touch that yet.

BR,
Jani.


[1] http://mid.gmane.org/cover.1450089383.git.jani.nikula@intel.com
[2] http://mid.gmane.org/1448923632-16760-1-git-send-email-m.deepak@intel.com

Jani Nikula (14):
  drm/i915/bios: add proper documentation for the Video BIOS Table (VBT)
  drm/i915/bios: fix header define name for intel_bios.h
  drm/i915/bios: split the MIPI DSI VBT block parsing to two
  drm/i915/bios: have get_blocksize() support MIPI sequence block v3+
  drm/i915/bios: abstract finding the panel sequence block
  drm/i915/bios: rewrite sequence block parsing
  drm/i915/dsi: be defensive about out of bounds sequence id
  drm/i915/dsi: be defensive about out of bounds operation byte
  drm/i915/bios: interpret the i2c element
  drm/i915/bios: add sequences for MIPI sequence block v2
  drm/i915/bios: add defines for v3 sequence block
  drm/i915/bios: add support for MIPI sequence block v3
  drm/i915/dsi: skip unknown elements for sequence block v3+
  drm/i915/dsi: reduce tedious repetition

vkorjani (1):
  drm/i915: Adding the parsing logic for the i2c element

 Documentation/DocBook/gpu.tmpl             |   6 +
 drivers/gpu/drm/i915/i915_drv.h            |   2 +-
 drivers/gpu/drm/i915/intel_bios.c          | 376 +++++++++++++++++------------
 drivers/gpu/drm/i915/intel_bios.h          |  60 +++--
 drivers/gpu/drm/i915/intel_dsi_panel_vbt.c | 198 +++++++++------
 5 files changed, 397 insertions(+), 245 deletions(-)

-- 
2.1.4

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^ permalink raw reply	[flat|nested] 90+ messages in thread
* [PATCH] drm/i915: Handle PipeC fused off on HSW
@ 2015-12-21 11:57 Gabriel Feceoru
  2015-12-21 13:13 ` ✗ warning: Fi.CI.BAT Patchwork
                   ` (2 more replies)
  0 siblings, 3 replies; 90+ messages in thread
From: Gabriel Feceoru @ 2015-12-21 11:57 UTC (permalink / raw)
  To: intel-gfx

On some HSW boards all pipeC tests fail with various dmesg errors.
This seems to be caused by Pipe C beeing disabled in FUSE_STRAP and
thus reading back the PIPECONF register is always zero.

Fixed by adjusting pipe_count to 2 and thus the pipeC igt tests will
be skipped.

Signed-off-by: Gabriel Feceoru <gabriel.feceoru@intel.com>
---
 drivers/gpu/drm/i915/i915_dma.c | 3 +++
 drivers/gpu/drm/i915/i915_reg.h | 1 +
 2 files changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index 988a380..130a496 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -813,6 +813,9 @@ static void intel_device_info_runtime_init(struct drm_device *dev)
 		     !(sfuse_strap & SFUSE_STRAP_FUSE_LOCK))) {
 			DRM_INFO("Display fused off, disabling\n");
 			info->num_pipes = 0;
+		} else if (I915_READ(FUSE_STRAP) & HSW_PIPE_C_DISABLE) {
+			DRM_INFO("PipeC fused off\n");
+			info->num_pipes = 2;
 		}
 	}
 
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 007ae83..0432a5f 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5940,6 +5940,7 @@ enum skl_disp_power_wells {
 #define  ILK_INTERNAL_GRAPHICS_DISABLE	(1 << 31)
 #define  ILK_INTERNAL_DISPLAY_DISABLE	(1 << 30)
 #define  ILK_DISPLAY_DEBUG_DISABLE	(1 << 29)
+#define  HSW_PIPE_C_DISABLE		(1 << 28)
 #define  ILK_HDCP_DISABLE		(1 << 25)
 #define  ILK_eDP_A_DISABLE		(1 << 24)
 #define  HSW_CDCLK_LIMIT		(1 << 24)
-- 
1.9.1

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^ permalink raw reply related	[flat|nested] 90+ messages in thread
* [PATCH v5 0/2] drm/i915: Disable link training optimization if DP config has changed
@ 2015-12-21 11:39 Mika Kahola
  2015-12-21 12:14 ` ✗ warning: Fi.CI.BAT Patchwork
                   ` (2 more replies)
  0 siblings, 3 replies; 90+ messages in thread
From: Mika Kahola @ 2015-12-21 11:39 UTC (permalink / raw)
  To: intel-gfx

These two patches are fixes for DP link trainging failures and flickering issues
reported by 

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91393

Mika Kahola (2):
  drm/i915: Disable fast link training if DP config changes
  drm/i915: Check DP no aux transaction bit on link training

 drivers/gpu/drm/i915/intel_dp.c               |  7 ++++++-
 drivers/gpu/drm/i915/intel_dp_link_training.c | 22 ++++++++++++++++++++++
 drivers/gpu/drm/i915/intel_drv.h              |  1 +
 3 files changed, 29 insertions(+), 1 deletion(-)

-- 
1.9.1

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^ permalink raw reply	[flat|nested] 90+ messages in thread
* [PATCH] drm/i915: Acquire RPM wakeref for KMS atomic commit
@ 2015-12-19  9:58 Chris Wilson
  2015-12-19 10:49 ` ✗ warning: Fi.CI.BAT Patchwork
  2015-12-21 10:37 ` Patchwork
  0 siblings, 2 replies; 90+ messages in thread
From: Chris Wilson @ 2015-12-19  9:58 UTC (permalink / raw)
  To: intel-gfx

Once all the preparations are complete, we are ready to write the
modesetting to the hardware. During this phase, we will be making lots
of HW register access, so take a top level wakeref to prevent an
unwarranted rpm suspend cycle mid-commit. Lower level functions should
be waking the individual power wells as required.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=93439
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Imre Deak <imre.deak@intel.com>
---
 drivers/gpu/drm/i915/intel_display.c | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index abd2d2944022..60451c3932db 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -13470,6 +13470,13 @@ static int intel_atomic_commit(struct drm_device *dev,
 	drm_atomic_helper_swap_state(dev, state);
 	dev_priv->wm.config = to_intel_atomic_state(state)->wm_config;
 
+	/* Take a rpm wakeref for the duration of the commit. Lower level
+	 * functions should be acquiring the power wells for their own use,
+	 * we take this toplevel reference to prevent rpm suspend cycles
+	 * mid-commit.
+	 */
+	intel_runtime_pm_get(dev_priv);
+
 	for_each_crtc_in_state(state, crtc, crtc_state, i) {
 		struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 
@@ -13558,6 +13565,8 @@ static int intel_atomic_commit(struct drm_device *dev,
 	if (any_ms)
 		intel_modeset_check_state(dev, state);
 
+	intel_runtime_pm_put(dev_priv);
+
 	drm_atomic_state_free(state);
 
 	return 0;
-- 
2.6.4

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^ permalink raw reply related	[flat|nested] 90+ messages in thread
* [PATCH] drm/fb-helper: Use proper plane mask for fb cleanup
@ 2015-12-19  1:27 Matt Roper
  2015-12-19 10:20 ` ✗ warning: Fi.CI.BAT Patchwork
  0 siblings, 1 reply; 90+ messages in thread
From: Matt Roper @ 2015-12-19  1:27 UTC (permalink / raw)
  To: dri-devel; +Cc: intel-gfx, Daniel Vetter

pan_display_atomic() calls drm_atomic_clean_old_fb() to sanitize the
legacy FB fields (plane->fb and plane->old_fb).  However it was building
the plane mask to pass to this function incorrectly (the bitwise OR was
using plane indices rather than plane masks).  The end result was that
sometimes the legacy pointers would become out of sync with the atomic
pointers.  If another operation tried to re-set the same FB onto the
plane, we might end up with the pointers back in sync, but improper
reference counts, which would eventually lead to system crashes when we
accessed a pointer to a prematurely-destroyed FB.

The cause here was a very subtle bug introduced in commit:

        commit 07d3bad6c1210bd21e85d084807ef4ee4ac43a78
        Author: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
        Date:   Wed Nov 11 11:29:11 2015 +0100

            drm/core: Fix old_fb handling in pan_display_atomic.

I found the crashes were most easily reproduced (on i915 at least) by
starting X and then VT switching to a VT that wasn't running a console
instance...the sequence of vt/fbcon entries that happen in that case
trigger a reference count mismatch and crash the system.

Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=93313
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
 drivers/gpu/drm/drm_fb_helper.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/drm_fb_helper.c b/drivers/gpu/drm/drm_fb_helper.c
index 69cbab5..1e103c4 100644
--- a/drivers/gpu/drm/drm_fb_helper.c
+++ b/drivers/gpu/drm/drm_fb_helper.c
@@ -1251,7 +1251,7 @@ retry:
 			goto fail;
 
 		plane = mode_set->crtc->primary;
-		plane_mask |= drm_plane_index(plane);
+		plane_mask |= (1 << drm_plane_index(plane));
 		plane->old_fb = plane->fb;
 	}
 
-- 
2.1.4

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^ permalink raw reply related	[flat|nested] 90+ messages in thread
* [PATCH v2] drm/i915/skl: Increase ddb blocks to support large cursor sizes
@ 2015-12-18 23:58 Radhakrishna Sripada
  2015-12-19  9:49 ` ✗ warning: Fi.CI.BAT Patchwork
  0 siblings, 1 reply; 90+ messages in thread
From: Radhakrishna Sripada @ 2015-12-18 23:58 UTC (permalink / raw)
  To: intel-gfx; +Cc: drm-intel-fixes, Kalyan Kondapally

Original value of 32 blocks is not sufficient when using cursor size of
256x256 causing FIFO underruns when the reworked wm
caluclations in

commit 024c9045221fe45482863c47c4b4c47d37f97cbf
Author: Matt Roper <matthew.d.roper@intel.com>
Date:   Thu Sep 24 15:53:11 2015 -0700

    drm/i915/skl: Eliminate usage of pipe_wm_parameters from SKL-style WM (v4)

are used. Increasing the number of blocks to 52 to make cursor plane tolerate
SAGV block time for the maximum possible cursor size.

v2: Included Matt's suggestion, bumping up the no of blocks in multi-pipe case
to 16.

Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Signed-off-by: Kalyan Kondapally <kalyan.kondapally@intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index d385d99..c5ba4e5 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -2802,9 +2802,9 @@ skl_ddb_get_pipe_allocation_limits(struct drm_device *dev,
 static unsigned int skl_cursor_allocation(const struct intel_wm_config *config)
 {
 	if (config->num_pipes_active == 1)
-		return 32;
+		return 52;
 
-	return 8;
+	return 16;
 }
 
 static void skl_ddb_entry_init_from_hw(struct skl_ddb_entry *entry, u32 reg)
-- 
1.9.1

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^ permalink raw reply related	[flat|nested] 90+ messages in thread
* [PATCH v2 0/5] Add GuC ADS (Addition Data Structure)
@ 2015-12-18 20:00 yu.dai
  2015-12-19  8:49 ` ✗ warning: Fi.CI.BAT Patchwork
  0 siblings, 1 reply; 90+ messages in thread
From: yu.dai @ 2015-12-18 20:00 UTC (permalink / raw)
  To: intel-gfx

From: Alex Dai <yu.dai@intel.com>

The GuC firmware uses this for various purposes. The ADS itself is a chunk of
memory created by driver to share with GuC. This series creates the GuC ADS
object and setup some basic settings for it.

This version addresses some comments from Chris W. Tidy up some code; replace
kmap_atomic by kmap etc.

Alex Dai (4):
  drm/i915/guc: Add GuC ADS (Addition Data Structure) - allocation
  drm/i915/guc: Add GuC ADS - scheduler policies
  drm/i915/guc: Add GuC ADS - MMIO reg state
  drm/i915/guc: Add GuC ADS - enabling ADS

Dave Gordon (1):
  drm/i915/guc: Expose (intel)_lr_context_size()

 drivers/gpu/drm/i915/i915_guc_reg.h        |   1 +
 drivers/gpu/drm/i915/i915_guc_submission.c |  95 ++++++++++++++++++++++++
 drivers/gpu/drm/i915/intel_guc.h           |   2 +
 drivers/gpu/drm/i915/intel_guc_fwif.h      | 113 ++++++++++++++++++++++++++++-
 drivers/gpu/drm/i915/intel_guc_loader.c    |   7 ++
 drivers/gpu/drm/i915/intel_lrc.c           |   4 +-
 drivers/gpu/drm/i915/intel_lrc.h           |   1 +
 7 files changed, 220 insertions(+), 3 deletions(-)

-- 
2.5.0

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^ permalink raw reply	[flat|nested] 90+ messages in thread
* [PATCH] drm/i915/skl: Default to noncoherent access up to F0
@ 2015-12-18 14:14 Mika Kuoppala
  2015-12-18 14:49 ` ✗ warning: Fi.CI.BAT Patchwork
  0 siblings, 1 reply; 90+ messages in thread
From: Mika Kuoppala @ 2015-12-18 14:14 UTC (permalink / raw)
  To: intel-gfx; +Cc: Ben Widawsky

The workarounds for disabling hdc invalidation and also forcing
context to be non coherent, are advised to be used up until rev D0.

However as it was found that rev F0, without the
WaForceEnableNonCoherent might system hang if the mesa
tried to use coherent mode.

As these two workarounds are about non coherent access, are
grouped in scope and they point the same HSD, increase the
scope of both to set default behaviour to non coherent access.

References: HSD: gen9lp/2131413
References: http://lists.freedesktop.org/archives/mesa-dev/2015-November/101515.html
Cc: Ben Widawsky <benjamin.widawsky@intel.com>
Cc: Francisco Jerez <currojerez@riseup.net>
Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
---
 drivers/gpu/drm/i915/intel_ringbuffer.c | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index eefce9a3e9c8..339701d7a9a5 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -1018,10 +1018,6 @@ static int skl_init_workarounds(struct intel_engine_cs *ring)
 		return ret;
 
 	if (IS_SKL_REVID(dev, 0, SKL_REVID_D0)) {
-		/* WaDisableHDCInvalidation:skl */
-		I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) |
-			   BDW_DISABLE_HDC_INVALIDATION);
-
 		/* WaDisableChickenBitTSGBarrierAckForFFSliceCS:skl */
 		I915_WRITE(FF_SLICE_CS_CHICKEN2,
 			   _MASKED_BIT_ENABLE(GEN9_TSG_BARRIER_ACK_DISABLE));
@@ -1046,7 +1042,7 @@ static int skl_init_workarounds(struct intel_engine_cs *ring)
 		WA_SET_BIT_MASKED(HIZ_CHICKEN,
 				  BDW_HIZ_POWER_COMPILER_CLOCK_GATING_DISABLE);
 
-	if (IS_SKL_REVID(dev, 0, SKL_REVID_D0)) {
+	if (IS_SKL_REVID(dev, 0, SKL_REVID_F0)) {
 		/*
 		 *Use Force Non-Coherent whenever executing a 3D context. This
 		 * is a workaround for a possible hang in the unlikely event
@@ -1055,6 +1051,10 @@ static int skl_init_workarounds(struct intel_engine_cs *ring)
 		/* WaForceEnableNonCoherent:skl */
 		WA_SET_BIT_MASKED(HDC_CHICKEN0,
 				  HDC_FORCE_NON_COHERENT);
+
+		/* WaDisableHDCInvalidation:skl */
+		I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) |
+			   BDW_DISABLE_HDC_INVALIDATION);
 	}
 
 	/* WaBarrierPerformanceFixDisable:skl */
-- 
2.5.0

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^ permalink raw reply related	[flat|nested] 90+ messages in thread
* [PATCH v3 0/2] Optimize WARN_ON macros
@ 2015-12-18 12:27 Joonas Lahtinen
  2015-12-18 13:20 ` ✗ warning: Fi.CI.BAT Patchwork
  2015-12-18 14:00 ` Patchwork
  0 siblings, 2 replies; 90+ messages in thread
From: Joonas Lahtinen @ 2015-12-18 12:27 UTC (permalink / raw)
  To: Intel graphics driver community testing & development

v3:
- Fixed potential OOPS scenario with modulo in condition
  (Dave Gordon)

Joonas Lahtinen (2):
  drm/i915: Simplify _STATE_ debug macros
  drm/i915: Compile-time concatenate WARN_ON macro strings

 drivers/gpu/drm/i915/i915_drv.h | 23 ++++++-----------------
 1 file changed, 6 insertions(+), 17 deletions(-)

-- 
2.4.3

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^ permalink raw reply	[flat|nested] 90+ messages in thread
* [PATCH v2 0/2] Optimize WARN_ON macros
@ 2015-12-18 11:17 Joonas Lahtinen
  2015-12-18 12:14 ` ✗ warning: Fi.CI.BAT Patchwork
  2015-12-18 13:59 ` Patchwork
  0 siblings, 2 replies; 90+ messages in thread
From: Joonas Lahtinen @ 2015-12-18 11:17 UTC (permalink / raw)
  To: Intel graphics driver community testing & development

Joonas Lahtinen (2):
  drm/i915: Simplify _STATE_ debug macros
  drm/i915: Compile-time concatenate WARN_ON macro strings

 drivers/gpu/drm/i915/i915_drv.h | 23 ++++++-----------------
 1 file changed, 6 insertions(+), 17 deletions(-)

-- 
2.4.3

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^ permalink raw reply	[flat|nested] 90+ messages in thread
* [PATCH 0/2] Optimize WARN_ON macros
@ 2015-12-18 10:39 Joonas Lahtinen
  2015-12-18 11:20 ` ✗ warning: Fi.CI.BAT Patchwork
  0 siblings, 1 reply; 90+ messages in thread
From: Joonas Lahtinen @ 2015-12-18 10:39 UTC (permalink / raw)
  To: Intel graphics driver community testing & development

Joonas Lahtinen (2):
  drm/i915: Simplify _STATE_ debug macros
  drm/i915: Compile time concatenate WARN_ON macro strings

 drivers/gpu/drm/i915/i915_drv.h | 23 ++++++-----------------
 1 file changed, 6 insertions(+), 17 deletions(-)

-- 
2.4.3

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^ permalink raw reply	[flat|nested] 90+ messages in thread
* [PATCH] drm/i915/backlight: prefer dev_priv over dev pointer
@ 2015-12-18  8:51 Jani Nikula
  2015-12-18  9:49 ` ✗ warning: Fi.CI.BAT Patchwork
  0 siblings, 1 reply; 90+ messages in thread
From: Jani Nikula @ 2015-12-18  8:51 UTC (permalink / raw)
  To: intel-gfx; +Cc: jani.nikula

Use dev_priv rather than dev pointer where applicable. Remove plenty of
unnecessary temp variables. No functional changes.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/intel_panel.c | 156 ++++++++++++++-----------------------
 1 file changed, 58 insertions(+), 98 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_panel.c b/drivers/gpu/drm/i915/intel_panel.c
index f5b4c98de608..21ee6477bf98 100644
--- a/drivers/gpu/drm/i915/intel_panel.c
+++ b/drivers/gpu/drm/i915/intel_panel.c
@@ -461,8 +461,7 @@ static inline u32 scale_hw_to_user(struct intel_connector *connector,
 static u32 intel_panel_compute_brightness(struct intel_connector *connector,
 					  u32 val)
 {
-	struct drm_device *dev = connector->base.dev;
-	struct drm_i915_private *dev_priv = dev->dev_private;
+	struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
 	struct intel_panel *panel = &connector->panel;
 
 	WARN_ON(panel->backlight.max == 0);
@@ -480,45 +479,40 @@ static u32 intel_panel_compute_brightness(struct intel_connector *connector,
 
 static u32 lpt_get_backlight(struct intel_connector *connector)
 {
-	struct drm_device *dev = connector->base.dev;
-	struct drm_i915_private *dev_priv = dev->dev_private;
+	struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
 
 	return I915_READ(BLC_PWM_PCH_CTL2) & BACKLIGHT_DUTY_CYCLE_MASK;
 }
 
 static u32 pch_get_backlight(struct intel_connector *connector)
 {
-	struct drm_device *dev = connector->base.dev;
-	struct drm_i915_private *dev_priv = dev->dev_private;
+	struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
 
 	return I915_READ(BLC_PWM_CPU_CTL) & BACKLIGHT_DUTY_CYCLE_MASK;
 }
 
 static u32 i9xx_get_backlight(struct intel_connector *connector)
 {
-	struct drm_device *dev = connector->base.dev;
-	struct drm_i915_private *dev_priv = dev->dev_private;
+	struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
 	struct intel_panel *panel = &connector->panel;
 	u32 val;
 
 	val = I915_READ(BLC_PWM_CTL) & BACKLIGHT_DUTY_CYCLE_MASK;
-	if (INTEL_INFO(dev)->gen < 4)
+	if (INTEL_INFO(dev_priv)->gen < 4)
 		val >>= 1;
 
 	if (panel->backlight.combination_mode) {
 		u8 lbpc;
 
-		pci_read_config_byte(dev->pdev, PCI_LBPC, &lbpc);
+		pci_read_config_byte(dev_priv->dev->pdev, PCI_LBPC, &lbpc);
 		val *= lbpc;
 	}
 
 	return val;
 }
 
-static u32 _vlv_get_backlight(struct drm_device *dev, enum pipe pipe)
+static u32 _vlv_get_backlight(struct drm_i915_private *dev_priv, enum pipe pipe)
 {
-	struct drm_i915_private *dev_priv = dev->dev_private;
-
 	if (WARN_ON(pipe != PIPE_A && pipe != PIPE_B))
 		return 0;
 
@@ -527,17 +521,16 @@ static u32 _vlv_get_backlight(struct drm_device *dev, enum pipe pipe)
 
 static u32 vlv_get_backlight(struct intel_connector *connector)
 {
-	struct drm_device *dev = connector->base.dev;
+	struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
 	enum pipe pipe = intel_get_pipe_from_connector(connector);
 
-	return _vlv_get_backlight(dev, pipe);
+	return _vlv_get_backlight(dev_priv, pipe);
 }
 
 static u32 bxt_get_backlight(struct intel_connector *connector)
 {
-	struct drm_device *dev = connector->base.dev;
+	struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
 	struct intel_panel *panel = &connector->panel;
-	struct drm_i915_private *dev_priv = dev->dev_private;
 
 	return I915_READ(BXT_BLC_PWM_DUTY(panel->backlight.controller));
 }
@@ -553,8 +546,7 @@ static u32 pwm_get_backlight(struct intel_connector *connector)
 
 static u32 intel_panel_get_backlight(struct intel_connector *connector)
 {
-	struct drm_device *dev = connector->base.dev;
-	struct drm_i915_private *dev_priv = dev->dev_private;
+	struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
 	struct intel_panel *panel = &connector->panel;
 	u32 val = 0;
 
@@ -573,16 +565,14 @@ static u32 intel_panel_get_backlight(struct intel_connector *connector)
 
 static void lpt_set_backlight(struct intel_connector *connector, u32 level)
 {
-	struct drm_device *dev = connector->base.dev;
-	struct drm_i915_private *dev_priv = dev->dev_private;
+	struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
 	u32 val = I915_READ(BLC_PWM_PCH_CTL2) & ~BACKLIGHT_DUTY_CYCLE_MASK;
 	I915_WRITE(BLC_PWM_PCH_CTL2, val | level);
 }
 
 static void pch_set_backlight(struct intel_connector *connector, u32 level)
 {
-	struct drm_device *dev = connector->base.dev;
-	struct drm_i915_private *dev_priv = dev->dev_private;
+	struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
 	u32 tmp;
 
 	tmp = I915_READ(BLC_PWM_CPU_CTL) & ~BACKLIGHT_DUTY_CYCLE_MASK;
@@ -591,8 +581,7 @@ static void pch_set_backlight(struct intel_connector *connector, u32 level)
 
 static void i9xx_set_backlight(struct intel_connector *connector, u32 level)
 {
-	struct drm_device *dev = connector->base.dev;
-	struct drm_i915_private *dev_priv = dev->dev_private;
+	struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
 	struct intel_panel *panel = &connector->panel;
 	u32 tmp, mask;
 
@@ -603,10 +592,10 @@ static void i9xx_set_backlight(struct intel_connector *connector, u32 level)
 
 		lbpc = level * 0xfe / panel->backlight.max + 1;
 		level /= lbpc;
-		pci_write_config_byte(dev->pdev, PCI_LBPC, lbpc);
+		pci_write_config_byte(dev_priv->dev->pdev, PCI_LBPC, lbpc);
 	}
 
-	if (IS_GEN4(dev)) {
+	if (IS_GEN4(dev_priv)) {
 		mask = BACKLIGHT_DUTY_CYCLE_MASK;
 	} else {
 		level <<= 1;
@@ -619,8 +608,7 @@ static void i9xx_set_backlight(struct intel_connector *connector, u32 level)
 
 static void vlv_set_backlight(struct intel_connector *connector, u32 level)
 {
-	struct drm_device *dev = connector->base.dev;
-	struct drm_i915_private *dev_priv = dev->dev_private;
+	struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
 	enum pipe pipe = intel_get_pipe_from_connector(connector);
 	u32 tmp;
 
@@ -633,8 +621,7 @@ static void vlv_set_backlight(struct intel_connector *connector, u32 level)
 
 static void bxt_set_backlight(struct intel_connector *connector, u32 level)
 {
-	struct drm_device *dev = connector->base.dev;
-	struct drm_i915_private *dev_priv = dev->dev_private;
+	struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
 	struct intel_panel *panel = &connector->panel;
 
 	I915_WRITE(BXT_BLC_PWM_DUTY(panel->backlight.controller), level);
@@ -663,8 +650,7 @@ intel_panel_actually_set_backlight(struct intel_connector *connector, u32 level)
 static void intel_panel_set_backlight(struct intel_connector *connector,
 				      u32 user_level, u32 user_max)
 {
-	struct drm_device *dev = connector->base.dev;
-	struct drm_i915_private *dev_priv = dev->dev_private;
+	struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
 	struct intel_panel *panel = &connector->panel;
 	u32 hw_level;
 
@@ -690,8 +676,7 @@ static void intel_panel_set_backlight(struct intel_connector *connector,
 void intel_panel_set_backlight_acpi(struct intel_connector *connector,
 				    u32 user_level, u32 user_max)
 {
-	struct drm_device *dev = connector->base.dev;
-	struct drm_i915_private *dev_priv = dev->dev_private;
+	struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
 	struct intel_panel *panel = &connector->panel;
 	enum pipe pipe = intel_get_pipe_from_connector(connector);
 	u32 hw_level;
@@ -726,8 +711,7 @@ void intel_panel_set_backlight_acpi(struct intel_connector *connector,
 
 static void lpt_disable_backlight(struct intel_connector *connector)
 {
-	struct drm_device *dev = connector->base.dev;
-	struct drm_i915_private *dev_priv = dev->dev_private;
+	struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
 	u32 tmp;
 
 	intel_panel_actually_set_backlight(connector, 0);
@@ -752,8 +736,7 @@ static void lpt_disable_backlight(struct intel_connector *connector)
 
 static void pch_disable_backlight(struct intel_connector *connector)
 {
-	struct drm_device *dev = connector->base.dev;
-	struct drm_i915_private *dev_priv = dev->dev_private;
+	struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
 	u32 tmp;
 
 	intel_panel_actually_set_backlight(connector, 0);
@@ -772,8 +755,7 @@ static void i9xx_disable_backlight(struct intel_connector *connector)
 
 static void i965_disable_backlight(struct intel_connector *connector)
 {
-	struct drm_device *dev = connector->base.dev;
-	struct drm_i915_private *dev_priv = dev->dev_private;
+	struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
 	u32 tmp;
 
 	intel_panel_actually_set_backlight(connector, 0);
@@ -784,8 +766,7 @@ static void i965_disable_backlight(struct intel_connector *connector)
 
 static void vlv_disable_backlight(struct intel_connector *connector)
 {
-	struct drm_device *dev = connector->base.dev;
-	struct drm_i915_private *dev_priv = dev->dev_private;
+	struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
 	enum pipe pipe = intel_get_pipe_from_connector(connector);
 	u32 tmp;
 
@@ -800,8 +781,7 @@ static void vlv_disable_backlight(struct intel_connector *connector)
 
 static void bxt_disable_backlight(struct intel_connector *connector)
 {
-	struct drm_device *dev = connector->base.dev;
-	struct drm_i915_private *dev_priv = dev->dev_private;
+	struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
 	struct intel_panel *panel = &connector->panel;
 	u32 tmp, val;
 
@@ -830,8 +810,7 @@ static void pwm_disable_backlight(struct intel_connector *connector)
 
 void intel_panel_disable_backlight(struct intel_connector *connector)
 {
-	struct drm_device *dev = connector->base.dev;
-	struct drm_i915_private *dev_priv = dev->dev_private;
+	struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
 	struct intel_panel *panel = &connector->panel;
 
 	if (!panel->backlight.present)
@@ -843,7 +822,7 @@ void intel_panel_disable_backlight(struct intel_connector *connector)
 	 * backlight. This will leave the backlight on unnecessarily when
 	 * another client is not activated.
 	 */
-	if (dev->switch_power_state == DRM_SWITCH_POWER_CHANGING) {
+	if (dev_priv->dev->switch_power_state == DRM_SWITCH_POWER_CHANGING) {
 		DRM_DEBUG_DRIVER("Skipping backlight disable on vga switch\n");
 		return;
 	}
@@ -860,8 +839,7 @@ void intel_panel_disable_backlight(struct intel_connector *connector)
 
 static void lpt_enable_backlight(struct intel_connector *connector)
 {
-	struct drm_device *dev = connector->base.dev;
-	struct drm_i915_private *dev_priv = dev->dev_private;
+	struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
 	struct intel_panel *panel = &connector->panel;
 	u32 pch_ctl1, pch_ctl2;
 
@@ -893,8 +871,7 @@ static void lpt_enable_backlight(struct intel_connector *connector)
 
 static void pch_enable_backlight(struct intel_connector *connector)
 {
-	struct drm_device *dev = connector->base.dev;
-	struct drm_i915_private *dev_priv = dev->dev_private;
+	struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
 	struct intel_panel *panel = &connector->panel;
 	enum pipe pipe = intel_get_pipe_from_connector(connector);
 	enum transcoder cpu_transcoder =
@@ -940,8 +917,7 @@ static void pch_enable_backlight(struct intel_connector *connector)
 
 static void i9xx_enable_backlight(struct intel_connector *connector)
 {
-	struct drm_device *dev = connector->base.dev;
-	struct drm_i915_private *dev_priv = dev->dev_private;
+	struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
 	struct intel_panel *panel = &connector->panel;
 	u32 ctl, freq;
 
@@ -958,7 +934,7 @@ static void i9xx_enable_backlight(struct intel_connector *connector)
 	ctl = freq << 17;
 	if (panel->backlight.combination_mode)
 		ctl |= BLM_LEGACY_MODE;
-	if (IS_PINEVIEW(dev) && panel->backlight.active_low_pwm)
+	if (IS_PINEVIEW(dev_priv) && panel->backlight.active_low_pwm)
 		ctl |= BLM_POLARITY_PNV;
 
 	I915_WRITE(BLC_PWM_CTL, ctl);
@@ -972,14 +948,13 @@ static void i9xx_enable_backlight(struct intel_connector *connector)
 	 * 855gm only, but checking for gen2 is safe, as 855gm is the only gen2
 	 * that has backlight.
 	 */
-	if (IS_GEN2(dev))
+	if (IS_GEN2(dev_priv))
 		I915_WRITE(BLC_HIST_CTL, BLM_HISTOGRAM_ENABLE);
 }
 
 static void i965_enable_backlight(struct intel_connector *connector)
 {
-	struct drm_device *dev = connector->base.dev;
-	struct drm_i915_private *dev_priv = dev->dev_private;
+	struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
 	struct intel_panel *panel = &connector->panel;
 	enum pipe pipe = intel_get_pipe_from_connector(connector);
 	u32 ctl, ctl2, freq;
@@ -1012,8 +987,7 @@ static void i965_enable_backlight(struct intel_connector *connector)
 
 static void vlv_enable_backlight(struct intel_connector *connector)
 {
-	struct drm_device *dev = connector->base.dev;
-	struct drm_i915_private *dev_priv = dev->dev_private;
+	struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
 	struct intel_panel *panel = &connector->panel;
 	enum pipe pipe = intel_get_pipe_from_connector(connector);
 	u32 ctl, ctl2;
@@ -1044,8 +1018,7 @@ static void vlv_enable_backlight(struct intel_connector *connector)
 
 static void bxt_enable_backlight(struct intel_connector *connector)
 {
-	struct drm_device *dev = connector->base.dev;
-	struct drm_i915_private *dev_priv = dev->dev_private;
+	struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
 	struct intel_panel *panel = &connector->panel;
 	enum pipe pipe = intel_get_pipe_from_connector(connector);
 	u32 pwm_ctl, val;
@@ -1102,8 +1075,7 @@ static void pwm_enable_backlight(struct intel_connector *connector)
 
 void intel_panel_enable_backlight(struct intel_connector *connector)
 {
-	struct drm_device *dev = connector->base.dev;
-	struct drm_i915_private *dev_priv = dev->dev_private;
+	struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
 	struct intel_panel *panel = &connector->panel;
 	enum pipe pipe = intel_get_pipe_from_connector(connector);
 
@@ -1278,8 +1250,7 @@ static u32 bxt_hz_to_pwm(struct intel_connector *connector, u32 pwm_freq_hz)
  */
 static u32 spt_hz_to_pwm(struct intel_connector *connector, u32 pwm_freq_hz)
 {
-	struct drm_device *dev = connector->base.dev;
-	struct drm_i915_private *dev_priv = dev->dev_private;
+	struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
 	u32 mul, clock;
 
 	if (I915_READ(SOUTH_CHICKEN1) & SPT_PWM_GRANULARITY)
@@ -1299,8 +1270,7 @@ static u32 spt_hz_to_pwm(struct intel_connector *connector, u32 pwm_freq_hz)
  */
 static u32 lpt_hz_to_pwm(struct intel_connector *connector, u32 pwm_freq_hz)
 {
-	struct drm_device *dev = connector->base.dev;
-	struct drm_i915_private *dev_priv = dev->dev_private;
+	struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
 	u32 mul, clock;
 
 	if (I915_READ(SOUTH_CHICKEN2) & LPT_PWM_GRANULARITY)
@@ -1393,8 +1363,7 @@ static u32 vlv_hz_to_pwm(struct intel_connector *connector, u32 pwm_freq_hz)
 
 static u32 get_backlight_max_vbt(struct intel_connector *connector)
 {
-	struct drm_device *dev = connector->base.dev;
-	struct drm_i915_private *dev_priv = dev->dev_private;
+	struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
 	struct intel_panel *panel = &connector->panel;
 	u16 pwm_freq_hz = dev_priv->vbt.backlight.pwm_freq_hz;
 	u32 pwm;
@@ -1427,8 +1396,7 @@ static u32 get_backlight_max_vbt(struct intel_connector *connector)
  */
 static u32 get_backlight_min_vbt(struct intel_connector *connector)
 {
-	struct drm_device *dev = connector->base.dev;
-	struct drm_i915_private *dev_priv = dev->dev_private;
+	struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
 	struct intel_panel *panel = &connector->panel;
 	int min;
 
@@ -1453,8 +1421,7 @@ static u32 get_backlight_min_vbt(struct intel_connector *connector)
 
 static int lpt_setup_backlight(struct intel_connector *connector, enum pipe unused)
 {
-	struct drm_device *dev = connector->base.dev;
-	struct drm_i915_private *dev_priv = dev->dev_private;
+	struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
 	struct intel_panel *panel = &connector->panel;
 	u32 pch_ctl1, pch_ctl2, val;
 
@@ -1483,8 +1450,7 @@ static int lpt_setup_backlight(struct intel_connector *connector, enum pipe unus
 
 static int pch_setup_backlight(struct intel_connector *connector, enum pipe unused)
 {
-	struct drm_device *dev = connector->base.dev;
-	struct drm_i915_private *dev_priv = dev->dev_private;
+	struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
 	struct intel_panel *panel = &connector->panel;
 	u32 cpu_ctl2, pch_ctl1, pch_ctl2, val;
 
@@ -1514,17 +1480,16 @@ static int pch_setup_backlight(struct intel_connector *connector, enum pipe unus
 
 static int i9xx_setup_backlight(struct intel_connector *connector, enum pipe unused)
 {
-	struct drm_device *dev = connector->base.dev;
-	struct drm_i915_private *dev_priv = dev->dev_private;
+	struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
 	struct intel_panel *panel = &connector->panel;
 	u32 ctl, val;
 
 	ctl = I915_READ(BLC_PWM_CTL);
 
-	if (IS_GEN2(dev) || IS_I915GM(dev) || IS_I945GM(dev))
+	if (IS_GEN2(dev_priv) || IS_I915GM(dev_priv) || IS_I945GM(dev_priv))
 		panel->backlight.combination_mode = ctl & BLM_LEGACY_MODE;
 
-	if (IS_PINEVIEW(dev))
+	if (IS_PINEVIEW(dev_priv))
 		panel->backlight.active_low_pwm = ctl & BLM_POLARITY_PNV;
 
 	panel->backlight.max = ctl >> 17;
@@ -1552,8 +1517,7 @@ static int i9xx_setup_backlight(struct intel_connector *connector, enum pipe unu
 
 static int i965_setup_backlight(struct intel_connector *connector, enum pipe unused)
 {
-	struct drm_device *dev = connector->base.dev;
-	struct drm_i915_private *dev_priv = dev->dev_private;
+	struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
 	struct intel_panel *panel = &connector->panel;
 	u32 ctl, ctl2, val;
 
@@ -1586,8 +1550,7 @@ static int i965_setup_backlight(struct intel_connector *connector, enum pipe unu
 
 static int vlv_setup_backlight(struct intel_connector *connector, enum pipe pipe)
 {
-	struct drm_device *dev = connector->base.dev;
-	struct drm_i915_private *dev_priv = dev->dev_private;
+	struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
 	struct intel_panel *panel = &connector->panel;
 	u32 ctl, ctl2, val;
 
@@ -1608,7 +1571,7 @@ static int vlv_setup_backlight(struct intel_connector *connector, enum pipe pipe
 
 	panel->backlight.min = get_backlight_min_vbt(connector);
 
-	val = _vlv_get_backlight(dev, pipe);
+	val = _vlv_get_backlight(dev_priv, pipe);
 	panel->backlight.level = intel_panel_compute_brightness(connector, val);
 
 	panel->backlight.enabled = (ctl2 & BLM_PWM_ENABLE) &&
@@ -1620,8 +1583,7 @@ static int vlv_setup_backlight(struct intel_connector *connector, enum pipe pipe
 static int
 bxt_setup_backlight(struct intel_connector *connector, enum pipe unused)
 {
-	struct drm_device *dev = connector->base.dev;
-	struct drm_i915_private *dev_priv = dev->dev_private;
+	struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
 	struct intel_panel *panel = &connector->panel;
 	u32 pwm_ctl, val;
 
@@ -1699,8 +1661,7 @@ static int pwm_setup_backlight(struct intel_connector *connector,
 
 int intel_panel_setup_backlight(struct drm_connector *connector, enum pipe pipe)
 {
-	struct drm_device *dev = connector->dev;
-	struct drm_i915_private *dev_priv = dev->dev_private;
+	struct drm_i915_private *dev_priv = to_i915(connector->dev);
 	struct intel_connector *intel_connector = to_intel_connector(connector);
 	struct intel_panel *panel = &intel_connector->panel;
 	int ret;
@@ -1755,36 +1716,35 @@ void intel_panel_destroy_backlight(struct drm_connector *connector)
 static void
 intel_panel_init_backlight_funcs(struct intel_panel *panel)
 {
-	struct intel_connector *intel_connector =
+	struct intel_connector *connector =
 		container_of(panel, struct intel_connector, panel);
-	struct drm_device *dev = intel_connector->base.dev;
-	struct drm_i915_private *dev_priv = dev->dev_private;
+	struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
 
-	if (IS_BROXTON(dev)) {
+	if (IS_BROXTON(dev_priv)) {
 		panel->backlight.setup = bxt_setup_backlight;
 		panel->backlight.enable = bxt_enable_backlight;
 		panel->backlight.disable = bxt_disable_backlight;
 		panel->backlight.set = bxt_set_backlight;
 		panel->backlight.get = bxt_get_backlight;
 		panel->backlight.hz_to_pwm = bxt_hz_to_pwm;
-	} else if (HAS_PCH_LPT(dev) || HAS_PCH_SPT(dev)) {
+	} else if (HAS_PCH_LPT(dev_priv) || HAS_PCH_SPT(dev_priv)) {
 		panel->backlight.setup = lpt_setup_backlight;
 		panel->backlight.enable = lpt_enable_backlight;
 		panel->backlight.disable = lpt_disable_backlight;
 		panel->backlight.set = lpt_set_backlight;
 		panel->backlight.get = lpt_get_backlight;
-		if (HAS_PCH_LPT(dev))
+		if (HAS_PCH_LPT(dev_priv))
 			panel->backlight.hz_to_pwm = lpt_hz_to_pwm;
 		else
 			panel->backlight.hz_to_pwm = spt_hz_to_pwm;
-	} else if (HAS_PCH_SPLIT(dev)) {
+	} else if (HAS_PCH_SPLIT(dev_priv)) {
 		panel->backlight.setup = pch_setup_backlight;
 		panel->backlight.enable = pch_enable_backlight;
 		panel->backlight.disable = pch_disable_backlight;
 		panel->backlight.set = pch_set_backlight;
 		panel->backlight.get = pch_get_backlight;
 		panel->backlight.hz_to_pwm = pch_hz_to_pwm;
-	} else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
+	} else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
 		if (dev_priv->vbt.has_mipi) {
 			panel->backlight.setup = pwm_setup_backlight;
 			panel->backlight.enable = pwm_enable_backlight;
@@ -1799,7 +1759,7 @@ intel_panel_init_backlight_funcs(struct intel_panel *panel)
 			panel->backlight.get = vlv_get_backlight;
 			panel->backlight.hz_to_pwm = vlv_hz_to_pwm;
 		}
-	} else if (IS_GEN4(dev)) {
+	} else if (IS_GEN4(dev_priv)) {
 		panel->backlight.setup = i965_setup_backlight;
 		panel->backlight.enable = i965_enable_backlight;
 		panel->backlight.disable = i965_disable_backlight;
-- 
2.1.4

_______________________________________________
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^ permalink raw reply related	[flat|nested] 90+ messages in thread
* [RFC][PATCH 0/6] Optionally display recurring warning messages
@ 2015-12-17 19:25 Joonas Lahtinen
  2015-12-18  8:20 ` ✗ warning: Fi.CI.BAT Patchwork
  0 siblings, 1 reply; 90+ messages in thread
From: Joonas Lahtinen @ 2015-12-17 19:25 UTC (permalink / raw)
  To: Intel graphics driver community testing & development

Wakeref series introduced multiple WARN_ONCE clauses which might be
triggered from several sources (hangcheck or cache flusing for example),
this series adds an i915.debug option to make them always WARN which is
useful in the CI.

Had to reorder i915_params to get rid of circular include dependency.

Compile tested, comments welcome.

Joonas Lahtinen (6):
  drm/i915: Compile time concatenate WARN_ON macro strings
  drm/i915: Decouple struct i915_params i915 into i915_params.h
  drm/i915: Reorder i915_params struct.
  drm/i915: Add i915.debug parameter
  drm/i915: Add helpers to reduce (repetitive) noise
  drm/i915: Use I915_WARN_RECUR for recurring warning messages

 drivers/gpu/drm/i915/i915_drv.h    | 75 +++++++++++++++++---------------------
 drivers/gpu/drm/i915/i915_params.c |  7 ++++
 drivers/gpu/drm/i915/i915_params.h | 69 +++++++++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/intel_drv.h   |  6 +--
 4 files changed, 112 insertions(+), 45 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/i915_params.h

-- 
2.4.3

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^ permalink raw reply	[flat|nested] 90+ messages in thread
* [PATCH] drm/i915: Hide one invalid cancellation bug in i915_switch_context()
@ 2015-12-17 18:18 Chris Wilson
  2015-12-18  7:49 ` ✗ warning: Fi.CI.BAT Patchwork
  2015-12-21 13:12 ` Patchwork
  0 siblings, 2 replies; 90+ messages in thread
From: Chris Wilson @ 2015-12-17 18:18 UTC (permalink / raw)
  To: intel-gfx; +Cc: Chris Wilson, Daniel Vetter, stable

As we add the VMA to the request early, it may be cancelled during
execbuf reservation. This will leave the context object pointing to a
dangling request; i915_wait_request() simply skips the wait and so we
may unbind the object whilst it is still active.

We can partially prevent such atrocity by doing the RCS context
initialisation earlier. This ensures that one callsite from blowing up
(and for igt this is a frequent culprit due to how the stressful batches
are submitted).

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Cc: stable@vger.kernel.org
---
 drivers/gpu/drm/i915/i915_gem_context.c | 29 +++++++++++++++++------------
 1 file changed, 17 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c
index 900ffd044db8..657686e6492f 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -657,7 +657,6 @@ static int do_switch(struct drm_i915_gem_request *req)
 	struct drm_i915_private *dev_priv = ring->dev->dev_private;
 	struct intel_context *from = ring->last_context;
 	u32 hw_flags = 0;
-	bool uninitialized = false;
 	int ret, i;
 
 	if (from != NULL && ring == &dev_priv->ring[RCS]) {
@@ -764,6 +763,15 @@ static int do_switch(struct drm_i915_gem_request *req)
 			to->remap_slice &= ~(1<<i);
 	}
 
+	if (!to->legacy_hw_ctx.initialized) {
+		if (ring->init_context) {
+			ret = ring->init_context(req);
+			if (ret)
+				goto unpin_out;
+		}
+		to->legacy_hw_ctx.initialized = true;
+	}
+
 	/* The backing object for the context is done after switching to the
 	 * *next* context. Therefore we cannot retire the previous context until
 	 * the next context has already started running. In fact, the below code
@@ -772,6 +780,14 @@ static int do_switch(struct drm_i915_gem_request *req)
 	 */
 	if (from != NULL) {
 		from->legacy_hw_ctx.rcs_state->base.read_domains = I915_GEM_DOMAIN_INSTRUCTION;
+		/* XXX Note very well this is dangerous!
+		 * We are pinning this object using this request as our
+		 * active reference. However, this request may yet be cancelled
+		 * during the execbuf dispatch, leaving us waiting on a
+		 * dangling request. Waiting upon this dangling request is
+		 * ignored, which means that we may unbind the context whilst
+		 * the GPU is still writing to the backing storage.
+		 */
 		i915_vma_move_to_active(i915_gem_obj_to_ggtt(from->legacy_hw_ctx.rcs_state), req);
 		/* As long as MI_SET_CONTEXT is serializing, ie. it flushes the
 		 * whole damn pipeline, we don't need to explicitly mark the
@@ -787,21 +803,10 @@ static int do_switch(struct drm_i915_gem_request *req)
 		i915_gem_context_unreference(from);
 	}
 
-	uninitialized = !to->legacy_hw_ctx.initialized;
-	to->legacy_hw_ctx.initialized = true;
-
 done:
 	i915_gem_context_reference(to);
 	ring->last_context = to;
 
-	if (uninitialized) {
-		if (ring->init_context) {
-			ret = ring->init_context(req);
-			if (ret)
-				DRM_ERROR("ring init context: %d\n", ret);
-		}
-	}
-
 	return 0;
 
 unpin_out:
-- 
2.6.4


^ permalink raw reply related	[flat|nested] 90+ messages in thread
* [PATCH] drm/i915: don't enable autosuspend on platforms without RPM support
@ 2015-12-17 17:04 Imre Deak
  2015-12-17 17:49 ` ✗ warning: Fi.CI.BAT Patchwork
  0 siblings, 1 reply; 90+ messages in thread
From: Imre Deak @ 2015-12-17 17:04 UTC (permalink / raw)
  To: intel-gfx

Since

commit 357597e51dd1aa3cf764d322abf89217e3dcd7bb
Author: Imre Deak <imre.deak@intel.com>
Date:   Tue Nov 10 06:12:22 2015 +0200

    drm/i915: remove HAS_RUNTIME_PM check from RPM get/put/assert helpers

this file is writeable also on platforms without RPM support, but
userspace (at least IGT) depends on this file being unchangable to
determine whether the device supports autosuspend. So restore the old
behavior.

This gets rid of igt/pm_rpm failures on old platforms without RPM
support, where the test should be skipped.

Testcase: igt/pm_rpm/basic-rte
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 drivers/gpu/drm/i915/intel_runtime_pm.c | 13 ++++++++-----
 1 file changed, 8 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index a0b9eaf..ddbdbff 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -2309,18 +2309,21 @@ void intel_runtime_pm_enable(struct drm_i915_private *dev_priv)
 	struct drm_device *dev = dev_priv->dev;
 	struct device *device = &dev->pdev->dev;
 
+	pm_runtime_set_autosuspend_delay(device, 10000); /* 10s */
+	pm_runtime_mark_last_busy(device);
+
 	/*
 	 * Take a permanent reference to disable the RPM functionality and drop
 	 * it only when unloading the driver. Use the low level get/put helpers,
 	 * so the driver's own RPM reference tracking asserts also work on
 	 * platforms without RPM support.
 	 */
-	if (!HAS_RUNTIME_PM(dev))
+	if (!HAS_RUNTIME_PM(dev)) {
+		pm_runtime_dont_use_autosuspend(device);
 		pm_runtime_get_sync(device);
-
-	pm_runtime_set_autosuspend_delay(device, 10000); /* 10s */
-	pm_runtime_mark_last_busy(device);
-	pm_runtime_use_autosuspend(device);
+	} else {
+		pm_runtime_use_autosuspend(device);
+	}
 
 	/*
 	 * The core calls the driver load handler with an RPM reference held.
-- 
2.5.0

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^ permalink raw reply related	[flat|nested] 90+ messages in thread
* [PATCH] drm/i915/vlv: Take forcewake on media engine writes
@ 2015-12-17 15:14 Mika Kuoppala
  2015-12-17 16:20 ` ✗ warning: Fi.CI.BAT Patchwork
  0 siblings, 1 reply; 90+ messages in thread
From: Mika Kuoppala @ 2015-12-17 15:14 UTC (permalink / raw)
  To: intel-gfx; +Cc: Deepak S

Since commit 940aece471bd ("drm/i915/vlv: Valleyview support
for forcewake Individual power wells.") we have only taken
media engine forcewake correctly on reads, but only taken render
engine forcewake on media engine writes and omitted the media
domain.

This asymmetry might have caused unstable behaviour on
media ring access.

Fix is to take media engine forcewake symmetrically to writes.

References: https://bugs.freedesktop.org/show_bug.cgi?id=88012
Cc: Deepak S <deepak.s@intel.com>
Cc: Jesse Barnes <jbarnes@virtuousgeek.org>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
---
 drivers/gpu/drm/i915/intel_uncore.c | 24 ++++++++++++++++++++++++
 1 file changed, 24 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
index 277e60ae0e47..a2e204088aa5 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -902,6 +902,23 @@ hsw_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool t
 	GEN6_WRITE_FOOTER; \
 }
 
+#define __vlv_write(x) \
+static void \
+vlv_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool trace) { \
+	enum forcewake_domains fw_engine = 0; \
+	GEN6_WRITE_HEADER; \
+	if (!NEEDS_FORCE_WAKE(offset)) \
+		fw_engine = 0; \
+	else if (FORCEWAKE_VLV_RENDER_RANGE_OFFSET(offset)) \
+		fw_engine = FORCEWAKE_RENDER; \
+	else if (FORCEWAKE_VLV_MEDIA_RANGE_OFFSET(offset)) \
+		fw_engine = FORCEWAKE_MEDIA; \
+	if (fw_engine) \
+		__force_wake_get(dev_priv, fw_engine); \
+	__raw_i915_write##x(dev_priv, reg, val); \
+	GEN6_WRITE_FOOTER; \
+}
+
 static const i915_reg_t gen8_shadowed_regs[] = {
 	FORCEWAKE_MT,
 	GEN6_RPNSWREQ,
@@ -1019,6 +1036,10 @@ __gen8_write(8)
 __gen8_write(16)
 __gen8_write(32)
 __gen8_write(64)
+__vlv_write(8)
+__vlv_write(16)
+__vlv_write(32)
+__vlv_write(64)
 __hsw_write(8)
 __hsw_write(16)
 __hsw_write(32)
@@ -1031,6 +1052,7 @@ __gen6_write(64)
 #undef __gen9_write
 #undef __chv_write
 #undef __gen8_write
+#undef __vlv_write
 #undef __hsw_write
 #undef __gen6_write
 #undef GEN6_WRITE_FOOTER
@@ -1243,6 +1265,8 @@ void intel_uncore_init(struct drm_device *dev)
 	case 6:
 		if (IS_HASWELL(dev)) {
 			ASSIGN_WRITE_MMIO_VFUNCS(hsw);
+		} else if (IS_VALLEYVIEW(dev)) {
+			ASSIGN_WRITE_MMIO_VFUNCS(vlv);
 		} else {
 			ASSIGN_WRITE_MMIO_VFUNCS(gen6);
 		}
-- 
2.5.0

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^ permalink raw reply related	[flat|nested] 90+ messages in thread
* [PATCH v2 0/5]  Add aspect ratio parsing
@ 2015-12-17 13:42 Shashank Sharma
  2015-12-17 15:49 ` ✗ warning: Fi.CI.BAT Patchwork
  0 siblings, 1 reply; 90+ messages in thread
From: Shashank Sharma @ 2015-12-17 13:42 UTC (permalink / raw)
  To: intel-gfx; +Cc: daniel.vetter

Currently DRM framework doesn't parse aspect ratio of a videomode
while converting it from a umode->kmode or viceversa. This causes
modeset of CEA modes with incorrect aspect ratio.

While running HDMI complaince, tests (like 7-27) expect the DUT
to apply the mode as per the VIC, but as driver does not consider
the aspect ratio part while searching a mode from modedb, we end
up setting mode with a wrong VIC, causing the test to fail.

What this patch set does:
Patch 1-2
- Adds aspect ratio flags in the DRM layer, in form of flags.
- Adds parsing of aspect ratio, during conversion of a umode->kmode
  and viceversa.
- Adds aspect ratio check while finding a mode, during modeset.

Patch 3-5
- Adds some new aspect ratio defined in CEA-861-F specs to
  support HDMI 2.0 displays, in DRM and I915 layer.

V2: needed a rebase

Shashank Sharma (5):
  drm: add picture aspect ratio flags
  drm: Add aspect ratio parsing in DRM layer
  video: Add new aspect ratios for HDMI 2.0
  drm: Add flags for new aspect ratios
  drm/i915: Add support for new aspect ratios

 drivers/gpu/drm/drm_modes.c       | 46 +++++++++++++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/intel_hdmi.c |  6 +++++
 drivers/gpu/drm/i915/intel_sdvo.c |  6 +++++
 drivers/video/hdmi.c              |  4 ++++
 include/linux/hdmi.h              |  2 ++
 include/uapi/drm/drm_mode.h       | 24 +++++++++++++++-----
 6 files changed, 83 insertions(+), 5 deletions(-)

-- 
1.9.1

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^ permalink raw reply	[flat|nested] 90+ messages in thread
* [PATCH] drm/i915: Limit VF cache invalidate workaround usage to gen9
@ 2015-12-17  1:51 Ben Widawsky
  2015-12-18  7:20 ` ✗ warning: Fi.CI.BAT Patchwork
  0 siblings, 1 reply; 90+ messages in thread
From: Ben Widawsky @ 2015-12-17  1:51 UTC (permalink / raw)
  To: Intel GFX; +Cc: Ben Widawsky

It is unclear if this is even required on BXT.

Cc: Imre Deak <imre.deak@intel.com>
Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com>
---
 drivers/gpu/drm/i915/intel_lrc.c | 14 +++++++-------
 1 file changed, 7 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 519cea32..0d35e94 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -1716,14 +1716,14 @@ static int gen8_emit_flush_render(struct drm_i915_gem_request *request,
 		flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
 		flags |= PIPE_CONTROL_QW_WRITE;
 		flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
-	}
 
-	/*
-	 * On GEN9+ Before VF_CACHE_INVALIDATE we need to emit a NULL pipe
-	 * control.
-	 */
-	vf_flush_wa = INTEL_INFO(ring->dev)->gen >= 9 &&
-		      flags & PIPE_CONTROL_VF_CACHE_INVALIDATE;
+		/*
+		 * On GEN9: before VF_CACHE_INVALIDATE we need to emit a NULL
+		 * pipe control.
+		 */
+		if (IS_GEN9(ring->dev))
+			vf_flush_wa = true;
+	}
 
 	ret = intel_logical_ring_begin(request, vf_flush_wa ? 12 : 6);
 	if (ret)
-- 
2.6.4

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^ permalink raw reply related	[flat|nested] 90+ messages in thread
* [PATCH] drm/i915/guc: Fix a warning message problem during driver unload
@ 2015-12-17  1:32 yu.dai
  2015-12-19  9:20 ` ✗ warning: Fi.CI.BAT Patchwork
  0 siblings, 1 reply; 90+ messages in thread
From: yu.dai @ 2015-12-17  1:32 UTC (permalink / raw)
  To: intel-gfx

From: Alex Dai <yu.dai@intel.com>

The device struct_mutex needs to be held before releasing any GEM
objects allocated by GuC.

Signed-off-by: Alex Dai <yu.dai@intel.com>
---
 drivers/gpu/drm/i915/intel_guc_loader.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c b/drivers/gpu/drm/i915/intel_guc_loader.c
index 625272f4..4748651 100644
--- a/drivers/gpu/drm/i915/intel_guc_loader.c
+++ b/drivers/gpu/drm/i915/intel_guc_loader.c
@@ -631,10 +631,10 @@ void intel_guc_ucode_fini(struct drm_device *dev)
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
 
+	mutex_lock(&dev->struct_mutex);
 	direct_interrupts_to_host(dev_priv);
 	i915_guc_submission_fini(dev);
 
-	mutex_lock(&dev->struct_mutex);
 	if (guc_fw->guc_fw_obj)
 		drm_gem_object_unreference(&guc_fw->guc_fw_obj->base);
 	guc_fw->guc_fw_obj = NULL;
-- 
2.5.0

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^ permalink raw reply related	[flat|nested] 90+ messages in thread
* [PATCH] drm/docs: more leftovers from the big vtable documentation pile
@ 2015-12-16 17:18 Daniel Vetter
  2016-01-04  7:20 ` ✗ warning: Fi.CI.BAT Patchwork
  0 siblings, 1 reply; 90+ messages in thread
From: Daniel Vetter @ 2015-12-16 17:18 UTC (permalink / raw)
  To: DRI Development
  Cc: Daniel Vetter, Intel Graphics Development, Thierry Reding,
	Laurent Pinchart, Daniel Vetter

Another pile of vfuncs from the old gpu.tmpl xml documentation that
I've forgotten to delete. I spotted a few more things to
clarify/extend in the new kerneldoc while going through this once
more.

Cc: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Cc: Thierry Reding <treding@nvidia.com>
Signed-off-by: Daniel Vetter <daniel.vetter@intel.com>
---
 Documentation/DocBook/gpu.tmpl           | 188 -------------------------------
 include/drm/drm_modeset_helper_vtables.h |  28 ++++-
 2 files changed, 25 insertions(+), 191 deletions(-)

diff --git a/Documentation/DocBook/gpu.tmpl b/Documentation/DocBook/gpu.tmpl
index a3764291c826..c0fa21c797fe 100644
--- a/Documentation/DocBook/gpu.tmpl
+++ b/Documentation/DocBook/gpu.tmpl
@@ -1579,194 +1579,6 @@ void intel_crt_init(struct drm_device *dev)
       entities.
     </para>
     <sect2>
-      <title>Legacy CRTC Helper Operations</title>
-      <itemizedlist>
-        <listitem id="drm-helper-crtc-mode-fixup">
-          <synopsis>bool (*mode_fixup)(struct drm_crtc *crtc,
-                       const struct drm_display_mode *mode,
-                       struct drm_display_mode *adjusted_mode);</synopsis>
-          <para>
-            Let CRTCs adjust the requested mode or reject it completely. This
-            operation returns true if the mode is accepted (possibly after being
-            adjusted) or false if it is rejected.
-          </para>
-          <para>
-            The <methodname>mode_fixup</methodname> operation should reject the
-            mode if it can't reasonably use it. The definition of "reasonable"
-            is currently fuzzy in this context. One possible behaviour would be
-            to set the adjusted mode to the panel timings when a fixed-mode
-            panel is used with hardware capable of scaling. Another behaviour
-            would be to accept any input mode and adjust it to the closest mode
-            supported by the hardware (FIXME: This needs to be clarified).
-          </para>
-        </listitem>
-        <listitem>
-          <synopsis>int (*mode_set_base)(struct drm_crtc *crtc, int x, int y,
-                     struct drm_framebuffer *old_fb)</synopsis>
-          <para>
-            Move the CRTC on the current frame buffer (stored in
-            <literal>crtc-&gt;fb</literal>) to position (x,y). Any of the frame
-            buffer, x position or y position may have been modified.
-          </para>
-          <para>
-            This helper operation is optional. If not provided, the
-            <function>drm_crtc_helper_set_config</function> function will fall
-            back to the <methodname>mode_set</methodname> helper operation.
-          </para>
-          <note><para>
-            FIXME: Why are x and y passed as arguments, as they can be accessed
-            through <literal>crtc-&gt;x</literal> and
-            <literal>crtc-&gt;y</literal>?
-          </para></note>
-        </listitem>
-        <listitem>
-          <synopsis>void (*prepare)(struct drm_crtc *crtc);</synopsis>
-          <para>
-            Prepare the CRTC for mode setting. This operation is called after
-            validating the requested mode. Drivers use it to perform
-            device-specific operations required before setting the new mode.
-          </para>
-        </listitem>
-        <listitem>
-          <synopsis>int (*mode_set)(struct drm_crtc *crtc, struct drm_display_mode *mode,
-                struct drm_display_mode *adjusted_mode, int x, int y,
-                struct drm_framebuffer *old_fb);</synopsis>
-          <para>
-            Set a new mode, position and frame buffer. Depending on the device
-            requirements, the mode can be stored internally by the driver and
-            applied in the <methodname>commit</methodname> operation, or
-            programmed to the hardware immediately.
-          </para>
-          <para>
-            The <methodname>mode_set</methodname> operation returns 0 on success
-	    or a negative error code if an error occurs.
-          </para>
-        </listitem>
-        <listitem>
-          <synopsis>void (*commit)(struct drm_crtc *crtc);</synopsis>
-          <para>
-            Commit a mode. This operation is called after setting the new mode.
-            Upon return the device must use the new mode and be fully
-            operational.
-          </para>
-        </listitem>
-      </itemizedlist>
-    </sect2>
-    <sect2>
-      <title>Encoder Helper Operations</title>
-      <itemizedlist>
-        <listitem>
-          <synopsis>bool (*mode_fixup)(struct drm_encoder *encoder,
-                       const struct drm_display_mode *mode,
-                       struct drm_display_mode *adjusted_mode);</synopsis>
-          <para>
-            Let encoders adjust the requested mode or reject it completely. This
-            operation returns true if the mode is accepted (possibly after being
-            adjusted) or false if it is rejected. See the
-            <link linkend="drm-helper-crtc-mode-fixup">mode_fixup CRTC helper
-            operation</link> for an explanation of the allowed adjustments.
-          </para>
-        </listitem>
-        <listitem>
-          <synopsis>void (*prepare)(struct drm_encoder *encoder);</synopsis>
-          <para>
-            Prepare the encoder for mode setting. This operation is called after
-            validating the requested mode. Drivers use it to perform
-            device-specific operations required before setting the new mode.
-          </para>
-        </listitem>
-        <listitem>
-          <synopsis>void (*mode_set)(struct drm_encoder *encoder,
-                 struct drm_display_mode *mode,
-                 struct drm_display_mode *adjusted_mode);</synopsis>
-          <para>
-            Set a new mode. Depending on the device requirements, the mode can
-            be stored internally by the driver and applied in the
-            <methodname>commit</methodname> operation, or programmed to the
-            hardware immediately.
-          </para>
-        </listitem>
-        <listitem>
-          <synopsis>void (*commit)(struct drm_encoder *encoder);</synopsis>
-          <para>
-            Commit a mode. This operation is called after setting the new mode.
-            Upon return the device must use the new mode and be fully
-            operational.
-          </para>
-        </listitem>
-      </itemizedlist>
-    </sect2>
-    <sect2>
-      <title>Connector Helper Operations</title>
-      <itemizedlist>
-        <listitem>
-          <synopsis>struct drm_encoder *(*best_encoder)(struct drm_connector *connector);</synopsis>
-          <para>
-            Return a pointer to the best encoder for the connecter. Device that
-            map connectors to encoders 1:1 simply return the pointer to the
-            associated encoder. This operation is mandatory.
-          </para>
-        </listitem>
-        <listitem>
-          <synopsis>int (*get_modes)(struct drm_connector *connector);</synopsis>
-          <para>
-            Fill the connector's <structfield>probed_modes</structfield> list
-            by parsing EDID data with <function>drm_add_edid_modes</function>,
-            adding standard VESA DMT modes with <function>drm_add_modes_noedid</function>,
-            or calling <function>drm_mode_probed_add</function> directly for every
-            supported mode and return the number of modes it has detected. This
-            operation is mandatory.
-          </para>
-          <para>
-            Note that the caller function will automatically add standard VESA
-            DMT modes up to 1024x768 if the <methodname>get_modes</methodname>
-            helper operation returns no mode and if the connector status is
-            connector_status_connected. There is no need to call
-            <function>drm_add_edid_modes</function> manually in that case.
-          </para>
-          <para>
-            The <structfield>vrefresh</structfield> value is computed by
-            <function>drm_helper_probe_single_connector_modes</function>.
-          </para>
-          <para>
-            When parsing EDID data, <function>drm_add_edid_modes</function> fills the
-            connector <structfield>display_info</structfield>
-            <structfield>width_mm</structfield> and
-            <structfield>height_mm</structfield> fields. When creating modes
-            manually the <methodname>get_modes</methodname> helper operation must
-            set the <structfield>display_info</structfield>
-            <structfield>width_mm</structfield> and
-            <structfield>height_mm</structfield> fields if they haven't been set
-            already (for instance at initialization time when a fixed-size panel is
-            attached to the connector). The mode <structfield>width_mm</structfield>
-            and <structfield>height_mm</structfield> fields are only used internally
-            during EDID parsing and should not be set when creating modes manually.
-          </para>
-        </listitem>
-        <listitem>
-          <synopsis>int (*mode_valid)(struct drm_connector *connector,
-		  struct drm_display_mode *mode);</synopsis>
-          <para>
-            Verify whether a mode is valid for the connector. Return MODE_OK for
-            supported modes and one of the enum drm_mode_status values (MODE_*)
-            for unsupported modes. This operation is optional.
-          </para>
-          <para>
-            As the mode rejection reason is currently not used beside for
-            immediately removing the unsupported mode, an implementation can
-            return MODE_BAD regardless of the exact reason why the mode is not
-            valid.
-          </para>
-          <note><para>
-            Note that the <methodname>mode_valid</methodname> helper operation is
-            only called for modes detected by the device, and
-            <emphasis>not</emphasis> for modes set by the user through the CRTC
-            <methodname>set_config</methodname> operation.
-          </para></note>
-        </listitem>
-      </itemizedlist>
-    </sect2>
-    <sect2>
       <title>Atomic Modeset Helper Functions Reference</title>
       <sect3>
 	<title>Overview</title>
diff --git a/include/drm/drm_modeset_helper_vtables.h b/include/drm/drm_modeset_helper_vtables.h
index 29e0dc50031d..b995d5ec50a0 100644
--- a/include/drm/drm_modeset_helper_vtables.h
+++ b/include/drm/drm_modeset_helper_vtables.h
@@ -131,6 +131,12 @@ struct drm_crtc_helper_funcs {
 	 * Atomic drivers which need to inspect and adjust more state should
 	 * instead use the @atomic_check callback.
 	 *
+	 * Also beware that the core nor helpers filters mode before passing the
+	 * to the driver. More specifically modes rejected by the ->mode_valid
+	 * callback from #drm_connector_helper_funcs can still be requested by
+	 * userspace and therefore also need to be rejected in either this hook,
+	 * or the one in #drm_encoder_helper_funcs.
+	 *
 	 * RETURNS:
 	 *
 	 * True if an acceptable configuration is possible, false if the modeset
@@ -188,7 +194,9 @@ struct drm_crtc_helper_funcs {
 	 * This callback is used by the legacy CRTC helpers to set a new
 	 * framebuffer and scanout position. It is optional and used as an
 	 * optimized fast-path instead of a full mode set operation with all the
-	 * resulting flickering. Since it can't update other planes it's
+	 * resulting flickering. If it is not present
+	 * drm_crtc_helper_set_config() will fall back to a full modeset, using
+	 * the ->mode_set() callbac. Since it can't update other planes it's
 	 * incompatible with atomic modeset support.
 	 *
 	 * This callback is only used by the CRTC helpers and deprecated.
@@ -439,6 +447,12 @@ struct drm_encoder_helper_funcs {
 	 * Atomic drivers which need to inspect and adjust more state should
 	 * instead use the @atomic_check callback.
 	 *
+	 * Also beware that the core nor helpers filters mode before passing the
+	 * to the driver. More specifically modes rejected by the ->mode_valid
+	 * callback from #drm_connector_helper_funcs can still be requested by
+	 * userspace and therefore also need to be rejected in either this hook,
+	 * or the one in #drm_crtc_helper_funcs.
+	 *
 	 * RETURNS:
 	 *
 	 * True if an acceptable configuration is possible, false if the modeset
@@ -640,8 +654,16 @@ struct drm_connector_helper_funcs {
 	 * In this function drivers then parse the modes in the EDID and add
 	 * them by calling drm_add_edid_modes(). But connectors that driver a
 	 * fixed panel can also manually add specific modes using
-	 * drm_mode_probed_add(). Finally drivers that support audio probably
-	 * want to update the ELD data, too, using drm_edid_to_eld().
+	 * drm_mode_probed_add(). Drivers who manually add modes should also
+	 * make sure that the @display_info, @width_mm and @height_mm fields of the
+	 * struct #drm_connector are filled out.
+	 *
+	 * Virtual drivers who just want some standard VESA mode with a given
+	 * resolution can call drm_add_modes_noedid(), and mark the preferred
+	 * one using drm_set_preferred_mode().
+	 *
+	 * Finally drivers that support audio probably want to update the ELD
+	 * data, too, using drm_edid_to_eld().
 	 *
 	 * This function is only called after the ->detect() hook has indicated
 	 * that a sink is connected and when the EDID isn't overridden through
-- 
2.6.4

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^ permalink raw reply related	[flat|nested] 90+ messages in thread
* [PATCH] drm/i915: Avoid writing relocs with addresses in non-canonical form
@ 2015-12-04 11:33 Michał Winiarski
  2015-12-19  8:20 ` ✗ warning: Fi.CI.BAT Patchwork
                   ` (3 more replies)
  0 siblings, 4 replies; 90+ messages in thread
From: Michał Winiarski @ 2015-12-04 11:33 UTC (permalink / raw)
  To: intel-gfx

According to bspec, some parts of HW expect the addresses to be in
a canonical form, where bits [63:48] == [47]. Let's convert addresses to
canonical form prior to relocating and return converted offsets to
userspace.

Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Michel Thierry <michel.thierry@intel.com>
Signed-off-by: Michał Winiarski <michal.winiarski@intel.com>
---
 drivers/gpu/drm/i915/i915_gem_execbuffer.c | 9 ++++++---
 drivers/gpu/drm/i915/i915_gem_gtt.h        | 5 +++++
 2 files changed, 11 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
index a4c243c..9f27be9 100644
--- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
@@ -395,7 +395,7 @@ i915_gem_execbuffer_relocate_entry(struct drm_i915_gem_object *obj,
 	target_i915_obj = target_vma->obj;
 	target_obj = &target_vma->obj->base;
 
-	target_offset = target_vma->node.start;
+	target_offset = gen8_canonical_addr(target_vma->node.start);
 
 	/* Sandybridge PPGTT errata: We need a global gtt mapping for MI and
 	 * pipe_control writes because the gpu doesn't properly redirect them
@@ -583,6 +583,7 @@ i915_gem_execbuffer_reserve_vma(struct i915_vma *vma,
 	struct drm_i915_gem_object *obj = vma->obj;
 	struct drm_i915_gem_exec_object2 *entry = vma->exec_entry;
 	uint64_t flags;
+	uint64_t offset;
 	int ret;
 
 	flags = PIN_USER;
@@ -623,8 +624,10 @@ i915_gem_execbuffer_reserve_vma(struct i915_vma *vma,
 			entry->flags |= __EXEC_OBJECT_HAS_FENCE;
 	}
 
-	if (entry->offset != vma->node.start) {
-		entry->offset = vma->node.start;
+	offset = gen8_canonical_addr(vma->node.start);
+
+	if (entry->offset != offset) {
+		entry->offset = offset;
 		*need_reloc = true;
 	}
 
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h b/drivers/gpu/drm/i915/i915_gem_gtt.h
index 877c32c..65e8f88 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.h
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.h
@@ -507,6 +507,11 @@ static inline size_t gen8_pte_count(uint64_t address, uint64_t length)
 	return i915_pte_count(address, length, GEN8_PDE_SHIFT);
 }
 
+static inline uint64_t gen8_canonical_addr(uint64_t address)
+{
+	return ((int64_t)address << 16) >> 16;
+}
+
 static inline dma_addr_t
 i915_page_dir_dma_addr(const struct i915_hw_ppgtt *ppgtt, const unsigned n)
 {
-- 
2.5.0

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Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 90+ messages in thread

end of thread, other threads:[~2016-01-25 15:44 UTC | newest]

Thread overview: 90+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2015-12-30 21:20 [PATCH] drm/dp/mst: constify drm_dp_mst_topology_cbs structures Julia Lawall
2015-12-30 21:20 ` Julia Lawall
2015-12-30 21:20 ` Julia Lawall
2015-12-31  7:20 ` ✗ warning: Fi.CI.BAT Patchwork
2016-01-04  7:10 ` [PATCH] drm/dp/mst: constify drm_dp_mst_topology_cbs structures Daniel Vetter
2016-01-04  7:10   ` Daniel Vetter
2016-01-04  7:10   ` Daniel Vetter
  -- strict thread matches above, loose matches on Subject: below --
2016-01-14 16:32 [PATCH] drm/i915: Don't do pre plane update on disabled crtcs Mika Kuoppala
2016-01-14 17:20 ` ✗ warning: Fi.CI.BAT Patchwork
2016-01-14 12:02 [PATCH 0/7] Misc WM fixes and Arbitrated Display Bandwidth WA for SKL Shobhit Kumar
2016-01-14 13:20 ` ✗ warning: Fi.CI.BAT Patchwork
2016-01-14 10:28 [PATCH 1/2] drm/i915/dsi: lose the loose 666 format name in favor of packed Jani Nikula
2016-01-14 11:49 ` ✗ warning: Fi.CI.BAT Patchwork
2016-01-13 22:05 [PATCH] drm/i915: Sink CRC: tune down error message at stop to debug_kms Rodrigo Vivi
2016-01-14 10:20 ` ✗ warning: Fi.CI.BAT Patchwork
2016-01-13 14:31 [PATCH] drm/crtc-helper: Add caveat to disable_unused_functions doc Daniel Vetter
2016-01-13 14:57 ` ✗ warning: Fi.CI.BAT Patchwork
2016-01-25 15:44   ` Daniel Vetter
2016-01-13 10:55 [PATCH] drm/i915: Init power domains early in driver load Daniel Vetter
2016-01-13 12:13 ` ✗ warning: Fi.CI.BAT Patchwork
2016-01-13 15:11   ` Daniel Vetter
2016-01-13  1:57 [PATCH v4] drm/i915: edp resume/On time optimization abhay.kumar
2016-01-13 10:20 ` ✗ warning: Fi.CI.BAT Patchwork
2016-01-12 19:08 [PATCH 0/7] drm/i915: Reviewed fb offsets[] prep patches ville.syrjala
2016-01-13  8:24 ` ✗ warning: Fi.CI.BAT Patchwork
2016-01-13 15:52   ` Ville Syrjälä
2016-01-12 16:04 [PATCH 1/2] drm/i915/gen8: Tidy display interrupt processing Tvrtko Ursulin
2016-01-13  7:49 ` ✗ warning: Fi.CI.BAT Patchwork
2016-01-12 15:59 [PATCH 0/2] DPCD Backlight Control Yetunde Adebisi
2016-01-12 17:49 ` ✗ warning: Fi.CI.BAT Patchwork
2016-01-21 15:07   ` Adebisi, YetundeX
2016-01-22 14:35     ` Jani Nikula
2016-01-11 22:55 [PATCH] drm/i915: edp resume/On time optimization abhay.kumar
2016-01-12  9:49 ` ✗ warning: Fi.CI.BAT Patchwork
2016-01-11 21:52 [PATCH] drm/i915: reboot notifier delay for eDP panels clinton.a.taylor
2016-01-12  9:16 ` ✗ warning: Fi.CI.BAT Patchwork
2016-01-11 16:16 [PATCH] drm/i915: Handle error paths during watermark sanitization properly Matt Roper
2016-01-11 16:49 ` ✗ warning: Fi.CI.BAT Patchwork
2016-01-12  7:20 ` Patchwork
2016-01-12 15:49 ` Patchwork
2016-01-08 20:25 [PATCH] drm: Release driver references to handle before making it available again Chris Wilson
2016-01-11 10:53 ` ✗ warning: Fi.CI.BAT Patchwork
2016-01-11 10:55 ` Patchwork
2016-01-08 16:58 [PATCH 1/2] drm/i915: Store edram capabilities instead of fixed size Mika Kuoppala
2016-01-11 10:27 ` ✗ warning: Fi.CI.BAT Patchwork
2016-01-08 15:03 [PATCH 0/3] Enabling GuC Loading on Broxton Peter Antoine
2016-01-11 10:13 ` ✗ warning: Fi.CI.BAT Patchwork
2016-01-12 16:23   ` Daniel Vetter
2016-01-07  9:59 [PATCH 0/5] Add encoder_mask to crtc_state, v2 Maarten Lankhorst
2016-01-11  8:52 ` ✗ warning: Fi.CI.BAT Patchwork
2016-01-06 20:53 [PATCH] drm/i915/guc: Fix a memory leak where guc->execbuf_client is not freed yu.dai
2016-01-14  9:49 ` ✗ warning: Fi.CI.BAT Patchwork
2016-01-19 10:07   ` Tvrtko Ursulin
2016-01-05 18:30 [PATCH 0/5] Some minor CSB/execlist stuff Ben Widawsky
2016-01-06  8:20 ` ✗ warning: Fi.CI.BAT Patchwork
2016-01-05 15:58 [PATCH] drm/i915: Update Skylake DDI translation table for DP Rodrigo Vivi
2016-01-06  7:20 ` ✗ warning: Fi.CI.BAT Patchwork
2016-01-05 15:32 [PATCH] drm/i915: Update Skylake DDI translation table for HDMI Rodrigo Vivi
2016-01-05 17:49 ` ✗ warning: Fi.CI.BAT Patchwork
2016-01-05 12:50 [PATCH 0/6] Fixing sink count related detection over Shubhangi Shrivastava
2016-01-05 13:49 ` ✗ warning: Fi.CI.BAT Patchwork
2016-01-05  3:29 [PATCH] [trivial] drm/i915 Fix typos in i915_gem_fence.c Masanari Iida
2016-01-05  8:20 ` ✗ warning: Fi.CI.BAT Patchwork
2016-01-05  1:10 [PATCH 1/3] drm/i915: Move HAS_PSR definition to the platform definition Rodrigo Vivi
2016-01-05  7:49 ` ✗ warning: Fi.CI.BAT Patchwork
2016-01-04 23:00 [PATCH] drm/i915: Allow a way to disable watermark for debuging purposes Rodrigo Vivi
2016-01-05  7:20 ` ✗ warning: Fi.CI.BAT Patchwork
2016-01-04 11:53 [PATCH v2 1/6] drm/i915: Set connector_state->connector using the helper Maarten Lankhorst
2016-01-04 12:49 ` ✗ warning: Fi.CI.BAT Patchwork
2016-01-04 11:21 [PATCH v5 0/3] drm/i915: Disable link training optimization if DP config has changed Mika Kahola
2016-01-04 11:49 ` ✗ warning: Fi.CI.BAT Patchwork
2015-12-31 12:45 [PATCH] drm/i915: Add RPM references in the *_get_hw_state functions Gabriel Feceoru
2015-12-31 16:20 ` ✗ warning: Fi.CI.BAT Patchwork
2015-12-31 10:00 [PATCH] drm/i915/bxt: Save/Restore Backlight registers when PG0 is gated Vidya Srinivas
2015-12-31 10:20 ` ✗ warning: Fi.CI.BAT Patchwork
2015-12-30 15:59 [PATCH v2] i915: correctly handling failed allocation Insu Yun
2016-01-04  8:14 ` ✗ warning: Fi.CI.BAT Patchwork
2015-12-29 22:20 [PATCH] drm/i915: Fix whitespace (trivial) Ben Widawsky
2015-12-30  7:20 ` ✗ warning: Fi.CI.BAT Patchwork
2015-12-29 10:55 [PATCH] drm/i915: Hold a RPM reference during i915_driver_unload Gabriel Feceoru
2015-12-29 12:32 ` ✗ warning: Fi.CI.BAT Patchwork
2015-12-29 12:40 ` Patchwork
2015-12-23 19:33 [PATCH v2, 0/4] improve handling of the driver's default context Dave Gordon
2015-12-24  7:49 ` ✗ warning: Fi.CI.BAT Patchwork
2015-12-23  6:50 [PATCH 1/2] drm/i915: fix get digital port issue in intel_audio libin.yang
2015-12-23  7:49 ` ✗ warning: Fi.CI.BAT Patchwork
2015-12-29  2:23   ` Libin Yang
2015-12-30 12:47     ` Jani Nikula
2015-12-23  5:22 [PATCH] drm/i915/bxt: Fix wm calculation for pixel format change Nabendu Maiti
2015-12-23  7:20 ` ✗ warning: Fi.CI.BAT Patchwork
2015-12-22  1:18 [PATCH] drm/i915: edp resume/On time optimization abhay.kumar
2015-12-22  8:49 ` ✗ warning: Fi.CI.BAT Patchwork
2015-12-21 19:32 [PATCH] drm/i915: Drop ilk_wm_max_level() Matt Roper
2015-12-22  8:20 ` ✗ warning: Fi.CI.BAT Patchwork
2015-12-21 15:31 [PATCH] drm/i915/skl: Use proper plane dimensions for DDB and WM calculations Matt Roper
2015-12-21 17:20 ` ✗ warning: Fi.CI.BAT Patchwork
2015-12-21 13:10 [PATCH 00/15] drm/i915/bios: mipi sequence block v3, etc Jani Nikula
2015-12-21 13:27 ` ✗ warning: Fi.CI.BAT Patchwork
2015-12-21 11:57 [PATCH] drm/i915: Handle PipeC fused off on HSW Gabriel Feceoru
2015-12-21 13:13 ` ✗ warning: Fi.CI.BAT Patchwork
2015-12-21 13:14 ` Patchwork
2016-01-13 16:49 ` Patchwork
2015-12-21 11:39 [PATCH v5 0/2] drm/i915: Disable link training optimization if DP config has changed Mika Kahola
2015-12-21 12:14 ` ✗ warning: Fi.CI.BAT Patchwork
2015-12-21 12:14 ` Patchwork
2015-12-21 12:20 ` Patchwork
2015-12-19  9:58 [PATCH] drm/i915: Acquire RPM wakeref for KMS atomic commit Chris Wilson
2015-12-19 10:49 ` ✗ warning: Fi.CI.BAT Patchwork
2015-12-21 10:37 ` Patchwork
2015-12-19  1:27 [PATCH] drm/fb-helper: Use proper plane mask for fb cleanup Matt Roper
2015-12-19 10:20 ` ✗ warning: Fi.CI.BAT Patchwork
2015-12-18 23:58 [PATCH v2] drm/i915/skl: Increase ddb blocks to support large cursor sizes Radhakrishna Sripada
2015-12-19  9:49 ` ✗ warning: Fi.CI.BAT Patchwork
2015-12-18 20:00 [PATCH v2 0/5] Add GuC ADS (Addition Data Structure) yu.dai
2015-12-19  8:49 ` ✗ warning: Fi.CI.BAT Patchwork
2015-12-18 14:14 [PATCH] drm/i915/skl: Default to noncoherent access up to F0 Mika Kuoppala
2015-12-18 14:49 ` ✗ warning: Fi.CI.BAT Patchwork
2015-12-18 12:27 [PATCH v3 0/2] Optimize WARN_ON macros Joonas Lahtinen
2015-12-18 13:20 ` ✗ warning: Fi.CI.BAT Patchwork
2015-12-18 14:00 ` Patchwork
2015-12-18 11:17 [PATCH v2 0/2] Optimize WARN_ON macros Joonas Lahtinen
2015-12-18 12:14 ` ✗ warning: Fi.CI.BAT Patchwork
2015-12-18 13:59 ` Patchwork
2015-12-18 10:39 [PATCH 0/2] Optimize WARN_ON macros Joonas Lahtinen
2015-12-18 11:20 ` ✗ warning: Fi.CI.BAT Patchwork
2015-12-18  8:51 [PATCH] drm/i915/backlight: prefer dev_priv over dev pointer Jani Nikula
2015-12-18  9:49 ` ✗ warning: Fi.CI.BAT Patchwork
2015-12-17 19:25 [RFC][PATCH 0/6] Optionally display recurring warning messages Joonas Lahtinen
2015-12-18  8:20 ` ✗ warning: Fi.CI.BAT Patchwork
2015-12-17 18:18 [PATCH] drm/i915: Hide one invalid cancellation bug in i915_switch_context() Chris Wilson
2015-12-18  7:49 ` ✗ warning: Fi.CI.BAT Patchwork
2015-12-21 13:12 ` Patchwork
2015-12-17 17:04 [PATCH] drm/i915: don't enable autosuspend on platforms without RPM support Imre Deak
2015-12-17 17:49 ` ✗ warning: Fi.CI.BAT Patchwork
2015-12-17 15:14 [PATCH] drm/i915/vlv: Take forcewake on media engine writes Mika Kuoppala
2015-12-17 16:20 ` ✗ warning: Fi.CI.BAT Patchwork
2015-12-17 13:42 [PATCH v2 0/5] Add aspect ratio parsing Shashank Sharma
2015-12-17 15:49 ` ✗ warning: Fi.CI.BAT Patchwork
2015-12-17  1:51 [PATCH] drm/i915: Limit VF cache invalidate workaround usage to gen9 Ben Widawsky
2015-12-18  7:20 ` ✗ warning: Fi.CI.BAT Patchwork
2015-12-17  1:32 [PATCH] drm/i915/guc: Fix a warning message problem during driver unload yu.dai
2015-12-19  9:20 ` ✗ warning: Fi.CI.BAT Patchwork
2015-12-16 17:18 [PATCH] drm/docs: more leftovers from the big vtable documentation pile Daniel Vetter
2016-01-04  7:20 ` ✗ warning: Fi.CI.BAT Patchwork
2015-12-04 11:33 [PATCH] drm/i915: Avoid writing relocs with addresses in non-canonical form Michał Winiarski
2015-12-19  8:20 ` ✗ warning: Fi.CI.BAT Patchwork
2015-12-22 11:13 ` Patchwork
2015-12-22 14:49 ` Patchwork
2015-12-29 17:49 ` Patchwork

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