From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752847AbbLaW3x (ORCPT ); Thu, 31 Dec 2015 17:29:53 -0500 Received: from mail.kernel.org ([198.145.29.136]:58725 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752052AbbLaW3v (ORCPT ); Thu, 31 Dec 2015 17:29:51 -0500 Date: Thu, 31 Dec 2015 16:29:46 -0600 From: Rob Herring To: Jiancheng Xue Cc: mturquette@baylibre.com, sboyd@codeaurora.org, pawel.moll@arm.com, mark.rutland@arm.com, ijc+devicetree@hellion.org.uk, galak@codeaurora.org, linux@arm.linux.org.uk, khilman@linaro.org, arnd@arndb.de, olof@lixom.net, xuwei5@hisilicon.com, haojian.zhuang@linaro.org, zhangfei.gao@linaro.org, bintian.wang@huawei.com, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, yanhaifeng@hisilicon.com, yanghongwei@hisilicon.com, suwenping@hisilicon.com, ml.yang@hisilicon.com, gaofei@hisilicon.com, zhangzhenxing@hisilicon.com Subject: Re: [PATCH v4 1/6] clk: hisilicon: add CRG driver for hi3519 soc Message-ID: <20151231222946.GA21265@rob-hp-laptop> References: <1451439832-13927-1-git-send-email-xuejiancheng@huawei.com> <1451439832-13927-2-git-send-email-xuejiancheng@huawei.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1451439832-13927-2-git-send-email-xuejiancheng@huawei.com> User-Agent: Mutt/1.5.23 (2014-03-12) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, Dec 30, 2015 at 09:43:47AM +0800, Jiancheng Xue wrote: > The CRG(Clock and Reset Generator) block provides clock > and reset signals for other modules in hi3519 soc. > > Signed-off-by: Jiancheng Xue > --- > .../devicetree/bindings/clock/hi3519-crg.txt | 46 +++++++ For the binding: Acked-by: Rob Herring From mboxrd@z Thu Jan 1 00:00:00 1970 From: robh@kernel.org (Rob Herring) Date: Thu, 31 Dec 2015 16:29:46 -0600 Subject: [PATCH v4 1/6] clk: hisilicon: add CRG driver for hi3519 soc In-Reply-To: <1451439832-13927-2-git-send-email-xuejiancheng@huawei.com> References: <1451439832-13927-1-git-send-email-xuejiancheng@huawei.com> <1451439832-13927-2-git-send-email-xuejiancheng@huawei.com> Message-ID: <20151231222946.GA21265@rob-hp-laptop> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On Wed, Dec 30, 2015 at 09:43:47AM +0800, Jiancheng Xue wrote: > The CRG(Clock and Reset Generator) block provides clock > and reset signals for other modules in hi3519 soc. > > Signed-off-by: Jiancheng Xue > --- > .../devicetree/bindings/clock/hi3519-crg.txt | 46 +++++++ For the binding: Acked-by: Rob Herring