From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752401AbcAERkm (ORCPT ); Tue, 5 Jan 2016 12:40:42 -0500 Received: from pandora.arm.linux.org.uk ([78.32.30.218]:42532 "EHLO pandora.arm.linux.org.uk" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751857AbcAERkk (ORCPT ); Tue, 5 Jan 2016 12:40:40 -0500 Date: Tue, 5 Jan 2016 17:40:18 +0000 From: Russell King - ARM Linux To: Mathieu Desnoyers Cc: Will Deacon , Thomas Gleixner , Paul Turner , Andrew Hunter , Peter Zijlstra , linux-kernel@vger.kernel.org, linux-api , Andy Lutomirski , Andi Kleen , Dave Watson , Chris Lameter , Ingo Molnar , Ben Maurer , rostedt , "Paul E. McKenney" , Josh Triplett , Linus Torvalds , Andrew Morton , Catalin Marinas , Michael Kerrisk Subject: Re: [RFC PATCH 1/3] getcpu_cache system call: cache CPU number of running thread Message-ID: <20160105174017.GY19062@n2100.arm.linux.org.uk> References: <1451977320-4886-1-git-send-email-mathieu.desnoyers@efficios.com> <1451977320-4886-2-git-send-email-mathieu.desnoyers@efficios.com> <20160105120400.GD10705@arm.com> <1079064730.338115.1452015105259.JavaMail.zimbra@efficios.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1079064730.338115.1452015105259.JavaMail.zimbra@efficios.com> User-Agent: Mutt/1.5.23 (2014-03-12) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, Jan 05, 2016 at 05:31:45PM +0000, Mathieu Desnoyers wrote: > For instance, an application could create a linked list or hash map > of thread control structures, which could contain the current CPU > number of each thread. A dispatch thread could then traverse or > lookup this structure to see on which CPU each thread is running and > do work queue dispatch or scheduling decisions accordingly. So, what happens if the linked list is walked from thread X, and we discover that thread Y is allegedly running on CPU1. We decide that we want to dispatch some work on that thread due to it being on CPU1, so we send an event to thread Y. Thread Y becomes runnable, and the scheduler decides to schedule the thread on CPU3 instead of CPU1. My point is that the above idea is inherently racy. The only case where it isn't racy is when thread Y is bound to CPU1, and so can't move - but then you'd know that thread Y is on CPU1 and there wouldn't be a need for the inherent complexity suggested above. The behaviour I've seen on ARM from the scheduler (on a quad CPU platform, observing the system activity with top reporting the last CPU number used by each thread) is that threads often migrate between CPUs - especially in the case of (eg) one or two threads running in a quad-CPU system. Given that, I'm really not sure what the use of reading and making decisions on the current CPU number would be within a program - unless the thread is bound to a particular CPU or group of CPUs, it seems that you can't rely on being on the reported CPU by the time the system call returns. -- RMK's Patch system: http://www.arm.linux.org.uk/developer/patches/ FTTC broadband for 0.8mile line: currently at 9.6Mbps down 400kbps up according to speedtest.net. From mboxrd@z Thu Jan 1 00:00:00 1970 From: Russell King - ARM Linux Subject: Re: [RFC PATCH 1/3] getcpu_cache system call: cache CPU number of running thread Date: Tue, 5 Jan 2016 17:40:18 +0000 Message-ID: <20160105174017.GY19062@n2100.arm.linux.org.uk> References: <1451977320-4886-1-git-send-email-mathieu.desnoyers@efficios.com> <1451977320-4886-2-git-send-email-mathieu.desnoyers@efficios.com> <20160105120400.GD10705@arm.com> <1079064730.338115.1452015105259.JavaMail.zimbra@efficios.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Return-path: Content-Disposition: inline In-Reply-To: <1079064730.338115.1452015105259.JavaMail.zimbra-vg+e7yoeK/dWk0Htik3J/w@public.gmane.org> Sender: linux-api-owner-u79uwXL29TY76Z2rM5mHXA@public.gmane.org To: Mathieu Desnoyers Cc: Will Deacon , Thomas Gleixner , Paul Turner , Andrew Hunter , Peter Zijlstra , linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-api , Andy Lutomirski , Andi Kleen , Dave Watson , Chris Lameter , Ingo Molnar , Ben Maurer , rostedt , "Paul E. McKenney" , Josh Triplett , Linus Torvalds , Andrew Morton , Catalin Marinas , Michael Kerrisk List-Id: linux-api@vger.kernel.org On Tue, Jan 05, 2016 at 05:31:45PM +0000, Mathieu Desnoyers wrote: > For instance, an application could create a linked list or hash map > of thread control structures, which could contain the current CPU > number of each thread. A dispatch thread could then traverse or > lookup this structure to see on which CPU each thread is running and > do work queue dispatch or scheduling decisions accordingly. So, what happens if the linked list is walked from thread X, and we discover that thread Y is allegedly running on CPU1. We decide that we want to dispatch some work on that thread due to it being on CPU1, so we send an event to thread Y. Thread Y becomes runnable, and the scheduler decides to schedule the thread on CPU3 instead of CPU1. My point is that the above idea is inherently racy. The only case where it isn't racy is when thread Y is bound to CPU1, and so can't move - but then you'd know that thread Y is on CPU1 and there wouldn't be a need for the inherent complexity suggested above. The behaviour I've seen on ARM from the scheduler (on a quad CPU platform, observing the system activity with top reporting the last CPU number used by each thread) is that threads often migrate between CPUs - especially in the case of (eg) one or two threads running in a quad-CPU system. Given that, I'm really not sure what the use of reading and making decisions on the current CPU number would be within a program - unless the thread is bound to a particular CPU or group of CPUs, it seems that you can't rely on being on the reported CPU by the time the system call returns. -- RMK's Patch system: http://www.arm.linux.org.uk/developer/patches/ FTTC broadband for 0.8mile line: currently at 9.6Mbps down 400kbps up according to speedtest.net.