From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga11.intel.com ([192.55.52.93]:61892 "EHLO mga11.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753451AbcAGMwb (ORCPT ); Thu, 7 Jan 2016 07:52:31 -0500 Date: Thu, 7 Jan 2016 14:52:26 +0200 From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= To: Daniel Vetter Cc: DRI Development , Intel Graphics Development , Patrik Jakobsson , Imre Deak , Jani Nikula , Meelis Roos , Chris Wilson , stable@vger.kernel.org, Daniel Vetter Subject: Re: [PATCH] drm/i915: Init power domains early in driver load Message-ID: <20160107125226.GA4437@intel.com> References: <1452157856-27360-1-git-send-email-daniel.vetter@ffwll.ch> <1452167061-27252-1-git-send-email-daniel.vetter@ffwll.ch> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <1452167061-27252-1-git-send-email-daniel.vetter@ffwll.ch> Sender: stable-owner@vger.kernel.org List-ID: On Thu, Jan 07, 2016 at 12:44:21PM +0100, Daniel Vetter wrote: > Since > > commit ac9b8236551d1177fd07b56aef9b565d1864420d > Author: Ville Syrj�l� > Date: Fri Nov 27 18:55:26 2015 +0200 > > drm/i915: Introduce a gmbus power domain > > gmbus also needs the power domain infrastructure right from the start, > since as soon as we register the i2c controllers someone can use them. > > v2: Adjust cleanup paths too (Chris). > > Cc: Ville Syrj�l� > Cc: Patrik Jakobsson > Cc: Imre Deak > Cc: Jani Nikula > Cc: Meelis Roos > Cc: Chris Wilson > Fixes: ac9b8236551d ("drm/i915: Introduce a gmbus power domain") > Cc: stable@vger.kernel.org > References: http://www.spinics.net/lists/intel-gfx/msg83075.html > Tested-by: Meelis Roos > Signed-off-by: Daniel Vetter > --- > drivers/gpu/drm/i915/i915_dma.c | 11 +++++------ > 1 file changed, 5 insertions(+), 6 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c > index 988a3806512a..490d8b0d931e 100644 > --- a/drivers/gpu/drm/i915/i915_dma.c > +++ b/drivers/gpu/drm/i915/i915_dma.c > @@ -398,7 +398,6 @@ static int i915_load_modeset_init(struct drm_device *dev) > if (ret) > goto cleanup_vga_switcheroo; > > - intel_power_domains_init_hw(dev_priv, false); > > intel_csr_ucode_init(dev_priv); > > @@ -1025,6 +1024,8 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags) > > intel_irq_init(dev_priv); > intel_uncore_sanitize(dev); > + intel_power_domains_init(dev_priv); > + intel_power_domains_init_hw(dev_priv); I think intel_init_dpio() needs to be moved too. We need to know the DPIO IOSF ports before attempting to talk to the PHY (which can happen from intel_power_domains_init_hw()). I'm also wondering why we're doing gmbus init this early. We shouldn't need it until modeset init. > > /* Try to make sure MCHBAR is enabled before poking at it */ > intel_setup_mchbar(dev); > @@ -1057,12 +1058,10 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags) > goto out_gem_unload; > } > > - intel_power_domains_init(dev_priv); > - > ret = i915_load_modeset_init(dev); > if (ret < 0) { > DRM_ERROR("failed to init modeset\n"); > - goto out_power_well; > + goto out_vblank; > } > > /* > @@ -1091,8 +1090,7 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags) > > return 0; > > -out_power_well: > - intel_power_domains_fini(dev_priv); > +out_vblank: > drm_vblank_cleanup(dev); > out_gem_unload: > WARN_ON(unregister_oom_notifier(&dev_priv->mm.oom_notifier)); > @@ -1103,6 +1101,7 @@ out_gem_unload: > > intel_teardown_gmbus(dev); > intel_teardown_mchbar(dev); > + intel_power_domains_fini(dev_priv); > pm_qos_remove_request(&dev_priv->pm_qos); > destroy_workqueue(dev_priv->gpu_error.hangcheck_wq); > out_freedpwq: > -- > 2.6.4 -- Ville Syrj�l� Intel OTC From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= Subject: Re: [PATCH] drm/i915: Init power domains early in driver load Date: Thu, 7 Jan 2016 14:52:26 +0200 Message-ID: <20160107125226.GA4437@intel.com> References: <1452157856-27360-1-git-send-email-daniel.vetter@ffwll.ch> <1452167061-27252-1-git-send-email-daniel.vetter@ffwll.ch> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: Content-Disposition: inline In-Reply-To: <1452167061-27252-1-git-send-email-daniel.vetter@ffwll.ch> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: Daniel Vetter Cc: Meelis Roos , Jani Nikula , Intel Graphics Development , DRI Development , stable@vger.kernel.org, Daniel Vetter List-Id: dri-devel@lists.freedesktop.org T24gVGh1LCBKYW4gMDcsIDIwMTYgYXQgMTI6NDQ6MjFQTSArMDEwMCwgRGFuaWVsIFZldHRlciB3 cm90ZToKPiBTaW5jZQo+IAo+IGNvbW1pdCBhYzliODIzNjU1MWQxMTc3ZmQwN2I1NmFlZjliNTY1 ZDE4NjQ0MjBkCj4gQXV0aG9yOiBWaWxsZSBTeXJqw6Rsw6QgPHZpbGxlLnN5cmphbGFAbGludXgu aW50ZWwuY29tPgo+IERhdGU6ICAgRnJpIE5vdiAyNyAxODo1NToyNiAyMDE1ICswMjAwCj4gCj4g ICAgIGRybS9pOTE1OiBJbnRyb2R1Y2UgYSBnbWJ1cyBwb3dlciBkb21haW4KPiAKPiBnbWJ1cyBh bHNvIG5lZWRzIHRoZSBwb3dlciBkb21haW4gaW5mcmFzdHJ1Y3R1cmUgcmlnaHQgZnJvbSB0aGUg c3RhcnQsCj4gc2luY2UgYXMgc29vbiBhcyB3ZSByZWdpc3RlciB0aGUgaTJjIGNvbnRyb2xsZXJz IHNvbWVvbmUgY2FuIHVzZSB0aGVtLgo+IAo+IHYyOiBBZGp1c3QgY2xlYW51cCBwYXRocyB0b28g KENocmlzKS4KPiAKPiBDYzogVmlsbGUgU3lyasOkbMOkIDx2aWxsZS5zeXJqYWxhQGxpbnV4Lmlu dGVsLmNvbT4KPiBDYzogUGF0cmlrIEpha29ic3NvbiA8cGF0cmlrLmpha29ic3NvbkBsaW51eC5p bnRlbC5jb20+Cj4gQ2M6IEltcmUgRGVhayA8aW1yZS5kZWFrQGludGVsLmNvbT4KPiBDYzogSmFu aSBOaWt1bGEgPGphbmkubmlrdWxhQGludGVsLmNvbT4KPiBDYzogTWVlbGlzIFJvb3MgPG1yb29z QGxpbnV4LmVlPgo+IENjOiBDaHJpcyBXaWxzb24gPGNocmlzQGNocmlzLXdpbHNvbi5jby51az4K PiBGaXhlczogYWM5YjgyMzY1NTFkICgiZHJtL2k5MTU6IEludHJvZHVjZSBhIGdtYnVzIHBvd2Vy IGRvbWFpbiIpCj4gQ2M6IHN0YWJsZUB2Z2VyLmtlcm5lbC5vcmcKPiBSZWZlcmVuY2VzOiBodHRw Oi8vd3d3LnNwaW5pY3MubmV0L2xpc3RzL2ludGVsLWdmeC9tc2c4MzA3NS5odG1sCj4gVGVzdGVk LWJ5OiBNZWVsaXMgUm9vcyA8bXJvb3NAbGludXguZWU+Cj4gU2lnbmVkLW9mZi1ieTogRGFuaWVs IFZldHRlciA8ZGFuaWVsLnZldHRlckBpbnRlbC5jb20+Cj4gLS0tCj4gIGRyaXZlcnMvZ3B1L2Ry bS9pOTE1L2k5MTVfZG1hLmMgfCAxMSArKysrKy0tLS0tLQo+ICAxIGZpbGUgY2hhbmdlZCwgNSBp bnNlcnRpb25zKCspLCA2IGRlbGV0aW9ucygtKQo+IAo+IGRpZmYgLS1naXQgYS9kcml2ZXJzL2dw dS9kcm0vaTkxNS9pOTE1X2RtYS5jIGIvZHJpdmVycy9ncHUvZHJtL2k5MTUvaTkxNV9kbWEuYwo+ IGluZGV4IDk4OGEzODA2NTEyYS4uNDkwZDhiMGQ5MzFlIDEwMDY0NAo+IC0tLSBhL2RyaXZlcnMv Z3B1L2RybS9pOTE1L2k5MTVfZG1hLmMKPiArKysgYi9kcml2ZXJzL2dwdS9kcm0vaTkxNS9pOTE1 X2RtYS5jCj4gQEAgLTM5OCw3ICszOTgsNiBAQCBzdGF0aWMgaW50IGk5MTVfbG9hZF9tb2Rlc2V0 X2luaXQoc3RydWN0IGRybV9kZXZpY2UgKmRldikKPiAgCWlmIChyZXQpCj4gIAkJZ290byBjbGVh bnVwX3ZnYV9zd2l0Y2hlcm9vOwo+ICAKPiAtCWludGVsX3Bvd2VyX2RvbWFpbnNfaW5pdF9odyhk ZXZfcHJpdiwgZmFsc2UpOwo+ICAKPiAgCWludGVsX2Nzcl91Y29kZV9pbml0KGRldl9wcml2KTsK PiAgCj4gQEAgLTEwMjUsNiArMTAyNCw4IEBAIGludCBpOTE1X2RyaXZlcl9sb2FkKHN0cnVjdCBk cm1fZGV2aWNlICpkZXYsIHVuc2lnbmVkIGxvbmcgZmxhZ3MpCj4gIAo+ICAJaW50ZWxfaXJxX2lu aXQoZGV2X3ByaXYpOwo+ICAJaW50ZWxfdW5jb3JlX3Nhbml0aXplKGRldik7Cj4gKwlpbnRlbF9w b3dlcl9kb21haW5zX2luaXQoZGV2X3ByaXYpOwo+ICsJaW50ZWxfcG93ZXJfZG9tYWluc19pbml0 X2h3KGRldl9wcml2KTsKCkkgdGhpbmsgaW50ZWxfaW5pdF9kcGlvKCkgbmVlZHMgdG8gYmUgbW92 ZWQgdG9vLiBXZSBuZWVkIHRvIGtub3cgdGhlCkRQSU8gSU9TRiBwb3J0cyBiZWZvcmUgYXR0ZW1w dGluZyB0byB0YWxrIHRvIHRoZSBQSFkgKHdoaWNoIGNhbiBoYXBwZW4KZnJvbSBpbnRlbF9wb3dl cl9kb21haW5zX2luaXRfaHcoKSkuCgpJJ20gYWxzbyB3b25kZXJpbmcgd2h5IHdlJ3JlIGRvaW5n IGdtYnVzIGluaXQgdGhpcyBlYXJseS4gV2Ugc2hvdWxkbid0Cm5lZWQgaXQgdW50aWwgbW9kZXNl dCBpbml0LgoKPiAgCj4gIAkvKiBUcnkgdG8gbWFrZSBzdXJlIE1DSEJBUiBpcyBlbmFibGVkIGJl Zm9yZSBwb2tpbmcgYXQgaXQgKi8KPiAgCWludGVsX3NldHVwX21jaGJhcihkZXYpOwo+IEBAIC0x MDU3LDEyICsxMDU4LDEwIEBAIGludCBpOTE1X2RyaXZlcl9sb2FkKHN0cnVjdCBkcm1fZGV2aWNl ICpkZXYsIHVuc2lnbmVkIGxvbmcgZmxhZ3MpCj4gIAkJCWdvdG8gb3V0X2dlbV91bmxvYWQ7Cj4g IAl9Cj4gIAo+IC0JaW50ZWxfcG93ZXJfZG9tYWluc19pbml0KGRldl9wcml2KTsKPiAtCj4gIAly ZXQgPSBpOTE1X2xvYWRfbW9kZXNldF9pbml0KGRldik7Cj4gIAlpZiAocmV0IDwgMCkgewo+ICAJ CURSTV9FUlJPUigiZmFpbGVkIHRvIGluaXQgbW9kZXNldFxuIik7Cj4gLQkJZ290byBvdXRfcG93 ZXJfd2VsbDsKPiArCQlnb3RvIG91dF92Ymxhbms7Cj4gIAl9Cj4gIAo+ICAJLyoKPiBAQCAtMTA5 MSw4ICsxMDkwLDcgQEAgaW50IGk5MTVfZHJpdmVyX2xvYWQoc3RydWN0IGRybV9kZXZpY2UgKmRl diwgdW5zaWduZWQgbG9uZyBmbGFncykKPiAgCj4gIAlyZXR1cm4gMDsKPiAgCj4gLW91dF9wb3dl cl93ZWxsOgo+IC0JaW50ZWxfcG93ZXJfZG9tYWluc19maW5pKGRldl9wcml2KTsKPiArb3V0X3Zi bGFuazoKPiAgCWRybV92YmxhbmtfY2xlYW51cChkZXYpOwo+ICBvdXRfZ2VtX3VubG9hZDoKPiAg CVdBUk5fT04odW5yZWdpc3Rlcl9vb21fbm90aWZpZXIoJmRldl9wcml2LT5tbS5vb21fbm90aWZp ZXIpKTsKPiBAQCAtMTEwMyw2ICsxMTAxLDcgQEAgb3V0X2dlbV91bmxvYWQ6Cj4gIAo+ICAJaW50 ZWxfdGVhcmRvd25fZ21idXMoZGV2KTsKPiAgCWludGVsX3RlYXJkb3duX21jaGJhcihkZXYpOwo+ ICsJaW50ZWxfcG93ZXJfZG9tYWluc19maW5pKGRldl9wcml2KTsKPiAgCXBtX3Fvc19yZW1vdmVf cmVxdWVzdCgmZGV2X3ByaXYtPnBtX3Fvcyk7Cj4gIAlkZXN0cm95X3dvcmtxdWV1ZShkZXZfcHJp di0+Z3B1X2Vycm9yLmhhbmdjaGVja193cSk7Cj4gIG91dF9mcmVlZHB3cToKPiAtLSAKPiAyLjYu NAoKLS0gClZpbGxlIFN5cmrDpGzDpApJbnRlbCBPVEMKX19fX19fX19fX19fX19fX19fX19fX19f X19fX19fX19fX19fX19fX19fX19fX18KSW50ZWwtZ2Z4IG1haWxpbmcgbGlzdApJbnRlbC1nZnhA bGlzdHMuZnJlZWRlc2t0b3Aub3JnCmh0dHA6Ly9saXN0cy5mcmVlZGVza3RvcC5vcmcvbWFpbG1h bi9saXN0aW5mby9pbnRlbC1nZngK