From mboxrd@z Thu Jan 1 00:00:00 1970 From: =?utf-8?B?U8O2cmVu?= Brinkmann Subject: Re: [RFC PATCH V2 3/8] genirq: Add runtime power management support for IRQ chips Date: Tue, 12 Jan 2016 13:43:11 -0800 Message-ID: <20160112214311.GA6491@xsjsorenbubuntu> References: <1450349309-8107-1-git-send-email-jonathanh@nvidia.com> <1450349309-8107-4-git-send-email-jonathanh@nvidia.com> <569548AA.8090903@ti.com> Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: QUOTED-PRINTABLE Return-path: Content-Disposition: inline In-Reply-To: <569548AA.8090903@ti.com> Sender: linux-kernel-owner@vger.kernel.org To: Grygorii Strashko Cc: Jon Hunter , Thomas Gleixner , Jason Cooper , Marc Zyngier , Jiang Liu , Stephen Warren , Thierry Reding , Kevin Hilman , Geert Uytterhoeven , Lars-Peter Clausen , Linus Walleij , linux-kernel@vger.kernel.org, linux-tegra@vger.kernel.org, Linux PM list List-Id: linux-tegra@vger.kernel.org On Tue, 2016-01-12 at 08:40PM +0200, Grygorii Strashko wrote: > Hi Jon, >=20 > On 12/17/2015 12:48 PM, Jon Hunter wrote: > > Some IRQ chips may be located in a power domain outside of the CPU > > subsystem and hence will require device specific runtime power mana= gement. > > In order to support such IRQ chips, add a pointer for a device stru= cture > > to the irq_chip structure, and if this pointer is populated by the = IRQ > > chip driver and the flag CHIP_HAS_RPM is set, then the pm_runtime_g= et/put > > APIs for this chip will be called when an IRQ is requested/freed, > > respectively. > >=20 > > Signed-off-by: Jon Hunter >=20 > I've tried to test these patches with OMAP GPIO and I see it works, i= n general. > "In general" - because OMAP GPIO has some code which is expected to b= e used > very late during suspend or when entering deep CPUIdle states, so I c= an't use > this approach "out-of-the-box" until i find the way to sort it out. >=20 > Hope some one else can try to test it with GPIO. Soren? I try to find the person who had the failing test that triggered my involvement. That would basically just cover the case that the GPIO controller is used as IRQ controller and needs to be enabled even if no GPIO has been requested. Suspend/resume may be more difficult. We have some out-of-tree code for that. But unfortunately not 100% stable. I'll check what happens and report back. Thanks, S=C3=B6ren From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755088AbcALVne (ORCPT ); Tue, 12 Jan 2016 16:43:34 -0500 Received: from mail-bl2nam02on0079.outbound.protection.outlook.com ([104.47.38.79]:22267 "EHLO NAM02-BL2-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1753533AbcALVn3 (ORCPT ); Tue, 12 Jan 2016 16:43:29 -0500 Authentication-Results: spf=pass (sender IP is 149.199.60.83) smtp.mailfrom=xilinx.com; vger.kernel.org; dkim=none (message not signed) header.d=none;vger.kernel.org; dmarc=bestguesspass action=none header.from=xilinx.com; Date: Tue, 12 Jan 2016 13:43:11 -0800 From: =?utf-8?B?U8O2cmVu?= Brinkmann To: Grygorii Strashko CC: Jon Hunter , Thomas Gleixner , Jason Cooper , Marc Zyngier , Jiang Liu , Stephen Warren , Thierry Reding , "Kevin Hilman" , Geert Uytterhoeven , Lars-Peter Clausen , Linus Walleij , , , Linux PM list Subject: Re: [RFC PATCH V2 3/8] genirq: Add runtime power management support for IRQ chips Message-ID: <20160112214311.GA6491@xsjsorenbubuntu> References: <1450349309-8107-1-git-send-email-jonathanh@nvidia.com> <1450349309-8107-4-git-send-email-jonathanh@nvidia.com> <569548AA.8090903@ti.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <569548AA.8090903@ti.com> User-Agent: Mutt/1.5.23 (2014-03-12) X-RCIS-Action: ALLOW X-TM-AS-Product-Ver: IMSS-7.1.0.1224-8.0.0.1202-22060.005 X-TM-AS-User-Approved-Sender: Yes;Yes X-EOPAttributedMessage: 0 X-Forefront-Antispam-Report: CIP:149.199.60.83;CTRY:US;IPV:NLI;EFV:NLI;SFV:NSPM;SFS:(10009020)(6009001)(2980300002)(438002)(377424004)(479174004)(24454002)(377454003)(164054003)(199003)(189002)(85182001)(76506005)(2950100001)(77096005)(5008740100001)(47776003)(33716001)(189998001)(6806005)(2906002)(1220700001)(83506001)(85202003)(86362001)(92566002)(33656002)(1096002)(50986999)(76176999)(81156007)(19580405001)(87936001)(1076002)(4326007)(586003)(11100500001)(63266004)(19580395003)(106466001)(23676002)(57986006)(110136002)(5001960100002)(50466002)(54356999)(4001350100001)(107986001)(217873001);DIR:OUT;SFP:1101;SCL:1;SRVR:BL2NAM02HT148;H:xsj-pvapsmtpgw01;FPR:;SPF:Pass;PTR:unknown-60-83.xilinx.com;A:1;MX:1;LANG:en; X-MS-Office365-Filtering-Correlation-Id: 71c74690-faf0-4182-e00a-08d31b996717 X-Exchange-Antispam-Report-Test: UriScan:;BCL:0;PCL:0;RULEID:(8251501002);SRVR:BL2NAM02HT148;UriScan:; X-Microsoft-Antispam-PRVS: <69e4efea747e41389ccb0c7e6774f556@BL2NAM02HT148.eop-nam02.prod.protection.outlook.com> X-Exchange-Antispam-Report-CFA-Test: BCL:0;PCL:0;RULEID:(601004)(2401047)(5005006)(8121501046)(13018025)(520078)(13015025)(13017025)(10201501046)(3002001);SRVR:BL2NAM02HT148;BCL:0;PCL:0;RULEID:;SRVR:BL2NAM02HT148; X-Forefront-PRVS: 081904387B X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 Jan 2016 21:43:26.1061 (UTC) X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c;Ip=[149.199.60.83];Helo=[xsj-pvapsmtpgw01] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL2NAM02HT148 X-OriginatorOrg: xilinx.com Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, 2016-01-12 at 08:40PM +0200, Grygorii Strashko wrote: > Hi Jon, > > On 12/17/2015 12:48 PM, Jon Hunter wrote: > > Some IRQ chips may be located in a power domain outside of the CPU > > subsystem and hence will require device specific runtime power management. > > In order to support such IRQ chips, add a pointer for a device structure > > to the irq_chip structure, and if this pointer is populated by the IRQ > > chip driver and the flag CHIP_HAS_RPM is set, then the pm_runtime_get/put > > APIs for this chip will be called when an IRQ is requested/freed, > > respectively. > > > > Signed-off-by: Jon Hunter > > I've tried to test these patches with OMAP GPIO and I see it works, in general. > "In general" - because OMAP GPIO has some code which is expected to be used > very late during suspend or when entering deep CPUIdle states, so I can't use > this approach "out-of-the-box" until i find the way to sort it out. > > Hope some one else can try to test it with GPIO. Soren? I try to find the person who had the failing test that triggered my involvement. That would basically just cover the case that the GPIO controller is used as IRQ controller and needs to be enabled even if no GPIO has been requested. Suspend/resume may be more difficult. We have some out-of-tree code for that. But unfortunately not 100% stable. I'll check what happens and report back. Thanks, Sören