From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933148AbcATMt4 (ORCPT ); Wed, 20 Jan 2016 07:49:56 -0500 Received: from foss.arm.com ([217.140.101.70]:45221 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751039AbcATMty (ORCPT ); Wed, 20 Jan 2016 07:49:54 -0500 Date: Wed, 20 Jan 2016 12:49:48 +0000 From: Marc Zyngier To: Alban Bedel Cc: , Ralf Baechle , Thomas Gleixner , Jason Cooper , Alexander Couzens , Joel Porquet , "Andrew Bresticker" , Subject: Re: [PATCH 6/6] MIPS: ath79: irq: Move the CPU IRQ driver to drivers/irqchip Message-ID: <20160120124948.6917859f@sofa.wild-wind.fr.eu.org> In-Reply-To: <1447788896-15553-7-git-send-email-albeu@free.fr> References: <1447788896-15553-1-git-send-email-albeu@free.fr> <1447788896-15553-7-git-send-email-albeu@free.fr> Organization: ARM Ltd X-Mailer: Claws Mail 3.13.2-1-geb0880 (GTK+ 2.24.25; x86_64-pc-linux-gnu) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, 17 Nov 2015 20:34:56 +0100 Alban Bedel wrote: > Signed-off-by: Alban Bedel > --- > arch/mips/ath79/irq.c | 81 ++------------------------ > arch/mips/include/asm/mach-ath79/ath79.h | 1 + > drivers/irqchip/Makefile | 1 + > drivers/irqchip/irq-ath79-cpu.c | 97 ++++++++++++++++++++++++++++++++ > 4 files changed, 105 insertions(+), 75 deletions(-) > create mode 100644 drivers/irqchip/irq-ath79-cpu.c > [...] > diff --git a/drivers/irqchip/irq-ath79-cpu.c b/drivers/irqchip/irq-ath79-cpu.c > new file mode 100644 > index 0000000..befe93c > --- /dev/null > +++ b/drivers/irqchip/irq-ath79-cpu.c > @@ -0,0 +1,97 @@ > +/* > + * Atheros AR71xx/AR724x/AR913x specific interrupt handling > + * > + * Copyright (C) 2015 Alban Bedel > + * Copyright (C) 2010-2011 Jaiganesh Narayanan > + * Copyright (C) 2008-2011 Gabor Juhos > + * Copyright (C) 2008 Imre Kaloz > + * > + * Parts of this file are based on Atheros' 2.6.15/2.6.31 BSP > + * > + * This program is free software; you can redistribute it and/or modify it > + * under the terms of the GNU General Public License version 2 as published > + * by the Free Software Foundation. > + */ > + > +#include > +#include > +#include > + > +#include > +#include > + > +/* > + * The IP2/IP3 lines are tied to a PCI/WMAC/USB device. Drivers for > + * these devices typically allocate coherent DMA memory, however the > + * DMA controller may still have some unsynchronized data in the FIFO. > + * Issue a flush in the handlers to ensure that the driver sees > + * the update. > + * > + * This array map the interrupt lines to the DDR write buffer channels. > + */ > + > +static unsigned irq_wb_chan[8] = { > + -1, -1, -1, -1, -1, -1, -1, -1, > +}; > + > +asmlinkage void plat_irq_dispatch(void) > +{ > + unsigned long pending; > + int irq; > + > + pending = read_c0_status() & read_c0_cause() & ST0_IM; > + > + if (!pending) { > + spurious_interrupt(); > + return; > + } > + > + pending >>= CAUSEB_IP; > + while (pending) { > + irq = fls(pending) - 1; > + if (irq < ARRAY_SIZE(irq_wb_chan) && irq_wb_chan[irq] != -1) > + ath79_ddr_wb_flush(irq_wb_chan[irq]); > + do_IRQ(MIPS_CPU_IRQ_BASE + irq); I'm rather unfamiliar with the MIPS IRQ handling, but I'm vaguely surprised by the lack of domain. How do you unsure that the IRQ space used here doesn't clash with the one created in your "misc" irqchip? > + pending &= ~BIT(irq); > + } > +} > + > +static int __init ar79_cpu_intc_of_init( > + struct device_node *node, struct device_node *parent) > +{ > + int err, i, count; > + > + /* Fill the irq_wb_chan table */ > + count = of_count_phandle_with_args( > + node, "qca,ddr-wb-channels", "#qca,ddr-wb-channel-cells"); > + > + for (i = 0; i < count; i++) { > + struct of_phandle_args args; > + u32 irq = i; > + > + of_property_read_u32_index( > + node, "qca,ddr-wb-channel-interrupts", i, &irq); > + if (irq >= ARRAY_SIZE(irq_wb_chan)) > + continue; > + > + err = of_parse_phandle_with_args( > + node, "qca,ddr-wb-channels", > + "#qca,ddr-wb-channel-cells", > + i, &args); > + if (err) > + return err; > + > + irq_wb_chan[irq] = args.args[0]; > + } > + > + return mips_cpu_irq_of_init(node, parent); > +} > +IRQCHIP_DECLARE(ar79_cpu_intc, "qca,ar7100-cpu-intc", > + ar79_cpu_intc_of_init); > + > +void __init ath79_cpu_irq_init(unsigned irq_wb_chan2, unsigned irq_wb_chan3) > +{ > + irq_wb_chan[2] = irq_wb_chan2; > + irq_wb_chan[3] = irq_wb_chan3; > + mips_cpu_irq_init(); > +} Thanks, M. -- AAAFNRAA From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from foss.arm.com ([217.140.101.70]:55439 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S27011324AbcATMuAuXL4K (ORCPT ); Wed, 20 Jan 2016 13:50:00 +0100 Date: Wed, 20 Jan 2016 12:49:48 +0000 From: Marc Zyngier Subject: Re: [PATCH 6/6] MIPS: ath79: irq: Move the CPU IRQ driver to drivers/irqchip Message-ID: <20160120124948.6917859f@sofa.wild-wind.fr.eu.org> In-Reply-To: <1447788896-15553-7-git-send-email-albeu@free.fr> References: <1447788896-15553-1-git-send-email-albeu@free.fr> <1447788896-15553-7-git-send-email-albeu@free.fr> MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Return-Path: Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-subscribe: List-owner: List-post: List-archive: To: Alban Bedel Cc: linux-mips@linux-mips.org, Ralf Baechle , Thomas Gleixner , Jason Cooper , Alexander Couzens , Joel Porquet , Andrew Bresticker , linux-kernel@vger.kernel.org Message-ID: <20160120124948.c1uARQyz2z2s-dxTUm_3mSlN34Qs3qHVYdyqtvgOLVQ@z> On Tue, 17 Nov 2015 20:34:56 +0100 Alban Bedel wrote: > Signed-off-by: Alban Bedel > --- > arch/mips/ath79/irq.c | 81 ++------------------------ > arch/mips/include/asm/mach-ath79/ath79.h | 1 + > drivers/irqchip/Makefile | 1 + > drivers/irqchip/irq-ath79-cpu.c | 97 ++++++++++++++++++++++++++++++++ > 4 files changed, 105 insertions(+), 75 deletions(-) > create mode 100644 drivers/irqchip/irq-ath79-cpu.c > [...] > diff --git a/drivers/irqchip/irq-ath79-cpu.c b/drivers/irqchip/irq-ath79-cpu.c > new file mode 100644 > index 0000000..befe93c > --- /dev/null > +++ b/drivers/irqchip/irq-ath79-cpu.c > @@ -0,0 +1,97 @@ > +/* > + * Atheros AR71xx/AR724x/AR913x specific interrupt handling > + * > + * Copyright (C) 2015 Alban Bedel > + * Copyright (C) 2010-2011 Jaiganesh Narayanan > + * Copyright (C) 2008-2011 Gabor Juhos > + * Copyright (C) 2008 Imre Kaloz > + * > + * Parts of this file are based on Atheros' 2.6.15/2.6.31 BSP > + * > + * This program is free software; you can redistribute it and/or modify it > + * under the terms of the GNU General Public License version 2 as published > + * by the Free Software Foundation. > + */ > + > +#include > +#include > +#include > + > +#include > +#include > + > +/* > + * The IP2/IP3 lines are tied to a PCI/WMAC/USB device. Drivers for > + * these devices typically allocate coherent DMA memory, however the > + * DMA controller may still have some unsynchronized data in the FIFO. > + * Issue a flush in the handlers to ensure that the driver sees > + * the update. > + * > + * This array map the interrupt lines to the DDR write buffer channels. > + */ > + > +static unsigned irq_wb_chan[8] = { > + -1, -1, -1, -1, -1, -1, -1, -1, > +}; > + > +asmlinkage void plat_irq_dispatch(void) > +{ > + unsigned long pending; > + int irq; > + > + pending = read_c0_status() & read_c0_cause() & ST0_IM; > + > + if (!pending) { > + spurious_interrupt(); > + return; > + } > + > + pending >>= CAUSEB_IP; > + while (pending) { > + irq = fls(pending) - 1; > + if (irq < ARRAY_SIZE(irq_wb_chan) && irq_wb_chan[irq] != -1) > + ath79_ddr_wb_flush(irq_wb_chan[irq]); > + do_IRQ(MIPS_CPU_IRQ_BASE + irq); I'm rather unfamiliar with the MIPS IRQ handling, but I'm vaguely surprised by the lack of domain. How do you unsure that the IRQ space used here doesn't clash with the one created in your "misc" irqchip? > + pending &= ~BIT(irq); > + } > +} > + > +static int __init ar79_cpu_intc_of_init( > + struct device_node *node, struct device_node *parent) > +{ > + int err, i, count; > + > + /* Fill the irq_wb_chan table */ > + count = of_count_phandle_with_args( > + node, "qca,ddr-wb-channels", "#qca,ddr-wb-channel-cells"); > + > + for (i = 0; i < count; i++) { > + struct of_phandle_args args; > + u32 irq = i; > + > + of_property_read_u32_index( > + node, "qca,ddr-wb-channel-interrupts", i, &irq); > + if (irq >= ARRAY_SIZE(irq_wb_chan)) > + continue; > + > + err = of_parse_phandle_with_args( > + node, "qca,ddr-wb-channels", > + "#qca,ddr-wb-channel-cells", > + i, &args); > + if (err) > + return err; > + > + irq_wb_chan[irq] = args.args[0]; > + } > + > + return mips_cpu_irq_of_init(node, parent); > +} > +IRQCHIP_DECLARE(ar79_cpu_intc, "qca,ar7100-cpu-intc", > + ar79_cpu_intc_of_init); > + > +void __init ath79_cpu_irq_init(unsigned irq_wb_chan2, unsigned irq_wb_chan3) > +{ > + irq_wb_chan[2] = irq_wb_chan2; > + irq_wb_chan[3] = irq_wb_chan3; > + mips_cpu_irq_init(); > +} Thanks, M. -- AAAFNRAA