From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933632AbcATNIa (ORCPT ); Wed, 20 Jan 2016 08:08:30 -0500 Received: from mezzanine.sirena.org.uk ([106.187.55.193]:35566 "EHLO mezzanine.sirena.org.uk" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751205AbcATNI1 (ORCPT ); Wed, 20 Jan 2016 08:08:27 -0500 Date: Wed, 20 Jan 2016 13:08:13 +0000 From: Mark Brown To: Chen Feng Cc: lee.jones@linaro.org, lgirdwood@gmail.com, linux-kernel@vger.kernel.org, yudongbin@hisilicon.com, saberlily.xia@hisilicon.com, suzhuangluan@hisilicon.com, kong.kongxinwei@hisilicon.com, xuyiping@hisilicon.com, z.liuxinliang@hisilicon.com, weidong2@hisilicon.com, w.f@huawei.com, puck.chen@foxmail.com, shimingxing@hisilicon.com, oliver.fu@hisilicon.com, albert.lubing@hisilicon.com, chenxiang9@huawei.com, liuzixing@huawei.com, haojian.zhuang@linaro.org, qijiwen@hisilicon.com, peter.panshilin@hisilicon.com, dan.zhao@hisilicon.com, linuxarm@huawei.com, dev@lists.96boards.org Message-ID: <20160120130813.GD6588@sirena.org.uk> References: <1453185124-30809-1-git-send-email-puck.chen@hisilicon.com> <1453185124-30809-6-git-send-email-puck.chen@hisilicon.com> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="JFnjb9gtssGV5AzD" Content-Disposition: inline In-Reply-To: <1453185124-30809-6-git-send-email-puck.chen@hisilicon.com> X-Cookie: APL hackers do it in the quad. User-Agent: Mutt/1.5.24 (2015-08-30) X-SA-Exim-Connect-IP: 2a01:348:6:8808:fab::3 X-SA-Exim-Mail-From: broonie@sirena.org.uk Subject: Re: [PATCH v6 5/5] hisilicon/dts: Add hi655x pmic dts node X-SA-Exim-Version: 4.2.1 (built Mon, 26 Dec 2011 16:24:06 +0000) X-SA-Exim-Scanned: Yes (on mezzanine.sirena.org.uk) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org --JFnjb9gtssGV5AzD Content-Type: text/plain; charset=us-ascii Content-Disposition: inline On Tue, Jan 19, 2016 at 02:32:04PM +0800, Chen Feng wrote: > index 82d2488..6de9881 100644 > --- a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi > +++ b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi > + regulators { > + ldo2: ldo2@a21 { > + regulator-compatible = "LDO2"; Why are you using the legacy regulator-compatible property? No new bindings should use this. > + regulator-min-microvolt = <2500000>; > + regulator-max-microvolt = <3200000>; This is broken as it misunderstands the purpose of specifying constraints. The constraints are there to say what the safe and supported configuration is on a given board, it is not possible to provide this information safely in a general include that is used by all systems using the PMIC. Specifying the maximum voltage range for the regulators is almost guaranteed to result in at least some configurations being enabled which will not work, in the worst case this may include configurations which could physically damage the system. In general it is very unusual to include the regulators in a .dtsi since essentially all the configuration for them should be board specific. --JFnjb9gtssGV5AzD Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- Version: GnuPG v2 iQEcBAEBCAAGBQJWn4a8AAoJECTWi3JdVIfQ/yoH/308iAXxind9Qu95PEtCCbbg vXzq8q8QKxm3t2cnBzznE4q5O+PjHUk4R1SpIncHLNcC/tRJBJRJMC2Kz8MfNgqg wCvyP4VUL2OL00vZZdHBL6Ssa178JcTSo7ylKZqQAjBvQa2xN/AtN1HmxJKspnQS osMOupl7+x53LuQocnsJVo4U2BWknaTlDvpSmZYxKQ08fLgkulTBRxDJ3kMk5fPW 0KpoOMGFfXI/SqcoS5sLUoHOYQ/M3zBHp0O8L16B6UqBkAPEThJuMAy3d/BMEAu1 LANjqWSQ7tx8Q1n4/TaqfKMbDgc8TF1BYpAAWydpwV1+YVYildgNC11eXArkOUU= =Y0Lk -----END PGP SIGNATURE----- --JFnjb9gtssGV5AzD--