From mboxrd@z Thu Jan 1 00:00:00 1970 From: James Hogan Subject: Re: [PATCH v4 7/7] mips/kvm: Support MSA in MIPS KVM guests Date: Tue, 2 Feb 2016 12:39:46 +0000 Message-ID: <20160202123946.GA5038@jhogan-linux.le.imgtec.org> References: <1450435564-30720-1-git-send-email-james.hogan@imgtec.com> <1450435564-30720-8-git-send-email-james.hogan@imgtec.com> <56B07DD6.8070203@imgtec.com> Mime-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="OXfL5xGRrasGEqWY" Cc: , Paolo Bonzini , , Aurelien Jarno To: Leon Alrae Return-path: Received: from mailapp01.imgtec.com ([195.59.15.196]:47943 "EHLO imgpgp01.kl.imgtec.org" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1754362AbcBBMjs (ORCPT ); Tue, 2 Feb 2016 07:39:48 -0500 Content-Disposition: inline In-Reply-To: <56B07DD6.8070203@imgtec.com> Sender: kvm-owner@vger.kernel.org List-ID: --OXfL5xGRrasGEqWY Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: quoted-printable Hi Leon, On Tue, Feb 02, 2016 at 09:58:46AM +0000, Leon Alrae wrote: > Hi James, >=20 > On 18/12/15 10:46, James Hogan wrote: > > @@ -611,17 +664,51 @@ static int kvm_mips_get_fpu_registers(CPUState *c= s) > > restore_flush_mode(env); > > } > > =20 > > - /* Floating point registers */ > > - for (i =3D 0; i < 32; ++i) { > > - if (env->CP0_Status & (1 << CP0St_FR)) { > > - err =3D kvm_mips_get_one_ureg64(cs, KVM_REG_MIPS_FPR_6= 4(i), > > - &env->active_fpu.fpr[i].= d); > > - } else { > > - err =3D kvm_mips_get_one_ureg(cs, KVM_REG_MIPS_FPR_32(= i), > > - &env->active_fpu.fpr[i].w[FP_END= IAN_IDX]); > > + /* > > + * FPU register state is a subset of MSA vector state, so don'= t save FPU > > + * registers if we're emulating a CPU with MSA. > > + */ > > + if (!(env->CP0_Config3 & (1 << CP0C3_MSAP))) { > > + /* Floating point registers */ > > + for (i =3D 0; i < 32; ++i) { > > + if (env->CP0_Status & (1 << CP0St_FR)) { > > + err =3D kvm_mips_get_one_ureg64(cs, KVM_REG_MIPS_F= PR_64(i), > > + &env->active_fpu.fpr= [i].d); > > + } else { > > + err =3D kvm_mips_get_one_ureg(cs, KVM_REG_MIPS_FPR= _32(i), > > + &env->active_fpu.fpr[i].w[FP_ENDIA= N_IDX]); > > + } > > + if (err < 0) { > > + DPRINTF("%s: Failed to get FPR%u (%d)\n", __func__= , i, err); > > + ret =3D err; > > + } > > } > > + } > > + } > > + > > + /* Only get MSA state if we're emulating a CPU with MSA */ > > + if (env->CP0_Config3 & (1 << CP0C3_MSAP)) { > > + /* MSA Control Registers */ > > + err =3D kvm_mips_get_one_reg(cs, KVM_REG_MIPS_MSA_IR, > > + &env->msair); > > + if (err < 0) { > > + DPRINTF("%s: Failed to get MSA_IR (%d)\n", __func__, err); > > + ret =3D err; > > + } > > + err =3D kvm_mips_get_one_reg(cs, KVM_REG_MIPS_MSA_CSR, > > + &env->active_tc.msacsr); > > + if (err < 0) { > > + DPRINTF("%s: Failed to get MSA_CSR (%d)\n", __func__, err); > > + ret =3D err; > > + } >=20 > Shouldn't MSA's float_status (i.e. msa_fp_status) be restored to reflect > MSACSR? Yes, it probably should. Good spot! I can use restore_msa_fp_status(env); here, and actually the FP one above (in previous patch) can change to restore_fp_status(env); too, since it does the same thing. I've rebased and resolved the uint64 thing too, would you like a resend? Thanks James --OXfL5xGRrasGEqWY Content-Type: application/pgp-signature; name="signature.asc" Content-Description: Digital signature -----BEGIN PGP SIGNATURE----- Version: GnuPG v2 iQIcBAEBCAAGBQJWsKOSAAoJEGwLaZPeOHZ690sP/2NW7oEcmILydOG7Ow9DlSDh N9DoKirGGdJq9XZKgjwOGObmlMb1kWrBpXvI/IgWFeDhxxycWlbErn8t00wCrWFu 5ozGRAeOxBd4dLPfzwPW+pFsHemM0k9nI6copncZnJjWFzfNX3CKCx1jMFR5BZ/i 21Uh762LkTmSJ4UggBqYs9ah4MXWN6qppe8h+yDvtbGRJdpDYFo5eN35FH2v3vVH wYa4JH26t7CwPaPwLp3FQK9Y6ihbXfGYOuyjA8I/7E+roPDSdT1sSB8v9PxoxvNo p9t3aGayLSGK0KQUXgBz38f0SDdfd6WU3jxvc3cP0rPqVzoqTPu8YFpFQulM8ir6 qbX+8oeCcdLhm2+lWrYUu++KXSHeYczKipKtS5N69aOzoywOGScxKTkWuP179gvv s4oB3zV25WhFpIoQXEe8KSGMWT4oztKJBvEWWisjfynin8tX3/kykv949NpW3iHI lX+KZp//9Vco/sybnfVheNawEh3WIVPt/EagnIX0pXRaQrEBHYP7SVaWZQsW6VyP xHpSMqvyGPjd/69HeWcvZZwTPyaaH/Vl9bGbQeLsmNUgyR47byS8zX29A/HJV++L YekSteDreGM08UeUmWWSB9RcjgISL7Sr5Tv79Lrdu9g1aALjfSreXq6VO3OxKn5i ZzX6XuSZwIgMOfNRT0pV =GO3l -----END PGP SIGNATURE----- --OXfL5xGRrasGEqWY-- From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:54670) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aQaFR-0003SA-LI for qemu-devel@nongnu.org; Tue, 02 Feb 2016 07:39:58 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1aQaFM-0000sr-DK for qemu-devel@nongnu.org; Tue, 02 Feb 2016 07:39:57 -0500 Received: from mailapp01.imgtec.com ([195.59.15.196]:45074 helo=imgpgp01.kl.imgtec.org) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aQaFM-0000qq-3U for qemu-devel@nongnu.org; Tue, 02 Feb 2016 07:39:52 -0500 Date: Tue, 2 Feb 2016 12:39:46 +0000 From: James Hogan Message-ID: <20160202123946.GA5038@jhogan-linux.le.imgtec.org> References: <1450435564-30720-1-git-send-email-james.hogan@imgtec.com> <1450435564-30720-8-git-send-email-james.hogan@imgtec.com> <56B07DD6.8070203@imgtec.com> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="OXfL5xGRrasGEqWY" Content-Disposition: inline In-Reply-To: <56B07DD6.8070203@imgtec.com> Subject: Re: [Qemu-devel] [PATCH v4 7/7] mips/kvm: Support MSA in MIPS KVM guests List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Leon Alrae Cc: Paolo Bonzini , Aurelien Jarno , qemu-devel@nongnu.org, kvm@vger.kernel.org --OXfL5xGRrasGEqWY Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: quoted-printable Hi Leon, On Tue, Feb 02, 2016 at 09:58:46AM +0000, Leon Alrae wrote: > Hi James, >=20 > On 18/12/15 10:46, James Hogan wrote: > > @@ -611,17 +664,51 @@ static int kvm_mips_get_fpu_registers(CPUState *c= s) > > restore_flush_mode(env); > > } > > =20 > > - /* Floating point registers */ > > - for (i =3D 0; i < 32; ++i) { > > - if (env->CP0_Status & (1 << CP0St_FR)) { > > - err =3D kvm_mips_get_one_ureg64(cs, KVM_REG_MIPS_FPR_6= 4(i), > > - &env->active_fpu.fpr[i].= d); > > - } else { > > - err =3D kvm_mips_get_one_ureg(cs, KVM_REG_MIPS_FPR_32(= i), > > - &env->active_fpu.fpr[i].w[FP_END= IAN_IDX]); > > + /* > > + * FPU register state is a subset of MSA vector state, so don'= t save FPU > > + * registers if we're emulating a CPU with MSA. > > + */ > > + if (!(env->CP0_Config3 & (1 << CP0C3_MSAP))) { > > + /* Floating point registers */ > > + for (i =3D 0; i < 32; ++i) { > > + if (env->CP0_Status & (1 << CP0St_FR)) { > > + err =3D kvm_mips_get_one_ureg64(cs, KVM_REG_MIPS_F= PR_64(i), > > + &env->active_fpu.fpr= [i].d); > > + } else { > > + err =3D kvm_mips_get_one_ureg(cs, KVM_REG_MIPS_FPR= _32(i), > > + &env->active_fpu.fpr[i].w[FP_ENDIA= N_IDX]); > > + } > > + if (err < 0) { > > + DPRINTF("%s: Failed to get FPR%u (%d)\n", __func__= , i, err); > > + ret =3D err; > > + } > > } > > + } > > + } > > + > > + /* Only get MSA state if we're emulating a CPU with MSA */ > > + if (env->CP0_Config3 & (1 << CP0C3_MSAP)) { > > + /* MSA Control Registers */ > > + err =3D kvm_mips_get_one_reg(cs, KVM_REG_MIPS_MSA_IR, > > + &env->msair); > > + if (err < 0) { > > + DPRINTF("%s: Failed to get MSA_IR (%d)\n", __func__, err); > > + ret =3D err; > > + } > > + err =3D kvm_mips_get_one_reg(cs, KVM_REG_MIPS_MSA_CSR, > > + &env->active_tc.msacsr); > > + if (err < 0) { > > + DPRINTF("%s: Failed to get MSA_CSR (%d)\n", __func__, err); > > + ret =3D err; > > + } >=20 > Shouldn't MSA's float_status (i.e. msa_fp_status) be restored to reflect > MSACSR? Yes, it probably should. Good spot! I can use restore_msa_fp_status(env); here, and actually the FP one above (in previous patch) can change to restore_fp_status(env); too, since it does the same thing. I've rebased and resolved the uint64 thing too, would you like a resend? Thanks James --OXfL5xGRrasGEqWY Content-Type: application/pgp-signature; name="signature.asc" Content-Description: Digital signature -----BEGIN PGP SIGNATURE----- Version: GnuPG v2 iQIcBAEBCAAGBQJWsKOSAAoJEGwLaZPeOHZ690sP/2NW7oEcmILydOG7Ow9DlSDh N9DoKirGGdJq9XZKgjwOGObmlMb1kWrBpXvI/IgWFeDhxxycWlbErn8t00wCrWFu 5ozGRAeOxBd4dLPfzwPW+pFsHemM0k9nI6copncZnJjWFzfNX3CKCx1jMFR5BZ/i 21Uh762LkTmSJ4UggBqYs9ah4MXWN6qppe8h+yDvtbGRJdpDYFo5eN35FH2v3vVH wYa4JH26t7CwPaPwLp3FQK9Y6ihbXfGYOuyjA8I/7E+roPDSdT1sSB8v9PxoxvNo p9t3aGayLSGK0KQUXgBz38f0SDdfd6WU3jxvc3cP0rPqVzoqTPu8YFpFQulM8ir6 qbX+8oeCcdLhm2+lWrYUu++KXSHeYczKipKtS5N69aOzoywOGScxKTkWuP179gvv s4oB3zV25WhFpIoQXEe8KSGMWT4oztKJBvEWWisjfynin8tX3/kykv949NpW3iHI lX+KZp//9Vco/sybnfVheNawEh3WIVPt/EagnIX0pXRaQrEBHYP7SVaWZQsW6VyP xHpSMqvyGPjd/69HeWcvZZwTPyaaH/Vl9bGbQeLsmNUgyR47byS8zX29A/HJV++L YekSteDreGM08UeUmWWSB9RcjgISL7Sr5Tv79Lrdu9g1aALjfSreXq6VO3OxKn5i ZzX6XuSZwIgMOfNRT0pV =GO3l -----END PGP SIGNATURE----- --OXfL5xGRrasGEqWY--