From mboxrd@z Thu Jan 1 00:00:00 1970 From: Marek Vasut Date: Tue, 9 Feb 2016 18:30:32 +0100 Subject: [U-Boot] Problem with mounting a jffs2 partition on flash. In-Reply-To: References: <201602081712.21810.marex@denx.de> Message-ID: <201602091830.32950.marex@denx.de> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de On Tuesday, February 09, 2016 at 04:36:33 PM, Bakhvalov, Denis (Nokia - PL/Wroclaw) wrote: > Hi, Hi! > Thank you for you responses! > > @To Marek: > > It would be very helpful to see the whole boot output, not just U-Boot > > output. For example SPL output is missing. Are you using mainline U-Boot > > SPL or not ? > > Here is the output from SPL: > > U-Boot SPL 2013.01.01-svn564 (May 27 2015 - 17:58:12) > Board Type : XXXX // I changed it > Preloader Ver.: 00.01.03.00 > QSPI Access Mode: Single Access > BOARD : Altera SOCFPGA Arria V Board > CLOCK: EOSC1 clock 25000 KHz > CLOCK: EOSC2 clock 25000 KHz > CLOCK: F2S_SDR_REF clock 0 KHz > CLOCK: F2S_PER_REF clock 0 KHz > CLOCK: MPU clock 800 MHz > CLOCK: DDR clock 400 MHz > CLOCK: UART clock 100000 KHz > CLOCK: MMC clock 12500 KHz > CLOCK: QSPI clock 400000 KHz > RESET: COLD > INFO : Watchdog enabled > SDRAM: Initializing MMR registers > SDRAM: Calibrating PHY > SEQ.C: Preparing to start memory calibration > SEQ.C: CALIBRATION PASSED > SDRAM: 512 MiB > SF: Read data capture delay calibrated to 3 (0 - 7) > SF: Detected S25FL512S with page size 512, total: 67108864 That's not mainline SPL. Please use mainline SPL with mainline U-Boot. Mixing and matching various versions of U-Boot and SPL is not supported. Is there any reason why you are using non-mainline SPL ? > Here is the output from U-Boot: > > U-Boot 2013.01.01-svn578 (Jan 08 2016 - 16:02:29) > VERSION : 00.02.04.00 > U-Boot code: 01000040 -> 01049080 BSS: -> 01089908 > IRQ Stack: 0badc0de > FIQ Stack: 0badc0de > CPU : Altera SOCFPGA Platform > BOARD : XXXX // I changed it > I2C: ready > monitor len: 000898C8 > ramsize: 1F000000 > TLB table from 1eff0000 to 1eff4000 > Top of RAM usable for U-Boot at: 1eff0000 > Reserving 550k for U-Boot at: 1ef66000 > Reserving 640k for malloc() at: 1eec6000 > Reserving 32 Bytes for Board Info at: 1eec5fe0 > Reserving 128 Bytes for Global Data at: 1eec5f60 > Reserving 2048 Bytes for IRQ stack at: 1eec5760 > New Stack Pointer is: 1eec5750 > DRAM: 496 MiB > relocation Offset is: 1df65fc0 > dram_bank_mmu_setup: bank: 0 > monitor flash len: 00051840 > Now running in RAM - U-Boot at: 1ef66000 > spi_setup_slave: bus 0 cs 0 max_hz 50MHz mode 3 > spi_claim_bus: bus:0 cs:0 > cadence_qspi_apb_chipselect : chipselect 0 decode 0 > cadence_qspi_apb_config_baudrate_div: ref_clk 400000000Hz sclk 50000000Hz > Div 0x3 cadence_qspi_apb_config_baudrate_div: ref_clk 400000000Hz sclk > 1000000Hz Div 0xf cadence_qspi_apb_config_baudrate_div: ref_clk > 400000000Hz sclk 50000000Hz Div 0x3 SF: Read data capture delay calibrated > to 3 (0 - 7) > SF: Configuration Register : READ : CMD : 0x35 > spi_claim_bus: bus:0 cs:0 > cadence_qspi_apb_chipselect : chipselect 0 decode 0 > cadence_qspi_apb_config_baudrate_div: ref_clk 400000000Hz sclk 50000000Hz > Div 0x3 SF: Bank Register : WRITE : CMD : 0x17 : BANK : 0x80 > SF: Opt Area Data : READ : CMD : { 0x4b : 0x00000010 } > spi_claim_bus: bus:0 cs:0 > cadence_qspi_apb_chipselect : chipselect 0 decode 0 > cadence_qspi_apb_config_baudrate_div: ref_clk 400000000Hz sclk 50000000Hz > Div 0x3 SF: Detected S25FL512S with page size 512, total 67108864 bytes > SF: Detected S25FL512S with page size 512, total: 67108864 > READ: 0x100000 => cmd = { 0x0b 0x0010000008 } len = 0x20000 > spi_claim_bus: bus:0 cs:0 > cadence_qspi_apb_chipselect : chipselect 0 decode 0 > cadence_qspi_apb_config_baudrate_div: ref_clk 400000000Hz sclk 50000000Hz > Div 0x3 READ: 0x140000 => cmd = { 0x0b 0x0014000008 } len = 0x20000 > spi_claim_bus: bus:0 cs:0 > cadence_qspi_apb_chipselect : chipselect 0 decode 0 > cadence_qspi_apb_config_baudrate_div: ref_clk 400000000Hz sclk 50000000Hz > Div 0x3 Destroy Hash Table: 1efae2a0 table = 00000000 > Create Hash Table: N=512 > ... > // then a lot of prints setting env variables. I thought you were using mainline U-Boot, but this output is from non-mainline U-Boot now. And it also contains some odd debug prints which are not even present in the U-Boot Altera delivers. I have to admit, I am quite confused. I suppose you have Arria V SoCDK and you're trying to run U-Boot 2016.01 on it, right ? Can you load the mainline SPL and mainline U-Boot and see if that works for you? If it does not, please share the entire boot log . If you have a custom board, you will need to change the memory timing bits based on the output from Quartus . This is slightly more involved in both the altera setup and mainline setup. > > How did you install the U-Boot on your board ? > > U-boot is simply stored to flash using USB blaster from Altera. I was more interested in the procedure you used. I usually install mainline U-Boot onto a board which boots from QSPI this way: $ quartus_hps -c 1 -o PV -a 0x0 u-boot-with-spl-dtb.sfp > @To Wolfgang: > > What do you mean by "current" here? UBI/UBIFS support in U-Boot was > > actually adapted from the Linux kernel, so Linux support for UBI/UBIFS > > predates the U-Boot code by a long, long time. > > Ok, I tried to make it work with UBI/UBIFS: > > 1. From Linux env I erased partition: > flasheraseall /dev/mtd5 > 2. I'm able to work with this partition is Linux env: > ubiattach /dev/ubi_ctrl -m 5 > ubimkvol /dev/ubi0 -N myUbifs -s 35MiB > mount -t ubifs ubi0_0 /mnt > 3. But from U-Boot it is not working: > All commands as before: > U-BOOT # sf probe 0 0 0 > U-BOOT # mtdparts > ... > ---list_partitions--- > > device nor0 , # parts = 4 > #: name size offset mask_flags > 0: boot 0x00100000 0x00000000 0 > 1: bootenv 0x00080000 0x00100000 0 > 2: SomeInfo 0x01980000 0x00180000 0 > 3: jffs2spart 0x02500000 0x01b00000 0 > > U-BOOT # ubi part ubifspart > > ---mtdparts_init--- > last_ids : nor0=snor0 > env_ids : nor0=snor0 > last_parts: > mtdparts=snor0:1M(boot),512k(bootenv),26112k(SomeInfo),-(ubifspart) > env_parts : > mtdparts=snor0:1M(boot),512k(bootenv),26112k(SomeInfo),-(ubifspart) > > last_partition : nor0,0 > env_partition : nor0,0 > --- find_dev_and_part --- > id = ubifspart > --- find_dev_and_part --- > id = ubifspart > Creating 1 MTD partitions on "nor0": > 0x000001b00000-0x000004000000 : "mtd=3" > raise: Signal # 8 caught > raise: Signal # 8 caught > UBI: attaching mtd1 to ubi0 > raise: Signal # 8 caught > UBI: physical eraseblock size: 0 bytes (0 KiB) > UBI: logical eraseblock size: -128 bytes > UBI: smallest flash I/O unit: 1 > UBI: VID header offset: 64 (aligned 64) > UBI: data offset: 128 > UBI: empty MTD device detected > UBI: create volume table (copy #1) > UBI error: ubi_scan_get_free_peb: no eraseblocks found > UBI error: ubi_init: cannot attach mtd1 > UBI error: ubi_init: UBI error: cannot initialize UBI, error -28 > UBI init error 28 > Command failed, result=28U-BOOT # > > I'm confused about those prints: > raise: Signal # 8 caught > There are just so much of them... Even when executing sf probe command. Is this u-boot 2016.01 or the ancient version provided by Altera please ? > > Do you mean you are using a prehistoric Linux kernel version? > > No, Linux version is 3.10.31. Is there any reason why you don't use Linux 4.4 ? There are customers who are using this on socfpga just fine, including FPGA manager and DT overlays to deal with the FPGA part. > > It appears it is hanging in the DRAM initialization phase. This is a > > very common issue. Please make sure your memory configuration is > > correct. > > You can deal with this later; first you need to have the system > > running at all. You should focus on this first. > > This is what I'm going to do next. I'm looking forward to your findings!