From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932705AbcBIUHY (ORCPT ); Tue, 9 Feb 2016 15:07:24 -0500 Received: from foss.arm.com ([217.140.101.70]:43234 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932149AbcBIUHW (ORCPT ); Tue, 9 Feb 2016 15:07:22 -0500 Date: Tue, 9 Feb 2016 20:07:15 +0000 From: Marc Zyngier To: David Daney Cc: David Daney , Will Deacon , , Mark Rutland , Catalin Marinas , , Andrew Pinski , David Daney Subject: Re: [PATCH] arm64: Add workaround for Cavium erratum 27456 Message-ID: <20160209200715.22487785@arm.com> In-Reply-To: <56BA450E.50109@caviumnetworks.com> References: <1455046156-10582-1-git-send-email-ddaney.cavm@gmail.com> <20160209195222.0882d7f7@arm.com> <56BA450E.50109@caviumnetworks.com> Organization: ARM Ltd X-Mailer: Claws Mail 3.11.1 (GTK+ 2.24.25; arm-unknown-linux-gnueabihf) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, 9 Feb 2016 11:59:10 -0800 David Daney wrote: > On 02/09/2016 11:52 AM, Marc Zyngier wrote: > > On Tue, 9 Feb 2016 11:29:16 -0800 > > David Daney wrote: > > > > Hi David, > > > >> From: Andrew Pinski > >> > >> On ThunderX T88 pass 1.x through 2.1 parts, broadcast TLBI > >> instructions may cause the icache to become invalid if it contains > >> data for a non-current ASID. > >> > >> This patch implements the workaround (which flushes the local icache > >> when switching the mm) by using code patching. > >> > >> Signed-off-by: Andrew Pinski > >> Signed-off-by: David Daney > >> --- > >> arch/arm64/Kconfig | 11 +++++++++++ > >> arch/arm64/include/asm/cpufeature.h | 3 ++- > >> arch/arm64/kernel/cpu_errata.c | 9 +++++++++ > >> arch/arm64/mm/proc.S | 12 ++++++++++++ > >> 4 files changed, 34 insertions(+), 1 deletion(-) > > > > It would be good to update Documentation/arm64/silicon-errata.txt to > > reflect the fact that there is a workaround available for this erratum. > > Would you prefer a separate patch for that, or should I roll it into > this one and resubmit? It'd feel more logical to keep it all together, but I'll leave that decision to Catalin and Will. Thanks, M. -- Jazz is not dead. It just smells funny. From mboxrd@z Thu Jan 1 00:00:00 1970 From: marc.zyngier@arm.com (Marc Zyngier) Date: Tue, 9 Feb 2016 20:07:15 +0000 Subject: [PATCH] arm64: Add workaround for Cavium erratum 27456 In-Reply-To: <56BA450E.50109@caviumnetworks.com> References: <1455046156-10582-1-git-send-email-ddaney.cavm@gmail.com> <20160209195222.0882d7f7@arm.com> <56BA450E.50109@caviumnetworks.com> Message-ID: <20160209200715.22487785@arm.com> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On Tue, 9 Feb 2016 11:59:10 -0800 David Daney wrote: > On 02/09/2016 11:52 AM, Marc Zyngier wrote: > > On Tue, 9 Feb 2016 11:29:16 -0800 > > David Daney wrote: > > > > Hi David, > > > >> From: Andrew Pinski > >> > >> On ThunderX T88 pass 1.x through 2.1 parts, broadcast TLBI > >> instructions may cause the icache to become invalid if it contains > >> data for a non-current ASID. > >> > >> This patch implements the workaround (which flushes the local icache > >> when switching the mm) by using code patching. > >> > >> Signed-off-by: Andrew Pinski > >> Signed-off-by: David Daney > >> --- > >> arch/arm64/Kconfig | 11 +++++++++++ > >> arch/arm64/include/asm/cpufeature.h | 3 ++- > >> arch/arm64/kernel/cpu_errata.c | 9 +++++++++ > >> arch/arm64/mm/proc.S | 12 ++++++++++++ > >> 4 files changed, 34 insertions(+), 1 deletion(-) > > > > It would be good to update Documentation/arm64/silicon-errata.txt to > > reflect the fact that there is a workaround available for this erratum. > > Would you prefer a separate patch for that, or should I roll it into > this one and resubmit? It'd feel more logical to keep it all together, but I'll leave that decision to Catalin and Will. Thanks, M. -- Jazz is not dead. It just smells funny.