From mboxrd@z Thu Jan  1 00:00:00 1970
From: will.deacon@arm.com (Will Deacon)
Date: Thu, 25 Feb 2016 16:46:31 +0000
Subject: [PATCH v5sub2 1/8] arm64: add support for module PLTs
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To: linux-arm-kernel@lists.infradead.org
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On Thu, Feb 25, 2016 at 05:43:35PM +0100, Ard Biesheuvel wrote:
> On 25 February 2016 at 17:42, Will Deacon <will.deacon@arm.com> wrote:
> > On Thu, Feb 25, 2016 at 05:33:25PM +0100, Ard Biesheuvel wrote:
> >> AFAIK, gcc never uses x18 (the platform register) so we may be able to
> >> use that instead. We'd need confirmation from the toolchain guys,
> >> though ...
> >
> > In fact, a better thing to do is probably for the atomic code to
> > save/restore those register explicitly and then remove them from the
> > cflags above.
> >
> > I'll try hacking something together...
> >
> 
> That would be more correct, indeed. Also, the PLT can only use br
> <reg> so it will always enter the callee with the preserved value
> stacked, and so the callee needs to be modified in any case.

Wait -- why does the callee need to be modified here? It has no idea
about whether or not it was invoked via a PLT.

Also, can I rely on the PLT not clobbering the condition code?

Will