From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753169AbcCGJyM (ORCPT ); Mon, 7 Mar 2016 04:54:12 -0500 Received: from foss.arm.com ([217.140.101.70]:53978 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753077AbcCGJui (ORCPT ); Mon, 7 Mar 2016 04:50:38 -0500 Date: Mon, 7 Mar 2016 09:50:21 +0000 From: Marc Zyngier To: Minghuan Lian Cc: , , Thomas Gleixner , Jason Cooper , Roy Zang , Mingkai Hu , Stuart Yoder , Yang-Leo Li , Rob Herring , Mark Rutland Subject: Re: [PATCH 2/2 v5] irqchip/Layerscape: Add SCFG MSI controller support Message-ID: <20160307095021.7f9f7484@arm.com> In-Reply-To: <1457321782-3245-2-git-send-email-Minghuan.Lian@nxp.com> References: <1457321782-3245-1-git-send-email-Minghuan.Lian@nxp.com> <1457321782-3245-2-git-send-email-Minghuan.Lian@nxp.com> Organization: ARM Ltd X-Mailer: Claws Mail 3.11.1 (GTK+ 2.24.25; arm-unknown-linux-gnueabihf) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, 7 Mar 2016 11:36:22 +0800 Minghuan Lian wrote: > Some kind of NXP Layerscape SoC provides a MSI > implementation which uses two SCFG registers MSIIR and > MSIR to support 32 MSI interrupts for each PCIe controller. > The patch is to support it. > > Signed-off-by: Minghuan Lian Acked-by: Marc Zyngier The DT binding still needs an Ack from the DT maintainers though (cc'd). M. -- Jazz is not dead. It just smells funny. From mboxrd@z Thu Jan 1 00:00:00 1970 From: marc.zyngier@arm.com (Marc Zyngier) Date: Mon, 7 Mar 2016 09:50:21 +0000 Subject: [PATCH 2/2 v5] irqchip/Layerscape: Add SCFG MSI controller support In-Reply-To: <1457321782-3245-2-git-send-email-Minghuan.Lian@nxp.com> References: <1457321782-3245-1-git-send-email-Minghuan.Lian@nxp.com> <1457321782-3245-2-git-send-email-Minghuan.Lian@nxp.com> Message-ID: <20160307095021.7f9f7484@arm.com> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On Mon, 7 Mar 2016 11:36:22 +0800 Minghuan Lian wrote: > Some kind of NXP Layerscape SoC provides a MSI > implementation which uses two SCFG registers MSIIR and > MSIR to support 32 MSI interrupts for each PCIe controller. > The patch is to support it. > > Signed-off-by: Minghuan Lian Acked-by: Marc Zyngier The DT binding still needs an Ack from the DT maintainers though (cc'd). M. -- Jazz is not dead. It just smells funny.