From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754409AbcCNEFD (ORCPT ); Mon, 14 Mar 2016 00:05:03 -0400 Received: from mx1.redhat.com ([209.132.183.28]:44417 "EHLO mx1.redhat.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750740AbcCNEE7 (ORCPT ); Mon, 14 Mar 2016 00:04:59 -0400 Date: Mon, 14 Mar 2016 09:34:55 +0530 From: Pratyush Anand To: Marc Zyngier Cc: David Long , Catalin Marinas , Will Deacon , Sandeepa Prabhu , William Cohen , Steve Capper , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Dave P Martin , Mark Rutland , Robin Murphy , Ard Biesheuvel , Jens Wiklander , Christoffer Dall , Alex =?iso-8859-1?Q?Benn=E9e?= , Yang Shi , Greg Kroah-Hartman , Viresh Kumar , "Suzuki K. Poulose" , Kees Cook , Zi Shen Lim , John Blackwood , Feng Kan , Balamurugan Shanmugam , James Morse , Vladimir Murzin , Mark Salyzyn , Petr Mladek , Andrew Morton , Mark Brown Subject: Re: [PATCH v11 4/9] arm64: add conditional instruction simulation support Message-ID: <20160314040455.GB6584@dhcppc6.redhat.com> References: <1457501543-24197-1-git-send-email-dave.long@linaro.org> <1457501543-24197-5-git-send-email-dave.long@linaro.org> <20160313120903.54b0c8f2@arm.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20160313120903.54b0c8f2@arm.com> User-Agent: Mutt/1.5.24 (2015-08-30) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 13/03/2016:12:09:03 PM, Marc Zyngier wrote: > On Wed, 9 Mar 2016 00:32:18 -0500 > David Long wrote: > > > +pstate_check_t * const opcode_condition_checks[16] = { > > + __check_eq, __check_ne, __check_cs, __check_cc, > > + __check_mi, __check_pl, __check_vs, __check_vc, > > + __check_hi, __check_ls, __check_ge, __check_lt, > > + __check_gt, __check_le, __check_al, __check_al > > The very last entry seems wrong, or is at least the opposite of what > the current code has. It should be something called __check_nv(), and > always return false (condition code NEVER). May be __check_nv() name is more appropriate as per definition, but shouldn't it still return true, because TRM says: "The condition code NV exists only to provide a valid disassembly of the 0b1111 encoding, otherwise its behavior is identical to AL" ~Pratyush From mboxrd@z Thu Jan 1 00:00:00 1970 From: panand@redhat.com (Pratyush Anand) Date: Mon, 14 Mar 2016 09:34:55 +0530 Subject: [PATCH v11 4/9] arm64: add conditional instruction simulation support In-Reply-To: <20160313120903.54b0c8f2@arm.com> References: <1457501543-24197-1-git-send-email-dave.long@linaro.org> <1457501543-24197-5-git-send-email-dave.long@linaro.org> <20160313120903.54b0c8f2@arm.com> Message-ID: <20160314040455.GB6584@dhcppc6.redhat.com> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On 13/03/2016:12:09:03 PM, Marc Zyngier wrote: > On Wed, 9 Mar 2016 00:32:18 -0500 > David Long wrote: > > > +pstate_check_t * const opcode_condition_checks[16] = { > > + __check_eq, __check_ne, __check_cs, __check_cc, > > + __check_mi, __check_pl, __check_vs, __check_vc, > > + __check_hi, __check_ls, __check_ge, __check_lt, > > + __check_gt, __check_le, __check_al, __check_al > > The very last entry seems wrong, or is at least the opposite of what > the current code has. It should be something called __check_nv(), and > always return false (condition code NEVER). May be __check_nv() name is more appropriate as per definition, but shouldn't it still return true, because TRM says: "The condition code NV exists only to provide a valid disassembly of the 0b1111 encoding, otherwise its behavior is identical to AL" ~Pratyush