From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933702AbcCNHib (ORCPT ); Mon, 14 Mar 2016 03:38:31 -0400 Received: from foss.arm.com ([217.140.101.70]:57705 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750883AbcCNHiX (ORCPT ); Mon, 14 Mar 2016 03:38:23 -0400 Date: Mon, 14 Mar 2016 07:38:03 +0000 From: Marc Zyngier To: Pratyush Anand Cc: David Long , Catalin Marinas , Will Deacon , Sandeepa Prabhu , William Cohen , "Steve Capper" , , , Dave P Martin , "Mark Rutland" , Robin Murphy , "Ard Biesheuvel" , Jens Wiklander , Christoffer Dall , Alex =?ISO-8859-1?Q?Benn?= =?ISO-8859-1?Q?=E9e?= , Yang Shi , Greg Kroah-Hartman , Viresh Kumar , "Suzuki K. Poulose" , Kees Cook , Zi Shen Lim , John Blackwood , Feng Kan , Balamurugan Shanmugam , James Morse , Vladimir Murzin , "Mark Salyzyn" , Petr Mladek , Andrew Morton , Mark Brown Subject: Re: [PATCH v11 4/9] arm64: add conditional instruction simulation support Message-ID: <20160314073803.22c90d69@arm.com> In-Reply-To: <20160314040455.GB6584@dhcppc6.redhat.com> References: <1457501543-24197-1-git-send-email-dave.long@linaro.org> <1457501543-24197-5-git-send-email-dave.long@linaro.org> <20160313120903.54b0c8f2@arm.com> <20160314040455.GB6584@dhcppc6.redhat.com> Organization: ARM Ltd X-Mailer: Claws Mail 3.11.1 (GTK+ 2.24.25; arm-unknown-linux-gnueabihf) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, 14 Mar 2016 09:34:55 +0530 Pratyush Anand wrote: Hi Pratyush, > On 13/03/2016:12:09:03 PM, Marc Zyngier wrote: > > On Wed, 9 Mar 2016 00:32:18 -0500 > > David Long wrote: > > > > > +pstate_check_t * const opcode_condition_checks[16] = { > > > + __check_eq, __check_ne, __check_cs, __check_cc, > > > + __check_mi, __check_pl, __check_vs, __check_vc, > > > + __check_hi, __check_ls, __check_ge, __check_lt, > > > + __check_gt, __check_le, __check_al, __check_al > > > > The very last entry seems wrong, or is at least the opposite of what > > the current code has. It should be something called __check_nv(), and > > always return false (condition code NEVER). > > May be __check_nv() name is more appropriate as per definition, but shouldn't it > still return true, because TRM says: > "The condition code NV exists only to provide a valid disassembly of the 0b1111 > encoding, otherwise its behavior is identical to AL" Indeed, I missed that. But this interpretation is for the A64 instruction set, and this array is also used by the new arm32_check_condition. The condition code table for A32 seems to completely ignore the 0b1111 code (there is simply no entry for it), and it is only in the ConditionHolds pseudocode that you can see how this is actually special-cased. So I'm fine leaving the code as it is, but a comment and a pointer to the ARMv8 ARM wouldn't go amiss. Thanks, M. -- Jazz is not dead. It just smells funny. From mboxrd@z Thu Jan 1 00:00:00 1970 From: marc.zyngier@arm.com (Marc Zyngier) Date: Mon, 14 Mar 2016 07:38:03 +0000 Subject: [PATCH v11 4/9] arm64: add conditional instruction simulation support In-Reply-To: <20160314040455.GB6584@dhcppc6.redhat.com> References: <1457501543-24197-1-git-send-email-dave.long@linaro.org> <1457501543-24197-5-git-send-email-dave.long@linaro.org> <20160313120903.54b0c8f2@arm.com> <20160314040455.GB6584@dhcppc6.redhat.com> Message-ID: <20160314073803.22c90d69@arm.com> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On Mon, 14 Mar 2016 09:34:55 +0530 Pratyush Anand wrote: Hi Pratyush, > On 13/03/2016:12:09:03 PM, Marc Zyngier wrote: > > On Wed, 9 Mar 2016 00:32:18 -0500 > > David Long wrote: > > > > > +pstate_check_t * const opcode_condition_checks[16] = { > > > + __check_eq, __check_ne, __check_cs, __check_cc, > > > + __check_mi, __check_pl, __check_vs, __check_vc, > > > + __check_hi, __check_ls, __check_ge, __check_lt, > > > + __check_gt, __check_le, __check_al, __check_al > > > > The very last entry seems wrong, or is at least the opposite of what > > the current code has. It should be something called __check_nv(), and > > always return false (condition code NEVER). > > May be __check_nv() name is more appropriate as per definition, but shouldn't it > still return true, because TRM says: > "The condition code NV exists only to provide a valid disassembly of the 0b1111 > encoding, otherwise its behavior is identical to AL" Indeed, I missed that. But this interpretation is for the A64 instruction set, and this array is also used by the new arm32_check_condition. The condition code table for A32 seems to completely ignore the 0b1111 code (there is simply no entry for it), and it is only in the ConditionHolds pseudocode that you can see how this is actually special-cased. So I'm fine leaving the code as it is, but a comment and a pointer to the ARMv8 ARM wouldn't go amiss. Thanks, M. -- Jazz is not dead. It just smells funny.