From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:39387) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ag42i-0007SH-Na for qemu-devel@nongnu.org; Wed, 16 Mar 2016 01:30:50 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ag42f-00032x-Fh for qemu-devel@nongnu.org; Wed, 16 Mar 2016 01:30:48 -0400 Date: Wed, 16 Mar 2016 16:19:33 +1100 From: David Gibson Message-ID: <20160316051933.GE9032@voom> References: <1457672078-17307-1-git-send-email-bharata@linux.vnet.ibm.com> <1457672078-17307-8-git-send-email-bharata@linux.vnet.ibm.com> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha1; protocol="application/pgp-signature"; boundary="ZvvH1QDaOFG4lOZN" Content-Disposition: inline In-Reply-To: <1457672078-17307-8-git-send-email-bharata@linux.vnet.ibm.com> Subject: Re: [Qemu-devel] [RFC PATCH v2 7/9] spapr: CPU hotplug support List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Bharata B Rao Cc: mjrosato@linux.vnet.ibm.com, agraf@suse.de, thuth@redhat.com, pkrempa@redhat.com, ehabkost@redhat.com, aik@ozlabs.ru, qemu-devel@nongnu.org, armbru@redhat.com, borntraeger@de.ibm.com, qemu-ppc@nongnu.org, pbonzini@redhat.com, imammedo@redhat.com, afaerber@suse.de, mdroth@linux.vnet.ibm.com --ZvvH1QDaOFG4lOZN Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Fri, Mar 11, 2016 at 10:24:36AM +0530, Bharata B Rao wrote: > Set up device tree entries for the hotplugged CPU core and use the > exising RTAS event logging infrastructure to send CPU hotplug notification > to the guest. >=20 > Signed-off-by: Bharata B Rao > --- > hw/ppc/spapr.c | 64 +++++++++++++++++++++++++++++++++++= +++ > hw/ppc/spapr_cpu_core.c | 69 +++++++++++++++++++++++++++++++++++= ++++++ > hw/ppc/spapr_events.c | 3 ++ > hw/ppc/spapr_rtas.c | 24 ++++++++++++++ > include/hw/ppc/spapr.h | 2 ++ > include/hw/ppc/spapr_cpu_core.h | 2 ++ > 6 files changed, 164 insertions(+) >=20 > diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c > index cffe8c8..822c87d 100644 > --- a/hw/ppc/spapr.c > +++ b/hw/ppc/spapr.c > @@ -603,6 +603,18 @@ static void spapr_populate_cpu_dt(CPUState *cs, void= *fdt, int offset, > size_t page_sizes_prop_size; > uint32_t vcpus_per_socket =3D smp_threads * smp_cores; > uint32_t pft_size_prop[] =3D {0, cpu_to_be32(spapr->htab_shift)}; > + sPAPRMachineClass *smc =3D SPAPR_MACHINE_GET_CLASS(qdev_get_machine(= )); > + sPAPRDRConnector *drc; > + sPAPRDRConnectorClass *drck; > + int drc_index; > + > + if (smc->dr_cpu_enabled) { > + drc =3D spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_CPU, in= dex); > + g_assert(drc); Small nit: rather than asserting here it might be simpler to just check for drc !=3D NULL instead of checking smc->dr_cpu_enabled. That should have the same effect for now, and will be correct if we ever have some pluggable and some non-pluggable CPUs... > + drck =3D SPAPR_DR_CONNECTOR_GET_CLASS(drc); > + drc_index =3D drck->get_index(drc); > + _FDT((fdt_setprop_cell(fdt, offset, "ibm,my-drc-index", drc_inde= x))); > + } > =20 > /* Note: we keep CI large pages off for now because a 64K capable gu= est > * provisioned with large pages might otherwise try to map a qemu > @@ -987,6 +999,16 @@ static void spapr_finalize_fdt(sPAPRMachineState *sp= apr, > _FDT(spapr_drc_populate_dt(fdt, 0, NULL, SPAPR_DR_CONNECTOR_TYPE= _LMB)); > } > =20 > + if (smc->dr_cpu_enabled) { > + int offset =3D fdt_path_offset(fdt, "/cpus"); > + ret =3D spapr_drc_populate_dt(fdt, offset, NULL, > + SPAPR_DR_CONNECTOR_TYPE_CPU); > + if (ret < 0) { > + error_report("Couldn't set up CPU DR device tree properties"= ); > + exit(1); > + } > + } > + > _FDT((fdt_pack(fdt))); > =20 > if (fdt_totalsize(fdt) > FDT_MAX_SIZE) { > @@ -1622,6 +1644,8 @@ static void spapr_boot_set(void *opaque, const char= *boot_device, > void spapr_cpu_init(sPAPRMachineState *spapr, PowerPCCPU *cpu, Error **e= rrp) > { > CPUPPCState *env =3D &cpu->env; > + CPUState *cs =3D CPU(cpu); > + int i; > =20 > /* Set time-base frequency to 512 MHz */ > cpu_ppc_tb_init(env, TIMEBASE_FREQ); > @@ -1646,6 +1670,14 @@ void spapr_cpu_init(sPAPRMachineState *spapr, Powe= rPCCPU *cpu, Error **errp) > } > } > =20 > + /* Set NUMA node for the added CPUs */ > + for (i =3D 0; i < nb_numa_nodes; i++) { > + if (test_bit(cs->cpu_index, numa_info[i].node_cpu)) { > + cs->numa_node =3D i; > + break; > + } > + } > + > xics_cpu_setup(spapr->icp, cpu); > =20 > qemu_register_reset(spapr_cpu_reset, cpu); > @@ -1824,6 +1856,11 @@ static void ppc_spapr_init(MachineState *machine) > =20 > for (i =3D 0; i < spapr_max_cores; i++) { > int core_dt_id =3D i * smt; > + sPAPRDRConnector *drc =3D > + spapr_dr_connector_new(OBJECT(spapr), > + SPAPR_DR_CONNECTOR_TYPE_CPU, core= _dt_id); > + > + qemu_register_reset(spapr_drc_reset, drc); =2E..at least it will be if you make construction of the DRC object conditional on dr_cpu_enabled. > if (i < spapr_cores) { > Object *core =3D object_new(TYPE_SPAPR_CPU_CORE); > @@ -2246,6 +2283,27 @@ out: > error_propagate(errp, local_err); > } > =20 > +void *spapr_populate_hotplug_cpu_dt(DeviceState *dev, CPUState *cs, > + int *fdt_offset, sPAPRMachineState *= spapr) > +{ > + PowerPCCPU *cpu =3D POWERPC_CPU(cs); > + DeviceClass *dc =3D DEVICE_GET_CLASS(cs); > + int id =3D ppc_get_vcpu_dt_id(cpu); > + void *fdt; > + int offset, fdt_size; > + char *nodename; > + > + fdt =3D create_device_tree(&fdt_size); > + nodename =3D g_strdup_printf("%s@%x", dc->fw_name, id); > + offset =3D fdt_add_subnode(fdt, 0, nodename); > + > + spapr_populate_cpu_dt(cs, fdt, offset, spapr); > + g_free(nodename); > + > + *fdt_offset =3D offset; > + return fdt; > +} > + > static void spapr_machine_device_plug(HotplugHandler *hotplug_dev, > DeviceState *dev, Error **errp) > { > @@ -2286,6 +2344,12 @@ static void spapr_machine_device_plug(HotplugHandl= er *hotplug_dev, > } > =20 > spapr_memory_plug(hotplug_dev, dev, node, errp); > + } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { > + if (!smc->dr_cpu_enabled && dev->hotplugged) { > + error_setg(errp, "CPU hotplug not supported for this machine= "); > + return; > + } > + spapr_core_plug(hotplug_dev, dev, errp); > } > } > =20 > diff --git a/hw/ppc/spapr_cpu_core.c b/hw/ppc/spapr_cpu_core.c > index 8c6d71d..db8de32 100644 > --- a/hw/ppc/spapr_cpu_core.c > +++ b/hw/ppc/spapr_cpu_core.c > @@ -15,6 +15,75 @@ > #include > #include "target-ppc/kvm_ppc.h" > =20 > +void spapr_core_plug(HotplugHandler *hotplug_dev, DeviceState *dev, > + Error **errp) > +{ > + sPAPRMachineClass *smc =3D SPAPR_MACHINE_GET_CLASS(qdev_get_machine(= )); > + sPAPRMachineState *spapr =3D SPAPR_MACHINE(qdev_get_machine()); > + sPAPRCPUCore *core =3D SPAPR_CPU_CORE(OBJECT(dev)); > + CPUState *cs =3D CPU(&core->threads[0]); > + sPAPRDRConnector *drc; > + sPAPRDRConnectorClass *drck; > + Error *local_err =3D NULL; > + void *fdt =3D NULL; > + int fdt_offset =3D 0; > + int core_id, core_dt_id; > + int smt =3D kvmppc_smt_threads(); > + > + /* TODO: Should we cache core_id in sPAPRCPUCore ? */ > + core_dt_id =3D object_property_get_int(OBJECT(dev), "core", > &local_err); As Igor pointed out elsewhere you should just be able to do CPU_CORE(dev)->core. > + if (local_err) { > + error_propagate(errp, local_err); > + return; > + } > + drc =3D spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_CPU, core_d= t_id); > + core_id =3D core_dt_id / smt; > + spapr->cores[core_id] =3D OBJECT(dev); > + > + if (!smc->dr_cpu_enabled) { > + /* > + * This is a cold plugged CPU core but the machine doesn't suppo= rt > + * DR. So skip the hotplug path ensuring that the core is brought > + * up online with out an associated DR connector. > + */ > + return; > + } > + > + g_assert(drc); > + > + /* > + * Setup CPU DT entries only for hotplugged CPUs. For boot time or > + * coldplugged CPUs DT entries are setup in spapr_finalize_fdt(). > + */ > + if (dev->hotplugged) { > + fdt =3D spapr_populate_hotplug_cpu_dt(dev, cs, &fdt_offset, spap= r); > + dev->hotplugged =3D true; > + } > + > + drck =3D SPAPR_DR_CONNECTOR_GET_CLASS(drc); > + drck->attach(drc, dev, fdt, fdt_offset, !dev->hotplugged, &local_err= ); > + if (local_err) { > + g_free(fdt); > + spapr->cores[core_id] =3D NULL; > + error_propagate(errp, local_err); > + return; > + } > + > + if (dev->hotplugged) { > + /* > + * Send hotplug notification interrupt to the guest only in case > + * of hotplugged CPUs. > + */ > + spapr_hotplug_req_add_by_index(drc); > + } else { > + /* > + * Set the right DRC states for cold plugged CPU. > + */ > + drck->set_allocation_state(drc, SPAPR_DR_ALLOCATION_STATE_USABLE= ); > + drck->set_isolation_state(drc, SPAPR_DR_ISOLATION_STATE_UNISOLAT= ED); > + } > +} > + > static void spapr_cpu_core_create_threads(sPAPRCPUCore *core, int thread= s, > Error **errp) > { > diff --git a/hw/ppc/spapr_events.c b/hw/ppc/spapr_events.c > index 39f4682..10340e1 100644 > --- a/hw/ppc/spapr_events.c > +++ b/hw/ppc/spapr_events.c > @@ -437,6 +437,9 @@ static void spapr_hotplug_req_event(uint8_t hp_id, ui= nt8_t hp_action, > case SPAPR_DR_CONNECTOR_TYPE_LMB: > hp->hotplug_type =3D RTAS_LOG_V6_HP_TYPE_MEMORY; > break; > + case SPAPR_DR_CONNECTOR_TYPE_CPU: > + hp->hotplug_type =3D RTAS_LOG_V6_HP_TYPE_CPU; > + break; > default: > /* we shouldn't be signaling hotplug events for resources > * that don't support them > diff --git a/hw/ppc/spapr_rtas.c b/hw/ppc/spapr_rtas.c > index b7c5ebd..cc0369e 100644 > --- a/hw/ppc/spapr_rtas.c > +++ b/hw/ppc/spapr_rtas.c > @@ -34,6 +34,7 @@ > =20 > #include "hw/ppc/spapr.h" > #include "hw/ppc/spapr_vio.h" > +#include "hw/ppc/ppc.h" > #include "qapi-event.h" > #include "hw/boards.h" > =20 > @@ -161,6 +162,27 @@ static void rtas_query_cpu_stopped_state(PowerPCCPU = *cpu_, > rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); > } > =20 > +/* > + * Set the timebase offset of the CPU to that of first CPU. > + * This helps hotplugged CPU to have the correct timebase offset. > + */ > +static void spapr_cpu_update_tb_offset(PowerPCCPU *cpu) > +{ > + PowerPCCPU *fcpu =3D POWERPC_CPU(first_cpu); > + > + cpu->env.tb_env->tb_offset =3D fcpu->env.tb_env->tb_offset; > +} > + > +static void spapr_cpu_set_endianness(PowerPCCPU *cpu) > +{ > + PowerPCCPU *fcpu =3D POWERPC_CPU(first_cpu); > + PowerPCCPUClass *pcc =3D POWERPC_CPU_GET_CLASS(fcpu); > + > + if (!pcc->interrupts_big_endian(fcpu)) { > + cpu->env.spr[SPR_LPCR] |=3D LPCR_ILE; > + } > +} > + > static void rtas_start_cpu(PowerPCCPU *cpu_, sPAPRMachineState *spapr, > uint32_t token, uint32_t nargs, > target_ulong args, > @@ -197,6 +219,8 @@ static void rtas_start_cpu(PowerPCCPU *cpu_, sPAPRMac= hineState *spapr, > env->nip =3D start; > env->gpr[3] =3D r3; > cs->halted =3D 0; > + spapr_cpu_set_endianness(cpu); > + spapr_cpu_update_tb_offset(cpu); > =20 > qemu_cpu_kick(cs); > =20 > diff --git a/include/hw/ppc/spapr.h b/include/hw/ppc/spapr.h > index c099c3c..8957072 100644 > --- a/include/hw/ppc/spapr.h > +++ b/include/hw/ppc/spapr.h > @@ -589,6 +589,8 @@ void spapr_hotplug_req_remove_by_count(sPAPRDRConnect= orType drc_type, > uint32_t count); > void spapr_cpu_init(sPAPRMachineState *spapr, PowerPCCPU *cpu, Error **e= rrp); > void spapr_cpu_reset(void *opaque); > +void *spapr_populate_hotplug_cpu_dt(DeviceState *dev, CPUState *cs, > + int *fdt_offset, sPAPRMachineState *= spapr); > =20 > /* rtas-configure-connector state */ > struct sPAPRConfigureConnectorState { > diff --git a/include/hw/ppc/spapr_cpu_core.h b/include/hw/ppc/spapr_cpu_c= ore.h > index 48fb76a..980d8ae 100644 > --- a/include/hw/ppc/spapr_cpu_core.h > +++ b/include/hw/ppc/spapr_cpu_core.h > @@ -25,4 +25,6 @@ typedef struct sPAPRCPUCore { > PowerPCCPU *threads; > } sPAPRCPUCore; > =20 > +void spapr_core_plug(HotplugHandler *hotplug_dev, DeviceState *dev, > + Error **errp); > #endif --=20 David Gibson | I'll have my music baroque, and my code david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_ | _way_ _around_! http://www.ozlabs.org/~dgibson --ZvvH1QDaOFG4lOZN Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAEBAgAGBQJW6OzlAAoJEGw4ysog2bOSe9gP/28ltrfV1PG8sBmiPLPeFtsC jsAE0+vVZDQAvgcAZtmZ+cN6mDgHeBStK1VbF87xiHuWelpP3pV/h+vswxxsg01R 0++PX5eitoBiWijisLkuFqq8ecrWf3tSELHP9Nhlj2vCMX6mQjQ8R7RZFfI4VXdg mubHrCBFplQnxZAtVSNFi8Tnrz/6GDwZMjyPJbgRnV/w7j/e8ZwtX9ZZpYymwUjX xjSIiFQWHEg8XlINDNMF5T3crLliFfuPRsciexce9T27B70Hbt2xqJmb22ShLiOA Ju+EiJUvtN0QQKrbY0vdjpez7EpqDmxSf8nc/lZFC4GHUmddOS+1VBzJRLtsIlxD /vhiKxgaICLVwZ45WQcnzze8/GZQdXOfBxyiF2h2L+Xsgzl1R438qEhJwaggQJOa fjgBfJJtjjJ6oBEigX3KLaAv6zpQKQYkaBeOlTTvLYzR3MhGMHa1XsIuhWL/gNoT VGefgHKdliPk/IYzK6XBCY0ZKsAxqP/DrLNjyHsUksWl3PZC6UbcmrFVJU2cchkq aD/9qJ2erZfJwenrKsqqykn099IKXsJB4JMfAoTMqQCaJy82nSCcZ+L44ptdwNFa FGGiDqX/fYk/zCfaG9VJZEfakr7Pdc/ZsaJl4t1X/sfz2F714UgHsil2eySxVVUA 8Hxegt/8fvHKiEIWjnLs =GIJ+ -----END PGP SIGNATURE----- --ZvvH1QDaOFG4lOZN--