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From: peterz@infradead.org (Peter Zijlstra)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH V1] perf: qcom: Add L3 cache PMU driver
Date: Mon, 21 Mar 2016 10:04:00 +0100	[thread overview]
Message-ID: <20160321090400.GQ6344@twins.programming.kicks-ass.net> (raw)
In-Reply-To: <1458333422-8963-1-git-send-email-agustinv@codeaurora.org>

On Fri, Mar 18, 2016 at 04:37:02PM -0400, Agustin Vega-Frias wrote:
> This adds a new dynamic PMU to the Perf Events framework to program
> and control the L3 cache PMUs in some Qualcomm Technologies SOCs.
> 
> The driver supports a distributed cache architecture where the overall
> cache is comprised of multiple slices each with its own PMU. The driver
> aggregates counts across the whole system to provide a global picture
> of the metrics selected by the user.

So is there never a situation where you want to profile just a single
slice?

It userspace at all aware of these slices through other means?

That is; typically we do not aggregate in-kernel like this but simply
expose each slice as a separate PMU and let userspace sort things.

  reply	other threads:[~2016-03-21  9:04 UTC|newest]

Thread overview: 13+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-03-18 20:37 [PATCH V1] perf: qcom: Add L3 cache PMU driver Agustin Vega-Frias
2016-03-21  9:04 ` Peter Zijlstra [this message]
2016-03-21 15:56   ` agustinv at codeaurora.org
2016-03-21 16:00     ` Peter Zijlstra
2016-03-21 10:35 ` Mark Rutland
2016-03-21 10:54   ` Will Deacon
2016-03-21 12:04   ` Peter Zijlstra
2016-03-21 16:37     ` agustinv at codeaurora.org
2016-03-21 16:06   ` agustinv at codeaurora.org
2016-03-22 18:33   ` agustinv at codeaurora.org
     [not found]     ` <56F26FF1.90002@arm.com>
2016-03-23 12:36       ` agustinv at codeaurora.org
2016-03-23 14:46         ` Peter Zijlstra
2016-03-22 20:48 ` Peter Zijlstra

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