From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:45894) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1alUcw-0000vw-SN for qemu-devel@nongnu.org; Thu, 31 Mar 2016 00:54:40 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1alUcs-0006Z1-LB for qemu-devel@nongnu.org; Thu, 31 Mar 2016 00:54:38 -0400 Date: Thu, 31 Mar 2016 15:55:42 +1100 From: David Gibson Message-ID: <20160331045542.GB416@voom.redhat.com> References: <1459352314-12552-1-git-send-email-clg@fr.ibm.com> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha1; protocol="application/pgp-signature"; boundary="qcHopEYAB45HaUaB" Content-Disposition: inline In-Reply-To: <1459352314-12552-1-git-send-email-clg@fr.ibm.com> Subject: Re: [Qemu-devel] [PATCH v2] spapr: compute interrupt vector address from LPCR List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: =?iso-8859-1?Q?C=E9dric?= Le Goater Cc: Thomas Huth , qemu-ppc@nongnu.org, qemu-devel@nongnu.org, Greg Kurz --qcHopEYAB45HaUaB Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Wed, Mar 30, 2016 at 05:38:34PM +0200, C=E9dric Le Goater wrote: > This address is changed by the linux kernel using the H_SET_MODE hcall > and needs to be restored when migrating a spapr VM running in > TCG. This can be done using the AIL bits from the LPCR register. >=20 > The patch introduces a helper routine cpu_ppc_get_excp_prefix() which > returns the effective address offset of the interrupt handler > depending on the LPCR_AIL bits. The same helper can be used in the > H_SET_MODE hcall, which lets us remove the H_SET_MODE_ADDR_TRANS_* > defines. >=20 > Signed-off-by: C=E9dric Le Goater I've applied this (with Greg's minor amendments) to ppc-for-2.6), since it certainly improves behaviour, although I have a couple of queries: > --- >=20 > Changes since v1: >=20 > - moved helper routine under target-ppc/ > - moved the restore of excp_prefix under cpu_post_load() >=20 > hw/ppc/spapr_hcall.c | 13 ++----------- > include/hw/ppc/spapr.h | 5 ----- > target-ppc/cpu.h | 9 +++++++++ > target-ppc/machine.c | 20 +++++++++++++++++++- > target-ppc/translate_init.c | 14 ++++++++++++++ > 5 files changed, 44 insertions(+), 17 deletions(-) >=20 > Index: qemu-dgibson-for-2.6.git/hw/ppc/spapr_hcall.c > =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D > --- qemu-dgibson-for-2.6.git.orig/hw/ppc/spapr_hcall.c > +++ qemu-dgibson-for-2.6.git/hw/ppc/spapr_hcall.c > @@ -835,17 +835,8 @@ static target_ulong h_set_mode_resource_ > return H_P4; > } > =20 > - switch (mflags) { > - case H_SET_MODE_ADDR_TRANS_NONE: > - prefix =3D 0; > - break; > - case H_SET_MODE_ADDR_TRANS_0001_8000: > - prefix =3D 0x18000; > - break; > - case H_SET_MODE_ADDR_TRANS_C000_0000_0000_4000: > - prefix =3D 0xC000000000004000ULL; > - break; > - default: > + prefix =3D cpu_ppc_get_excp_prefix(mflags); > + if (prefix =3D=3D (target_ulong) -1ULL) { > return H_UNSUPPORTED_FLAG; > } > =20 > Index: qemu-dgibson-for-2.6.git/target-ppc/machine.c > =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D > --- qemu-dgibson-for-2.6.git.orig/target-ppc/machine.c > +++ qemu-dgibson-for-2.6.git/target-ppc/machine.c > @@ -156,12 +156,26 @@ static void cpu_pre_save(void *opaque) > } > } > =20 > + > +static int cpu_post_load_excp_prefix(CPUPPCState *env) > +{ > + int ail =3D (env->spr[SPR_LPCR] & LPCR_AIL) >> LPCR_AIL_SHIFT; > + target_ulong prefix =3D cpu_ppc_get_excp_prefix(ail); > + > + if (prefix =3D=3D (target_ulong) -1ULL) { > + return -EINVAL; > + } > + env->excp_prefix =3D prefix; > + return 0; > +} > + > static int cpu_post_load(void *opaque, int version_id) > { > PowerPCCPU *cpu =3D opaque; > CPUPPCState *env =3D &cpu->env; > int i; > target_ulong msr; > + int ret =3D 0; > =20 > /* > * We always ignore the source PVR. The user or management > @@ -201,7 +215,11 @@ static int cpu_post_load(void *opaque, i > =20 > hreg_compute_mem_idx(env); > =20 > - return 0; > + if (env->spr[SPR_LPCR] & LPCR_AIL) { > + ret =3D cpu_post_load_excp_prefix(env); > + } Why not call this unconditionally? If AIL =3D=3D 0 it will still do the right thing. Aren't there also circumstances where the exception prefix can depend on the MSR? Do those need to be handled somewhere? > + > + return ret; > } > =20 > static bool fpu_needed(void *opaque) > Index: qemu-dgibson-for-2.6.git/target-ppc/translate_init.c > =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D > --- qemu-dgibson-for-2.6.git.orig/target-ppc/translate_init.c > +++ qemu-dgibson-for-2.6.git/target-ppc/translate_init.c > @@ -8522,6 +8522,20 @@ void cpu_ppc_set_papr(PowerPCCPU *cpu) > } > } > =20 > +target_ulong cpu_ppc_get_excp_prefix(target_ulong ail) > +{ > + switch (ail) { > + case AIL_NONE: > + return 0; > + case AIL_0001_8000: > + return 0x18000; > + case AIL_C000_0000_0000_4000: > + return 0xC000000000004000ULL; > + default: > + return (target_ulong) -1ULL; > + } > +} > + > #endif /* !defined(CONFIG_USER_ONLY) */ > =20 > #endif /* defined (TARGET_PPC64) */ > Index: qemu-dgibson-for-2.6.git/target-ppc/cpu.h > =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D > --- qemu-dgibson-for-2.6.git.orig/target-ppc/cpu.h > +++ qemu-dgibson-for-2.6.git/target-ppc/cpu.h > @@ -1269,6 +1269,7 @@ void store_booke_tsr (CPUPPCState *env, > void ppc_tlb_invalidate_all (CPUPPCState *env); > void ppc_tlb_invalidate_one (CPUPPCState *env, target_ulong addr); > void cpu_ppc_set_papr(PowerPCCPU *cpu); > +target_ulong cpu_ppc_get_excp_prefix(target_ulong ail); > #endif > #endif > =20 > @@ -2277,6 +2278,14 @@ enum { > HMER_XSCOM_STATUS_LSH =3D (63 - 23), > }; > =20 > +/* Alternate Interrupt Location (AIL) */ > +enum { > + AIL_NONE =3D 0, > + AIL_RESERVED =3D 1, > + AIL_0001_8000 =3D 2, > + AIL_C000_0000_0000_4000 =3D 3, > +}; > + > /***********************************************************************= ******/ > =20 > static inline target_ulong cpu_read_xer(CPUPPCState *env) > Index: qemu-dgibson-for-2.6.git/include/hw/ppc/spapr.h > =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D > --- qemu-dgibson-for-2.6.git.orig/include/hw/ppc/spapr.h > +++ qemu-dgibson-for-2.6.git/include/hw/ppc/spapr.h > @@ -204,11 +204,6 @@ struct sPAPRMachineState { > #define H_SET_MODE_ENDIAN_BIG 0 > #define H_SET_MODE_ENDIAN_LITTLE 1 > =20 > -/* Flags for H_SET_MODE_RESOURCE_ADDR_TRANS_MODE */ > -#define H_SET_MODE_ADDR_TRANS_NONE 0 > -#define H_SET_MODE_ADDR_TRANS_0001_8000 2 > -#define H_SET_MODE_ADDR_TRANS_C000_0000_0000_4000 3 > - > /* VASI States */ > #define H_VASI_INVALID 0 > #define H_VASI_ENABLED 1 >=20 --=20 David Gibson | I'll have my music baroque, and my code david AT gibson.dropbear.id.au | minimalist, thank you. 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