From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755265AbcCaIdw (ORCPT ); Thu, 31 Mar 2016 04:33:52 -0400 Received: from mail.kernel.org ([198.145.29.136]:56725 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754938AbcCaIds (ORCPT ); Thu, 31 Mar 2016 04:33:48 -0400 Date: Thu, 31 Mar 2016 16:33:25 +0800 From: Shawn Guo To: Stefan Agner Cc: mturquette@baylibre.com, sboyd@codeaurora.org, kernel@pengutronix.de, sergeimir@emcraft.com, tglx@linutronix.de, jason@lakedaemon.net, marc.zyngier@arm.com, robh+dt@kernel.org, pawel.moll@arm.com, mark.rutland@arm.com, ijc+devicetree@hellion.org.uk, galak@codeaurora.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org Subject: Re: [PATCH 04/18] ARM: dts: vf610: add on-chip SRAM Message-ID: <20160331083325.GX28207@tiger> References: <1457576219-7971-1-git-send-email-stefan@agner.ch> <1457576219-7971-5-git-send-email-stefan@agner.ch> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1457576219-7971-5-git-send-email-stefan@agner.ch> User-Agent: Mutt/1.5.21 (2010-09-15) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, Mar 09, 2016 at 06:16:45PM -0800, Stefan Agner wrote: > Add Vybrids massive on-chip SRAM areas. Make use of the memory > region functionality to denominate the retained SRAM area in > LPSTOP2 and LPSTOP3. > > Signed-off-by: Stefan Agner This one looks fine to me. I was going to pick it up separately, but it doesn't apply. Shawn > --- > arch/arm/boot/dts/vfxxx.dtsi | 37 +++++++++++++++++++++++++++++++++++++ > 1 file changed, 37 insertions(+) > > diff --git a/arch/arm/boot/dts/vfxxx.dtsi b/arch/arm/boot/dts/vfxxx.dtsi > index 909988d..b038ea4 100644 > --- a/arch/arm/boot/dts/vfxxx.dtsi > +++ b/arch/arm/boot/dts/vfxxx.dtsi > @@ -91,6 +91,43 @@ > interrupt-parent = <&gpc>; > ranges; > > + ocram0: sram@3f000000 { > + compatible = "mmio-sram"; > + reg = <0x3f000000 0x40000>; > + > + #address-cells = <1>; > + #size-cells = <1>; > + ranges = <0 0x3f000000 0x40000>; > + > + stbyram1@0 { > + reg = <0x0 0x4000>; > + label = "stbyram1"; > + pool; > + }; > + > + stbyram2@4000 { > + reg = <0x4000 0xc000>; > + label = "stbyram2"; > + pool; > + }; > + }; > + > + ocram1: sram@3f040000 { > + compatible = "mmio-sram"; > + reg = <0x3f040000 0x40000>; > + }; > + > + gfxram0: sram@3f400000 { > + compatible = "mmio-sram"; > + reg = <0x3f400000 0x80000>; > + }; > + > + /* used by L2 cache */ > + gfxram1: sram@3f480000 { > + compatible = "mmio-sram"; > + reg = <0x3f480000 0x80000>; > + }; > + > aips0: aips-bus@40000000 { > compatible = "fsl,aips-bus", "simple-bus"; > #address-cells = <1>; > -- > 2.7.2 > > From mboxrd@z Thu Jan 1 00:00:00 1970 From: shawnguo@kernel.org (Shawn Guo) Date: Thu, 31 Mar 2016 16:33:25 +0800 Subject: [PATCH 04/18] ARM: dts: vf610: add on-chip SRAM In-Reply-To: <1457576219-7971-5-git-send-email-stefan@agner.ch> References: <1457576219-7971-1-git-send-email-stefan@agner.ch> <1457576219-7971-5-git-send-email-stefan@agner.ch> Message-ID: <20160331083325.GX28207@tiger> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On Wed, Mar 09, 2016 at 06:16:45PM -0800, Stefan Agner wrote: > Add Vybrids massive on-chip SRAM areas. Make use of the memory > region functionality to denominate the retained SRAM area in > LPSTOP2 and LPSTOP3. > > Signed-off-by: Stefan Agner This one looks fine to me. I was going to pick it up separately, but it doesn't apply. Shawn > --- > arch/arm/boot/dts/vfxxx.dtsi | 37 +++++++++++++++++++++++++++++++++++++ > 1 file changed, 37 insertions(+) > > diff --git a/arch/arm/boot/dts/vfxxx.dtsi b/arch/arm/boot/dts/vfxxx.dtsi > index 909988d..b038ea4 100644 > --- a/arch/arm/boot/dts/vfxxx.dtsi > +++ b/arch/arm/boot/dts/vfxxx.dtsi > @@ -91,6 +91,43 @@ > interrupt-parent = <&gpc>; > ranges; > > + ocram0: sram at 3f000000 { > + compatible = "mmio-sram"; > + reg = <0x3f000000 0x40000>; > + > + #address-cells = <1>; > + #size-cells = <1>; > + ranges = <0 0x3f000000 0x40000>; > + > + stbyram1 at 0 { > + reg = <0x0 0x4000>; > + label = "stbyram1"; > + pool; > + }; > + > + stbyram2 at 4000 { > + reg = <0x4000 0xc000>; > + label = "stbyram2"; > + pool; > + }; > + }; > + > + ocram1: sram at 3f040000 { > + compatible = "mmio-sram"; > + reg = <0x3f040000 0x40000>; > + }; > + > + gfxram0: sram at 3f400000 { > + compatible = "mmio-sram"; > + reg = <0x3f400000 0x80000>; > + }; > + > + /* used by L2 cache */ > + gfxram1: sram at 3f480000 { > + compatible = "mmio-sram"; > + reg = <0x3f480000 0x80000>; > + }; > + > aips0: aips-bus at 40000000 { > compatible = "fsl,aips-bus", "simple-bus"; > #address-cells = <1>; > -- > 2.7.2 > >